1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2011-2012 Calxeda, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/* First 4KB has pen for secondary cores. */ 9*4882a593Smuzhiyun/memreserve/ 0x00000000 0x0001000; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Calxeda Highbank"; 13*4882a593Smuzhiyun compatible = "calxeda,highbank"; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@900 { 22*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun reg = <0x900>; 25*4882a593Smuzhiyun next-level-cache = <&L2>; 26*4882a593Smuzhiyun clocks = <&a9pll>; 27*4882a593Smuzhiyun clock-names = "cpu"; 28*4882a593Smuzhiyun operating-points = < 29*4882a593Smuzhiyun /* kHz ignored */ 30*4882a593Smuzhiyun 1300000 1000000 31*4882a593Smuzhiyun 1200000 1000000 32*4882a593Smuzhiyun 1100000 1000000 33*4882a593Smuzhiyun 800000 1000000 34*4882a593Smuzhiyun 400000 1000000 35*4882a593Smuzhiyun 200000 1000000 36*4882a593Smuzhiyun >; 37*4882a593Smuzhiyun clock-latency = <100000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpu@901 { 41*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 42*4882a593Smuzhiyun device_type = "cpu"; 43*4882a593Smuzhiyun reg = <0x901>; 44*4882a593Smuzhiyun next-level-cache = <&L2>; 45*4882a593Smuzhiyun clocks = <&a9pll>; 46*4882a593Smuzhiyun clock-names = "cpu"; 47*4882a593Smuzhiyun operating-points = < 48*4882a593Smuzhiyun /* kHz ignored */ 49*4882a593Smuzhiyun 1300000 1000000 50*4882a593Smuzhiyun 1200000 1000000 51*4882a593Smuzhiyun 1100000 1000000 52*4882a593Smuzhiyun 800000 1000000 53*4882a593Smuzhiyun 400000 1000000 54*4882a593Smuzhiyun 200000 1000000 55*4882a593Smuzhiyun >; 56*4882a593Smuzhiyun clock-latency = <100000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun cpu@902 { 60*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 61*4882a593Smuzhiyun device_type = "cpu"; 62*4882a593Smuzhiyun reg = <0x902>; 63*4882a593Smuzhiyun next-level-cache = <&L2>; 64*4882a593Smuzhiyun clocks = <&a9pll>; 65*4882a593Smuzhiyun clock-names = "cpu"; 66*4882a593Smuzhiyun operating-points = < 67*4882a593Smuzhiyun /* kHz ignored */ 68*4882a593Smuzhiyun 1300000 1000000 69*4882a593Smuzhiyun 1200000 1000000 70*4882a593Smuzhiyun 1100000 1000000 71*4882a593Smuzhiyun 800000 1000000 72*4882a593Smuzhiyun 400000 1000000 73*4882a593Smuzhiyun 200000 1000000 74*4882a593Smuzhiyun >; 75*4882a593Smuzhiyun clock-latency = <100000>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun cpu@903 { 79*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 80*4882a593Smuzhiyun device_type = "cpu"; 81*4882a593Smuzhiyun reg = <0x903>; 82*4882a593Smuzhiyun next-level-cache = <&L2>; 83*4882a593Smuzhiyun clocks = <&a9pll>; 84*4882a593Smuzhiyun clock-names = "cpu"; 85*4882a593Smuzhiyun operating-points = < 86*4882a593Smuzhiyun /* kHz ignored */ 87*4882a593Smuzhiyun 1300000 1000000 88*4882a593Smuzhiyun 1200000 1000000 89*4882a593Smuzhiyun 1100000 1000000 90*4882a593Smuzhiyun 800000 1000000 91*4882a593Smuzhiyun 400000 1000000 92*4882a593Smuzhiyun 200000 1000000 93*4882a593Smuzhiyun >; 94*4882a593Smuzhiyun clock-latency = <100000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun memory@0 { 99*4882a593Smuzhiyun name = "memory"; 100*4882a593Smuzhiyun device_type = "memory"; 101*4882a593Smuzhiyun reg = <0x00000000 0xff900000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun soc { 105*4882a593Smuzhiyun ranges = <0x00000000 0x00000000 0xffffffff>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun memory-controller@fff00000 { 108*4882a593Smuzhiyun compatible = "calxeda,hb-ddr-ctrl"; 109*4882a593Smuzhiyun reg = <0xfff00000 0x1000>; 110*4882a593Smuzhiyun interrupts = <0 91 4>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun timer@fff10600 { 114*4882a593Smuzhiyun compatible = "arm,cortex-a9-twd-timer"; 115*4882a593Smuzhiyun reg = <0xfff10600 0x20>; 116*4882a593Smuzhiyun interrupts = <1 13 0xf01>; 117*4882a593Smuzhiyun clocks = <&a9periphclk>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun watchdog@fff10620 { 121*4882a593Smuzhiyun compatible = "arm,cortex-a9-twd-wdt"; 122*4882a593Smuzhiyun reg = <0xfff10620 0x20>; 123*4882a593Smuzhiyun interrupts = <1 14 0xf01>; 124*4882a593Smuzhiyun clocks = <&a9periphclk>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun intc: interrupt-controller@fff11000 { 128*4882a593Smuzhiyun compatible = "arm,cortex-a9-gic"; 129*4882a593Smuzhiyun #interrupt-cells = <3>; 130*4882a593Smuzhiyun interrupt-controller; 131*4882a593Smuzhiyun reg = <0xfff11000 0x1000>, 132*4882a593Smuzhiyun <0xfff10100 0x100>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun L2: cache-controller { 136*4882a593Smuzhiyun compatible = "arm,pl310-cache"; 137*4882a593Smuzhiyun reg = <0xfff12000 0x1000>; 138*4882a593Smuzhiyun interrupts = <0 70 4>; 139*4882a593Smuzhiyun cache-unified; 140*4882a593Smuzhiyun cache-level = <2>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun pmu { 144*4882a593Smuzhiyun compatible = "arm,cortex-a9-pmu"; 145*4882a593Smuzhiyun interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun sregs@fff3c200 { 150*4882a593Smuzhiyun compatible = "calxeda,hb-sregs-l2-ecc"; 151*4882a593Smuzhiyun reg = <0xfff3c200 0x100>; 152*4882a593Smuzhiyun interrupts = <0 71 4>, <0 72 4>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun/include/ "ecx-common.dtsi" 159