1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2011-2012 Calxeda, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/* First 4KB has pen for secondary cores. */ 9*4882a593Smuzhiyun/memreserve/ 0x00000000 0x0001000; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Calxeda ECX-2000"; 13*4882a593Smuzhiyun compatible = "calxeda,ecx-2000"; 14*4882a593Smuzhiyun #address-cells = <2>; 15*4882a593Smuzhiyun #size-cells = <2>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun clocks = <&a9pll>; 26*4882a593Smuzhiyun clock-names = "cpu"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun cpu@1 { 30*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 31*4882a593Smuzhiyun device_type = "cpu"; 32*4882a593Smuzhiyun reg = <1>; 33*4882a593Smuzhiyun clocks = <&a9pll>; 34*4882a593Smuzhiyun clock-names = "cpu"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun cpu@2 { 38*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 39*4882a593Smuzhiyun device_type = "cpu"; 40*4882a593Smuzhiyun reg = <2>; 41*4882a593Smuzhiyun clocks = <&a9pll>; 42*4882a593Smuzhiyun clock-names = "cpu"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun cpu@3 { 46*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 47*4882a593Smuzhiyun device_type = "cpu"; 48*4882a593Smuzhiyun reg = <3>; 49*4882a593Smuzhiyun clocks = <&a9pll>; 50*4882a593Smuzhiyun clock-names = "cpu"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun memory@0 { 55*4882a593Smuzhiyun name = "memory"; 56*4882a593Smuzhiyun device_type = "memory"; 57*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x00000000 0xff800000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun memory@200000000 { 61*4882a593Smuzhiyun name = "memory"; 62*4882a593Smuzhiyun device_type = "memory"; 63*4882a593Smuzhiyun reg = <0x00000002 0x00000000 0x00000003 0x00000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun soc { 67*4882a593Smuzhiyun ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun timer { 70*4882a593Smuzhiyun compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, 71*4882a593Smuzhiyun <1 14 0xf08>, 72*4882a593Smuzhiyun <1 11 0xf08>, 73*4882a593Smuzhiyun <1 10 0xf08>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun memory-controller@fff00000 { 77*4882a593Smuzhiyun compatible = "calxeda,ecx-2000-ddr-ctrl"; 78*4882a593Smuzhiyun reg = <0xfff00000 0x1000>; 79*4882a593Smuzhiyun interrupts = <0 91 4>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun intc: interrupt-controller@fff11000 { 83*4882a593Smuzhiyun compatible = "arm,cortex-a15-gic"; 84*4882a593Smuzhiyun #interrupt-cells = <3>; 85*4882a593Smuzhiyun #address-cells = <0>; 86*4882a593Smuzhiyun interrupt-controller; 87*4882a593Smuzhiyun interrupts = <1 9 0xf04>; 88*4882a593Smuzhiyun reg = <0xfff11000 0x1000>, 89*4882a593Smuzhiyun <0xfff12000 0x2000>, 90*4882a593Smuzhiyun <0xfff14000 0x2000>, 91*4882a593Smuzhiyun <0xfff16000 0x2000>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pmu { 95*4882a593Smuzhiyun compatible = "arm,cortex-a9-pmu"; 96*4882a593Smuzhiyun interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun/include/ "ecx-common.dtsi" 102