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/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dclk-vco-pll.c9 * VCO-PLL clock implementation
12 #define pr_fmt(fmt) "clk-vco-pll: " fmt
21 * DOC: VCO-PLL clock
23 * VCO and PLL rate are derived from following equations:
26 * vco = (2 * M[15:8] * Fin)/N
29 * vco = (2 * M[15:0] * Fin)/(256 * N)
33 * vco and pll are very closely bound to each other, "vco needs to program:
37 * clk_register_vco_pll() registers instances of both vco & pll.
39 * set_rate to vco. A single rate table exists for both the clocks, which
97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
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/OK3568_Linux_fs/kernel/drivers/clk/versatile/
H A Dclk-icst.c3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
37 * struct clk_icst - ICST VCO clock wrapper
39 * @vcoreg: VCO register address
40 * @lockreg: VCO lock register address
58 * vco_get() - get ICST VCO settings from a certain ICST
60 * @vco: the VCO struct to return the value in
62 static int vco_get(struct clk_icst *icst, struct icst_vco *vco) in vco_get() argument
80 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
81 vco->r = 22; in vco_get()
82 vco->s = 1; in vco_get()
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H A Dicst.c27 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) in icst_hz() argument
29 u64 dividend = p->ref * 2 * (u64)(vco.v + 8); in icst_hz()
30 u32 divisor = (vco.r + 2) * p->s2div[vco.s]; in icst_hz()
49 struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; in icst_hz_to_vco() local
66 return vco; in icst_hz_to_vco()
68 vco.s = p->idx2s[i]; in icst_hz_to_vco()
91 vco.v = vd - 8; in icst_hz_to_vco()
92 vco.r = rd - 2; in icst_hz_to_vco()
99 return vco; in icst_hz_to_vco()
H A Dclk-icst.h18 * struct clk_icst_desc - descriptor for the ICST VCO
20 * @vco_offset: offset to the ICST VCO from the provided memory base
21 * @lock_offset: offset to the ICST VCO locking register from the provided
/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c75 int temp, vco = 0, bootmod_ccr, pdr; in setup_5441x_clocks() local
107 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
109 gd->arch.vco_clk = vco; in setup_5441x_clocks()
115 gd->cpu_clk = vco / temp; /* cpu clock */ in setup_5441x_clocks()
116 gd->arch.flb_clk = vco / temp; /* FlexBus clock */ in setup_5441x_clocks()
122 gd->bus_clk = vco / temp; /* bus clock */ in setup_5441x_clocks()
134 int vco = 0, temp, fbtemp, pcrvalue; in setup_5445x_clocks() local
196 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
198 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in setup_5445x_clocks()
205 vco = i * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c226 unsigned int vco; in intel_hpll_vco() local
246 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
247 if (vco == 0) in intel_hpll_vco()
248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
253 return vco; in intel_hpll_vco()
268 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
277 switch (cdclk_config->vco) { in g33_get_cdclk()
294 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
300 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c54 * Put all plls VCO registers back to reset value (bandgap power down).
105 /* Put all plls VCO registers back to reset value. */ in cm_basic_init()
108 &clock_manager_base->main_pll.vco); in cm_basic_init()
111 &clock_manager_base->per_pll.vco); in cm_basic_init()
114 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
130 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
131 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
138 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
139 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
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H A Dclock_manager_arria10.c164 /* calculate the intended main VCO frequency based on handoff */
170 /* Check main VCO clock source: eosc, intosc or f2s? */ in cm_calc_handoff_main_vco_clk_hz()
185 /* calculate the VCO frequency */ in cm_calc_handoff_main_vco_clk_hz()
192 /* calculate the intended periph VCO frequency based on handoff */
198 /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ in cm_calc_handoff_periph_vco_clk_hz()
217 /* calculate the VCO frequency */ in cm_calc_handoff_periph_vco_clk_hz()
419 /* Check main VCO clock source: eosc, intosc or f2s? */ in cm_calc_safe_pll_numer()
434 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ in cm_calc_safe_pll_numer()
529 * Put all plls VCO registers back to reset value (bgpwr dwn).
580 * Put all plls VCO registers back to reset value. in cm_full_cfg()
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/OK3568_Linux_fs/kernel/drivers/clk/berlin/
H A Dberlin2-avpll.c19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
26 * Also, here and there the VCO registers are a bit different with
115 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
127 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_enable() local
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
142 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_disable() local
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/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c76 int vco, temp, pcrvalue, pfdr; in get_clocks() local
91 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
92 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in get_clocks()
97 vco = in get_clocks()
101 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
104 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
105 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
114 gd->cpu_clk = vco / temp; /* cpu clock */ in get_clocks()
117 gd->arch.flb_clk = vco / temp; /* flexbus clock */ in get_clocks()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-si544.c45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
223 u64 vco; in si544_calc_muldiv() local
248 vco = FVCO_MIN + ls_freq - 1; in si544_calc_muldiv()
249 do_div(vco, ls_freq); in si544_calc_muldiv()
250 settings->hs_div = vco; in si544_calc_muldiv()
257 /* Calculate VCO frequency (in 10..12GHz range) */ in si544_calc_muldiv()
258 vco = (u64)ls_freq * settings->hs_div; in si544_calc_muldiv()
261 tmp = do_div(vco, FXO); in si544_calc_muldiv()
262 settings->fb_div_int = vco; in si544_calc_muldiv()
265 vco = (u64)tmp << 32; in si544_calc_muldiv()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.h72 #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
73 #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
74 #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
75 #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
76 #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
77 #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
78 #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
79 #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
80 #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
81 #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
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/OK3568_Linux_fs/kernel/drivers/clk/pistachio/
H A Dclk-pll.c199 u64 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_frac_set_rate() local
209 /* calculate vco */ in pll_gf40lp_frac_set_rate()
210 vco = params->fref; in pll_gf40lp_frac_set_rate()
211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
212 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
214 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) in pll_gf40lp_frac_set_rate()
215 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, in pll_gf40lp_frac_set_rate()
222 if (val > vco / 16) in pll_gf40lp_frac_set_rate()
224 name, val, vco / 16); in pll_gf40lp_frac_set_rate()
356 u32 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_laint_set_rate() local
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/OK3568_Linux_fs/kernel/drivers/media/tuners/
H A Dfc0011.c21 FC11_REG_VCO, /* VCO */
22 FC11_REG_VCOSEL, /* VCO select */
30 FC11_REG_VCOCAL, /* VCO calibrate */
39 FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
40 FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
51 FC11_VCOCAL_RUN = 0, /* VCO calibration run */
52 FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
53 FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
54 FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
132 /* Initiate VCO calibration */
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
167 /* Calc VCO at full accuracy */ in ProgramClock()
172 * Check it's within restricted VCO range in ProgramClock()
175 * against VCO limit in ProgramClock()
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/OK3568_Linux_fs/kernel/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c42 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
45 /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
131 * @vco_rate: pointer to a u64 to store the computed VCO rate into
136 * desired target VCO rate into the variable pointed to by @vco_rate.
225 u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; in wrpll_configure_for_rate() local
254 /* Calculate the Q shift and target VCO rate */ in wrpll_configure_for_rate()
279 vco = vco_pre * f; in wrpll_configure_for_rate()
282 if (vco > target_vco_rate) { in wrpll_configure_for_rate()
284 vco = vco_pre * f; in wrpll_configure_for_rate()
285 } else if (vco < MIN_VCO_FREQ) { in wrpll_configure_for_rate()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/matrox/
H A Dg450_pll.c106 unsigned int *vco, unsigned int fout) in g450_firstpll() argument
114 *vco = vcomax; in g450_firstpll()
116 *vco = fout; in g450_firstpll()
131 *vco = tvco; in g450_firstpll()
133 return g450_nextpll(minfo, pi, vco, 0xFF0000 | p); in g450_firstpll()
437 unsigned int vco; in __g450_setclk() local
440 vco = g450_mnp2vco(minfo, mnp); in __g450_setclk()
441 delta = pll_freq_delta(fout, g450_vco2f(mnp, vco)); in __g450_setclk()
444 sorted equally good frequencies from lower VCO in __g450_setclk()
448 /* all else being equal except VCO, in __g450_setclk()
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/OK3568_Linux_fs/external/xserver/hw/xfree86/ramdac/
H A DIBM.c46 unsigned long MinClock, /* Min VCO rating */ in IBMramdac640CalculateMNPCForClock()
47 unsigned long MaxClock, /* Max VCO rating */ in IBMramdac640CalculateMNPCForClock()
55 unsigned long IntRef, VCO, Clock; in IBMramdac640CalculateMNPCForClock() local
64 VCO = IntRef * (M + 1); in IBMramdac640CalculateMNPCForClock()
65 if ((VCO < MinClock) || (VCO > MaxClock)) in IBMramdac640CalculateMNPCForClock()
87 *rC = (VCO <= 1280000 ? 1 : 2); in IBMramdac640CalculateMNPCForClock()
106 unsigned long MinClock, /* Min VCO rating */ in IBMramdac526CalculateMNPCForClock()
107 unsigned long MaxClock, /* Max VCO rating */ in IBMramdac526CalculateMNPCForClock()
115 unsigned long IntRef, VCO, Clock; in IBMramdac526CalculateMNPCForClock() local
124 VCO = IntRef * (M + 1); in IBMramdac526CalculateMNPCForClock()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dfsl,plldig.yaml30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
H A Darm,syscon-icst.yaml73 description: Parent clock for the ICST VCO
83 vco-offset:
85 description: Offset to the VCO register for the oscillator
100 vco-offset = <0x00>;
/OK3568_Linux_fs/kernel/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c25 * fractional divide ratio) and 3 (VCO config).
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
30 * When this happens, we remember which VCO configuration produced the lock
34 * If we do not see a PLL lock on any standard VCO config, we fall back on an
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
58 /* This table stores the synthesizer fractional divide ratio for *all* VCO
78 /* Here is the data for all the standard VCO configurations. We shrink our
206 /* The VCO configuration for autocal (all channels) */
235 /* index into synth/VCO config tables where PLL lock was found
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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-iproc-pll.c37 /* number of VCO frequency bands */
125 * Based on the target frequency, find a match from the VCO frequency parameter
287 struct iproc_pll_vco_param *vco) in pll_fractional_change_only() argument
303 if (ndiv_int != vco->ndiv_int) in pll_fractional_change_only()
309 if (pdiv != vco->pdiv) in pll_fractional_change_only()
315 static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco, in pll_set_rate() argument
321 unsigned long rate = vco->rate; in pll_set_rate()
331 if (vco->pdiv == 0) in pll_set_rate()
334 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
336 /* determine Ki and Kp index based on target VCO frequency */ in pll_set_rate()
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c31 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; in get_pllfreq() local
47 /* The formula for VCO is from TR manual, rev. D */ in get_pllfreq()
48 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); in get_pllfreq()
65 fout = vco / (dfs_mfi + (dfs_mfn / 256)); in get_pllfreq()
67 fout = vco / plldv_rfdphi_div; in get_pllfreq()
75 fout = vco / plldv_rfdphi_div; in get_pllfreq()
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dstb6100.c74 [STB6100_VCO] = "VCO",
348 /* PLL Loop disabled, bias on, VCO on, synth on */ in stb6100_set_frequency()
356 /* VCO divide ratio (LO divide ratio, VCO prescaler enable). */ in stb6100_set_frequency()
362 /* VCO enabled, search clock off as per LL3.7, 3.4.1 */ in stb6100_set_frequency()
383 /* F(VCO) = F(LO) * (ODIV == 0 ? 2 : 4) */ in stb6100_set_frequency()
385 /* N(I) = floor(f(VCO) / (f(XTAL) * (PSD2 ? 2 : 1))) */ in stb6100_set_frequency()
387 /* N(F) = round(f(VCO) / f(XTAL) * (PSD2 ? 2 : 1) - N(I)) * 2 ^ 9 */ in stb6100_set_frequency()
450 regs[STB6100_LPEN] = 0xfb; /* PLL Loop enabled, bias on, VCO on, synth on */ in stb6100_set_frequency()
458 regs[STB6100_VCO] &= ~STB6100_VCO_OCK; /* VCO fast search */ in stb6100_set_frequency()
465 regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */ in stb6100_set_frequency()
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A D4xx.c419 u32 cpu, plb, opb, ebc, vco; in __ibm440eplike_fixup_clocks() local
446 vco = sys_clk * m; in __ibm440eplike_fixup_clocks()
447 clk_a = vco / fwdva; in __ibm440eplike_fixup_clocks()
448 clk_b = vco / fwdvb; in __ibm440eplike_fixup_clocks()
452 vco = 0; in __ibm440eplike_fixup_clocks()
749 u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1; in ibm405ex_fixup_clocks() local
751 /* PLL's VCO is the source for primary forward ? */ in ibm405ex_fixup_clocks()
774 vco = (unsigned int)(sys_clk * m); in ibm405ex_fixup_clocks()
778 vco = 0; in ibm405ex_fixup_clocks()
781 /* CPU = VCO / ( FWDVA x CPUDV0) */ in ibm405ex_fixup_clocks()
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