1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/processor.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/immap.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Low Power Divider specifications
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
21*4882a593Smuzhiyun #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define CLOCK_PLL_FVCO_MAX 540000000
24*4882a593Smuzhiyun #define CLOCK_PLL_FVCO_MIN 300000000
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define CLOCK_PLL_FSYS_MAX 266666666
27*4882a593Smuzhiyun #define CLOCK_PLL_FSYS_MIN 100000000
28*4882a593Smuzhiyun #define MHZ 1000000
29*4882a593Smuzhiyun
clock_enter_limp(int lpdiv)30*4882a593Smuzhiyun void clock_enter_limp(int lpdiv)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun ccm_t *ccm = (ccm_t *)MMAP_CCM;
33*4882a593Smuzhiyun int i, j;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Check bounds of divider */
36*4882a593Smuzhiyun if (lpdiv < CLOCK_LPD_MIN)
37*4882a593Smuzhiyun lpdiv = CLOCK_LPD_MIN;
38*4882a593Smuzhiyun if (lpdiv > CLOCK_LPD_MAX)
39*4882a593Smuzhiyun lpdiv = CLOCK_LPD_MAX;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Round divider down to nearest power of two */
42*4882a593Smuzhiyun for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Apply the divider to the system clock */
45*4882a593Smuzhiyun clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Enable Limp Mode */
48*4882a593Smuzhiyun setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * brief Exit Limp mode
53*4882a593Smuzhiyun * warning The PLL should be set and locked prior to exiting Limp mode
54*4882a593Smuzhiyun */
clock_exit_limp(void)55*4882a593Smuzhiyun void clock_exit_limp(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun ccm_t *ccm = (ccm_t *)MMAP_CCM;
58*4882a593Smuzhiyun pll_t *pll = (pll_t *)MMAP_PLL;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Exit Limp mode */
61*4882a593Smuzhiyun clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Wait for the PLL to lock */
64*4882a593Smuzhiyun while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
65*4882a593Smuzhiyun ;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * get_clocks() fills in gd->cpu_clock and gd->bus_clk
70*4882a593Smuzhiyun */
get_clocks(void)71*4882a593Smuzhiyun int get_clocks(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun ccm_t *ccm = (ccm_t *)MMAP_CCM;
75*4882a593Smuzhiyun pll_t *pll = (pll_t *)MMAP_PLL;
76*4882a593Smuzhiyun int vco, temp, pcrvalue, pfdr;
77*4882a593Smuzhiyun u8 bootmode;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
80*4882a593Smuzhiyun pfdr = pcrvalue >> 24;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (pfdr == 0x1E)
83*4882a593Smuzhiyun bootmode = 0; /* Normal Mode */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifdef CONFIG_CF_SBF
86*4882a593Smuzhiyun bootmode = 3; /* Serial Mode */
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (bootmode == 0) {
90*4882a593Smuzhiyun /* Normal mode */
91*4882a593Smuzhiyun vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
92*4882a593Smuzhiyun if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
93*4882a593Smuzhiyun /* Default value */
94*4882a593Smuzhiyun pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
95*4882a593Smuzhiyun pcrvalue |= 0x1E << 24;
96*4882a593Smuzhiyun out_be32(&pll->pcr, pcrvalue);
97*4882a593Smuzhiyun vco =
98*4882a593Smuzhiyun ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
99*4882a593Smuzhiyun CONFIG_SYS_INPUT_CLKSRC;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun gd->arch.vco_clk = vco; /* Vco clock */
102*4882a593Smuzhiyun } else if (bootmode == 3) {
103*4882a593Smuzhiyun /* serial mode */
104*4882a593Smuzhiyun vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
105*4882a593Smuzhiyun gd->arch.vco_clk = vco; /* Vco clock */
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
109*4882a593Smuzhiyun /* Limp mode */
110*4882a593Smuzhiyun } else {
111*4882a593Smuzhiyun gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
114*4882a593Smuzhiyun gd->cpu_clk = vco / temp; /* cpu clock */
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
117*4882a593Smuzhiyun gd->arch.flb_clk = vco / temp; /* flexbus clock */
118*4882a593Smuzhiyun gd->bus_clk = gd->arch.flb_clk;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_FSL
122*4882a593Smuzhiyun gd->arch.i2c1_clk = gd->bus_clk;
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return (0);
126*4882a593Smuzhiyun }
127