54  * Put all plls VCO registers back to reset value (bandgap power down).
105 	/* Put all plls VCO registers back to reset value. */  in cm_basic_init()
108 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
111 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
114 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
129 	readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
130 	readl(&clock_manager_base->per_pll.vco);  in cm_basic_init()
131 	readl(&clock_manager_base->sdr_pll.vco);  in cm_basic_init()
138 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);  in cm_basic_init()
139 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);  in cm_basic_init()
140 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
188 	/* 7 us must have elapsed before we can enable the VCO */  in cm_basic_init()
192 	/* Enable vco */  in cm_basic_init()
193 	/* main pll vco */  in cm_basic_init()
195 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
199 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
201 	/* sdram pll vco */  in cm_basic_init()
203 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
236 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
240 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
242 	u32 periphvco = readl(&clock_manager_base->per_pll.vco);  in cm_basic_init()
246 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
251 		&clock_manager_base->sdr_pll.vco);  in cm_basic_init()
255 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
259 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
263 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
324 	/* get the main VCO clock */  in cm_get_main_vco_clk_hz()
325 	reg = readl(&clock_manager_base->main_pll.vco);  in cm_get_main_vco_clk_hz()
340 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
350 	/* get the PER VCO clock */  in cm_get_per_vco_clk_hz()
351 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
379 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()
389 	/* get the SDRAM VCO clock */  in cm_get_sdram_clk_hz()
390 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()