1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM System Controller ICST Clocks 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Linus Walleij <linusw@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The ICS525 and ICS307 oscillators are produced by Integrated 14*4882a593Smuzhiyun Devices Technology (IDT). ARM integrated these oscillators deeply into their 15*4882a593Smuzhiyun reference designs by adding special control registers that manage such 16*4882a593Smuzhiyun oscillators to their system controllers. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun The various ARM system controllers contain logic to serialize and initialize 19*4882a593Smuzhiyun an ICST clock request after a write to the 32 bit register at an offset 20*4882a593Smuzhiyun into the system controller. Furthermore, to even be able to alter one of 21*4882a593Smuzhiyun these frequencies, the system controller must first be unlocked by 22*4882a593Smuzhiyun writing a special token to another offset in the system controller. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun Some ARM hardware contain special versions of the serial interface that only 25*4882a593Smuzhiyun connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to 26*4882a593Smuzhiyun different values and sometimes also hard-wires the output divider. They 27*4882a593Smuzhiyun therefore have special compatible strings as per this table (the OD value is 28*4882a593Smuzhiyun the value on the pins, not the resulting output divider). 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun In the core modules and logic tiles, the ICST is a configurable clock fed 31*4882a593Smuzhiyun from a 24 MHz clock on the motherboard (usually the main crystal) used for 32*4882a593Smuzhiyun generating e.g. video clocks. It is located on the core module and there is 33*4882a593Smuzhiyun only one of these. This clock node must be a subnode of the core module. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun Hardware variant RDW OD VDW 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun Integrator/AP 22 1 Bit 8 0, rest variable 38*4882a593Smuzhiyun integratorap-cm 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun Integrator/AP 46 3 Bit 8 0, rest variable 41*4882a593Smuzhiyun integratorap-sys 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun Integrator/AP 22 or 1 17 or (33 or 25 MHz) 44*4882a593Smuzhiyun integratorap-pci 14 1 14 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun Integrator/CP 22 variable Bit 8 0, rest variable 47*4882a593Smuzhiyun integratorcp-cm-core 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun Integrator/CP 22 variable Bit 8 0, rest variable 50*4882a593Smuzhiyun integratorcp-cm-mem 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun The ICST oscillator must be provided inside a system controller node. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunproperties: 55*4882a593Smuzhiyun "#clock-cells": 56*4882a593Smuzhiyun const: 0 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun compatible: 59*4882a593Smuzhiyun enum: 60*4882a593Smuzhiyun - arm,syscon-icst525 61*4882a593Smuzhiyun - arm,syscon-icst307 62*4882a593Smuzhiyun - arm,syscon-icst525-integratorap-cm 63*4882a593Smuzhiyun - arm,syscon-icst525-integratorap-sys 64*4882a593Smuzhiyun - arm,syscon-icst525-integratorap-pci 65*4882a593Smuzhiyun - arm,syscon-icst525-integratorcp-cm-core 66*4882a593Smuzhiyun - arm,syscon-icst525-integratorcp-cm-mem 67*4882a593Smuzhiyun - arm,integrator-cm-auxosc 68*4882a593Smuzhiyun - arm,versatile-cm-auxosc 69*4882a593Smuzhiyun - arm,impd-vco1 70*4882a593Smuzhiyun - arm,impd-vco2 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun clocks: 73*4882a593Smuzhiyun description: Parent clock for the ICST VCO 74*4882a593Smuzhiyun maxItems: 1 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun clock-output-names: 77*4882a593Smuzhiyun maxItems: 1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun lock-offset: 80*4882a593Smuzhiyun $ref: '/schemas/types.yaml#/definitions/uint32' 81*4882a593Smuzhiyun description: Offset to the unlocking register for the oscillator 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vco-offset: 84*4882a593Smuzhiyun $ref: '/schemas/types.yaml#/definitions/uint32' 85*4882a593Smuzhiyun description: Offset to the VCO register for the oscillator 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunrequired: 88*4882a593Smuzhiyun - "#clock-cells" 89*4882a593Smuzhiyun - compatible 90*4882a593Smuzhiyun - clocks 91*4882a593Smuzhiyun 92*4882a593SmuzhiyunadditionalProperties: false 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunexamples: 95*4882a593Smuzhiyun - | 96*4882a593Smuzhiyun vco1: clock { 97*4882a593Smuzhiyun compatible = "arm,impd1-vco1"; 98*4882a593Smuzhiyun #clock-cells = <0>; 99*4882a593Smuzhiyun lock-offset = <0x08>; 100*4882a593Smuzhiyun vco-offset = <0x00>; 101*4882a593Smuzhiyun clocks = <&sysclk>; 102*4882a593Smuzhiyun clock-output-names = "IM-PD1-VCO1"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun... 106