Searched +full:0 +full:x01c21000 (Results 1 – 17 of 17) sorted by relevance
13 #define I2C_BASE 0x01c2100015 #define I2C_BASE 0x01c22000
36 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)37 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)38 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)39 #define DAVINCI_UART0_BASE (0x01c20000)40 #define DAVINCI_UART1_BASE (0x01c20400)41 #define DAVINCI_TIMER3_BASE (0x01c20800)42 #define DAVINCI_I2C_BASE (0x01c21000)43 #define DAVINCI_TIMER0_BASE (0x01c21400)44 #define DAVINCI_TIMER1_BASE (0x01c21800)45 #define DAVINCI_WDOG_BASE (0x01c21c00)[all …]
17 const: 0112 #sound-dai-cells = <0>;114 reg = <0x01c21000 0x40>;118 dmas = <&dma 0 2>, <&dma 0 2>;
60 reg = <0x01c20e00 0xc>;67 #sound-dai-cells = <0>;69 reg = <0x01c21000 0x400>;80 #sound-dai-cells = <0>;82 reg = <0x01c22400 0x400>;
86 #clock-cells = <0>;94 #clock-cells = <0>;117 reg = <0x01000000 0x10000>;128 compatible = "allwinner,sun8i-h3-de2-mixer-0";129 reg = <0x01100000 0x100000>;138 #size-cells = <0>;152 reg = <0x01c02000 0x1000>;162 reg = <0x01c0c000 0x1000>;171 #size-cells = <0>;173 tcon0_in: port@0 {[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;216 #clock-cells = <0>;224 #clock-cells = <0>;241 #clock-cells = <0>;248 #clock-cells = <0>;255 #clock-cells = <0>;257 reg = <0x01c200d0 0x4>;277 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
52 #define DA8XX_CP_INTC_BASE 0xfffee00056 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)58 #define DA8XX_JTAG_ID_REG 0x1859 #define DA8XX_HOST1CFG_REG 0x4460 #define DA8XX_CHIPSIG_REG 0x17461 #define DA8XX_CFGCHIP0_REG 0x17c62 #define DA8XX_CFGCHIP1_REG 0x18063 #define DA8XX_CFGCHIP2_REG 0x18464 #define DA8XX_CFGCHIP3_REG 0x18865 #define DA8XX_CFGCHIP4_REG 0x18c[all …]
24 #define DAVINCI_I2C_BASE 0x01C2100025 #define DAVINCI_ATA_BASE 0x01C6600026 #define DAVINCI_MMCSD0_BASE 0x01E1000027 #define DM355_MMCSD0_BASE 0x01E1100028 #define DM355_MMCSD1_BASE 0x01E0000029 #define DM365_MMCSD0_BASE 0x01D1100030 #define DM365_MMCSD1_BASE 0x01D0000037 0x800); in davinci_map_sysmod()49 .end = DAVINCI_I2C_BASE + 0x40,77 .end = DAVINCI_ATA_BASE + 0x7ff,[all …]
30 #define DA8XX_TPCC_BASE 0x01c0000031 #define DA8XX_TPTC0_BASE 0x01c0800032 #define DA8XX_TPTC1_BASE 0x01c0840033 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */34 #define DA8XX_I2C0_BASE 0x01c2200035 #define DA8XX_RTC_BASE 0x01c2300036 #define DA8XX_PRUSS_MEM_BASE 0x01c3000037 #define DA8XX_MMCSD0_BASE 0x01c4000038 #define DA8XX_SPI0_BASE 0x01c4100039 #define DA830_SPI1_BASE 0x01e12000[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;78 #clock-cells = <0>;80 clock-frequency = <0>;84 #clock-cells = <0>;86 reg = <0x01c20050 0x4>;93 #clock-cells = <0>;100 osc32k: clk@0 {101 #clock-cells = <0>;[all …]
64 framebuffer@0 {110 #size-cells = <0>;111 cpu0: cpu@0 {114 reg = <0x0>;125 cooling-min-level = <0>;163 reg = <0x40000000 0x80000000>;178 #clock-cells = <0>;180 clock-frequency = <0>;184 #clock-cells = <0>;186 reg = <0x01c20050 0x4>;[all …]
66 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;119 cooling-min-level = <0>;163 reg = <0x40000000 0x80000000>;186 #clock-cells = <0>;188 reg = <0x01c20050 0x4>;194 #clock-cells = <0>;202 osc32k: clk@0 {[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]