1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mach-davinci/devices.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * DaVinci platform device setup/initialization
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/platform_data/i2c-davinci.h>
11*4882a593Smuzhiyun #include <linux/platform_data/mmc-davinci.h>
12*4882a593Smuzhiyun #include <linux/platform_data/edma.h>
13*4882a593Smuzhiyun #include <linux/dma-mapping.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/reboot.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <mach/hardware.h>
18*4882a593Smuzhiyun #include <mach/cputype.h>
19*4882a593Smuzhiyun #include <mach/mux.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "davinci.h"
22*4882a593Smuzhiyun #include "irqs.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define DAVINCI_I2C_BASE 0x01C21000
25*4882a593Smuzhiyun #define DAVINCI_ATA_BASE 0x01C66000
26*4882a593Smuzhiyun #define DAVINCI_MMCSD0_BASE 0x01E10000
27*4882a593Smuzhiyun #define DM355_MMCSD0_BASE 0x01E11000
28*4882a593Smuzhiyun #define DM355_MMCSD1_BASE 0x01E00000
29*4882a593Smuzhiyun #define DM365_MMCSD0_BASE 0x01D11000
30*4882a593Smuzhiyun #define DM365_MMCSD1_BASE 0x01D00000
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun void __iomem *davinci_sysmod_base;
33*4882a593Smuzhiyun
davinci_map_sysmod(void)34*4882a593Smuzhiyun void davinci_map_sysmod(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun davinci_sysmod_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE,
37*4882a593Smuzhiyun 0x800);
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Throw a bug since a lot of board initialization code depends
40*4882a593Smuzhiyun * on system module availability. ioremap() failing this early
41*4882a593Smuzhiyun * need careful looking into anyway.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun BUG_ON(!davinci_sysmod_base);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static struct resource i2c_resources[] = {
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun .start = DAVINCI_I2C_BASE,
49*4882a593Smuzhiyun .end = DAVINCI_I2C_BASE + 0x40,
50*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
51*4882a593Smuzhiyun },
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_I2C),
54*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static struct platform_device davinci_i2c_device = {
59*4882a593Smuzhiyun .name = "i2c_davinci",
60*4882a593Smuzhiyun .id = 1,
61*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(i2c_resources),
62*4882a593Smuzhiyun .resource = i2c_resources,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
davinci_init_i2c(struct davinci_i2c_platform_data * pdata)65*4882a593Smuzhiyun void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun if (cpu_is_davinci_dm644x())
68*4882a593Smuzhiyun davinci_cfg_reg(DM644X_I2C);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun davinci_i2c_device.dev.platform_data = pdata;
71*4882a593Smuzhiyun (void) platform_device_register(&davinci_i2c_device);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static struct resource ide_resources[] = {
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun .start = DAVINCI_ATA_BASE,
77*4882a593Smuzhiyun .end = DAVINCI_ATA_BASE + 0x7ff,
78*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_IDE),
82*4882a593Smuzhiyun .end = DAVINCI_INTC_IRQ(IRQ_IDE),
83*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static u64 ide_dma_mask = DMA_BIT_MASK(32);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct platform_device ide_device = {
90*4882a593Smuzhiyun .name = "palm_bk3710",
91*4882a593Smuzhiyun .id = -1,
92*4882a593Smuzhiyun .resource = ide_resources,
93*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ide_resources),
94*4882a593Smuzhiyun .dev = {
95*4882a593Smuzhiyun .dma_mask = &ide_dma_mask,
96*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
davinci_init_ide(void)100*4882a593Smuzhiyun void __init davinci_init_ide(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun if (cpu_is_davinci_dm644x()) {
103*4882a593Smuzhiyun davinci_cfg_reg(DM644X_HPIEN_DISABLE);
104*4882a593Smuzhiyun davinci_cfg_reg(DM644X_ATAEN);
105*4882a593Smuzhiyun davinci_cfg_reg(DM644X_HDIREN);
106*4882a593Smuzhiyun } else if (cpu_is_davinci_dm646x()) {
107*4882a593Smuzhiyun /* IRQ_DM646X_IDE is the same as IRQ_IDE */
108*4882a593Smuzhiyun davinci_cfg_reg(DM646X_ATAEN);
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun WARN_ON(1);
111*4882a593Smuzhiyun return;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun platform_device_register(&ide_device);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_MMC_DAVINCI)
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static struct resource mmcsd0_resources[] = {
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun /* different on dm355 */
124*4882a593Smuzhiyun .start = DAVINCI_MMCSD0_BASE,
125*4882a593Smuzhiyun .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
126*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun /* IRQs: MMC/SD, then SDIO */
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
131*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
132*4882a593Smuzhiyun }, {
133*4882a593Smuzhiyun /* different on dm355 */
134*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
135*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static struct platform_device davinci_mmcsd0_device = {
140*4882a593Smuzhiyun .name = "dm6441-mmc",
141*4882a593Smuzhiyun .id = 0,
142*4882a593Smuzhiyun .dev = {
143*4882a593Smuzhiyun .dma_mask = &mmcsd0_dma_mask,
144*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
145*4882a593Smuzhiyun },
146*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mmcsd0_resources),
147*4882a593Smuzhiyun .resource = mmcsd0_resources,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static struct resource mmcsd1_resources[] = {
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun .start = DM355_MMCSD1_BASE,
155*4882a593Smuzhiyun .end = DM355_MMCSD1_BASE + SZ_4K - 1,
156*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun /* IRQs: MMC/SD, then SDIO */
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
161*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
162*4882a593Smuzhiyun }, {
163*4882a593Smuzhiyun .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
164*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
165*4882a593Smuzhiyun },
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static struct platform_device davinci_mmcsd1_device = {
169*4882a593Smuzhiyun .name = "dm6441-mmc",
170*4882a593Smuzhiyun .id = 1,
171*4882a593Smuzhiyun .dev = {
172*4882a593Smuzhiyun .dma_mask = &mmcsd1_dma_mask,
173*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mmcsd1_resources),
176*4882a593Smuzhiyun .resource = mmcsd1_resources,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun
davinci_setup_mmc(int module,struct davinci_mmc_config * config)180*4882a593Smuzhiyun void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun struct platform_device *pdev = NULL;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (WARN_ON(cpu_is_davinci_dm646x()))
185*4882a593Smuzhiyun return;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
188*4882a593Smuzhiyun * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
189*4882a593Smuzhiyun *
190*4882a593Smuzhiyun * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
191*4882a593Smuzhiyun * not handled right here ...
192*4882a593Smuzhiyun */
193*4882a593Smuzhiyun switch (module) {
194*4882a593Smuzhiyun case 1:
195*4882a593Smuzhiyun if (cpu_is_davinci_dm355()) {
196*4882a593Smuzhiyun /* REVISIT we may not need all these pins if e.g. this
197*4882a593Smuzhiyun * is a hard-wired SDIO device...
198*4882a593Smuzhiyun */
199*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_CMD);
200*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_CLK);
201*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_DATA0);
202*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_DATA1);
203*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_DATA2);
204*4882a593Smuzhiyun davinci_cfg_reg(DM355_SD1_DATA3);
205*4882a593Smuzhiyun } else if (cpu_is_davinci_dm365()) {
206*4882a593Smuzhiyun /* Configure pull down control */
207*4882a593Smuzhiyun unsigned v;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
210*4882a593Smuzhiyun __raw_writel(v & ~0xfc0,
211*4882a593Smuzhiyun DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
214*4882a593Smuzhiyun mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
215*4882a593Smuzhiyun SZ_4K - 1;
216*4882a593Smuzhiyun mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
217*4882a593Smuzhiyun IRQ_DM365_SDIOINT1);
218*4882a593Smuzhiyun davinci_mmcsd1_device.name = "da830-mmc";
219*4882a593Smuzhiyun } else
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun pdev = &davinci_mmcsd1_device;
223*4882a593Smuzhiyun break;
224*4882a593Smuzhiyun case 0:
225*4882a593Smuzhiyun if (cpu_is_davinci_dm355()) {
226*4882a593Smuzhiyun mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
227*4882a593Smuzhiyun mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
228*4882a593Smuzhiyun mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
229*4882a593Smuzhiyun IRQ_DM355_SDIOINT0);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
232*4882a593Smuzhiyun davinci_cfg_reg(DM355_MMCSD0);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* enable RX EDMA */
235*4882a593Smuzhiyun davinci_cfg_reg(DM355_EVT26_MMC0_RX);
236*4882a593Smuzhiyun } else if (cpu_is_davinci_dm365()) {
237*4882a593Smuzhiyun mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
238*4882a593Smuzhiyun mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
239*4882a593Smuzhiyun SZ_4K - 1;
240*4882a593Smuzhiyun mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
241*4882a593Smuzhiyun IRQ_DM365_SDIOINT0);
242*4882a593Smuzhiyun davinci_mmcsd0_device.name = "da830-mmc";
243*4882a593Smuzhiyun } else if (cpu_is_davinci_dm644x()) {
244*4882a593Smuzhiyun /* REVISIT: should this be in board-init code? */
245*4882a593Smuzhiyun /* Power-on 3.3V IO cells */
246*4882a593Smuzhiyun __raw_writel(0,
247*4882a593Smuzhiyun DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
248*4882a593Smuzhiyun /*Set up the pull regiter for MMC */
249*4882a593Smuzhiyun davinci_cfg_reg(DM644X_MSTK);
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun pdev = &davinci_mmcsd0_device;
253*4882a593Smuzhiyun break;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun if (WARN_ON(!pdev))
257*4882a593Smuzhiyun return;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun pdev->dev.platform_data = config;
260*4882a593Smuzhiyun platform_device_register(pdev);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun #else
264*4882a593Smuzhiyun
davinci_setup_mmc(int module,struct davinci_mmc_config * config)265*4882a593Smuzhiyun void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun #endif
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static struct resource wdt_resources[] = {
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun .start = DAVINCI_WDOG_BASE,
276*4882a593Smuzhiyun .end = DAVINCI_WDOG_BASE + SZ_1K - 1,
277*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
278*4882a593Smuzhiyun },
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun static struct platform_device davinci_wdt_device = {
282*4882a593Smuzhiyun .name = "davinci-wdt",
283*4882a593Smuzhiyun .id = -1,
284*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(wdt_resources),
285*4882a593Smuzhiyun .resource = wdt_resources,
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun
davinci_init_wdt(void)288*4882a593Smuzhiyun int davinci_init_wdt(void)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun return platform_device_register(&davinci_wdt_device);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static struct platform_device davinci_gpio_device = {
294*4882a593Smuzhiyun .name = "davinci_gpio",
295*4882a593Smuzhiyun .id = -1,
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
davinci_gpio_register(struct resource * res,int size,void * pdata)298*4882a593Smuzhiyun int davinci_gpio_register(struct resource *res, int size, void *pdata)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun davinci_gpio_device.resource = res;
301*4882a593Smuzhiyun davinci_gpio_device.num_resources = size;
302*4882a593Smuzhiyun davinci_gpio_device.dev.platform_data = pdata;
303*4882a593Smuzhiyun return platform_device_register(&davinci_gpio_device);
304*4882a593Smuzhiyun }
305