Lines Matching +full:0 +full:x01c21000
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
228 polling-delay-passive = <0>;
229 polling-delay = <0>;
242 reg = <0x1000000 0x400000>;
246 ranges = <0 0x1000000 0x400000>;
248 display_clocks: clock@0 {
250 reg = <0x0 0x10000>;
263 reg = <0x20000 0x10000>;
273 compatible = "allwinner,sun50i-a64-de2-mixer-0";
274 reg = <0x100000 0x100000>;
283 #size-cells = <0>;
287 #size-cells = <0>;
290 mixer0_out_tcon0: endpoint@0 {
291 reg = <0>;
305 reg = <0x200000 0x100000>;
314 #size-cells = <0>;
318 #size-cells = <0>;
321 mixer1_out_tcon0: endpoint@0 {
322 reg = <0>;
337 reg = <0x01c00000 0x1000>;
344 reg = <0x00018000 0x28000>;
347 ranges = <0 0x00018000 0x28000>;
349 de2_sram: sram-section@0 {
351 reg = <0x0000 0x28000>;
357 reg = <0x01d00000 0x40000>;
360 ranges = <0 0x01d00000 0x40000>;
362 ve_sram: sram-section@0 {
365 reg = <0x000000 0x40000>;
372 reg = <0x01c02000 0x1000>;
384 reg = <0x01c0c000 0x1000>;
389 #clock-cells = <0>;
395 #size-cells = <0>;
397 tcon0_in: port@0 {
399 #size-cells = <0>;
400 reg = <0>;
402 tcon0_in_mixer0: endpoint@0 {
403 reg = <0>;
415 #size-cells = <0>;
430 reg = <0x01c0d000 0x1000>;
439 #size-cells = <0>;
441 tcon1_in: port@0 {
443 #size-cells = <0>;
444 reg = <0>;
446 tcon1_in_mixer0: endpoint@0 {
447 reg = <0>;
459 #size-cells = <0>;
472 reg = <0x01c0e000 0x1000>;
483 reg = <0x01c0f000 0x1000>;
492 #size-cells = <0>;
497 reg = <0x01c10000 0x1000>;
506 #size-cells = <0>;
511 reg = <0x01c11000 0x1000>;
520 #size-cells = <0>;
525 reg = <0x1c14000 0x400>;
530 reg = <0x34 0x8>;
536 reg = <0x01c15000 0x1000>;
546 reg = <0x01c17000 0x1000>;
555 reg = <0x01c19000 0x0400>;
560 phys = <&usbphy 0>;
562 extcon = <&usbphy 0>;
569 reg = <0x01c19400 0x14>,
570 <0x01c1a800 0x4>,
571 <0x01c1b800 0x4>;
589 reg = <0x01c1a000 0x100>;
596 phys = <&usbphy 0>;
603 reg = <0x01c1a400 0x100>;
608 phys = <&usbphy 0>;
615 reg = <0x01c1b000 0x100>;
629 reg = <0x01c1b400 0x100>;
641 reg = <0x01c20000 0x400>;
642 clocks = <&osc24M>, <&rtc 0>;
650 reg = <0x01c20800 0x400>;
654 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
802 #sound-dai-cells = <0>;
805 reg = <0x01c21000 0x400>;
813 pinctrl-0 = <&spdif_tx_pin>;
820 reg = <0x01c21800 0x400>;
826 #sound-dai-cells = <0>;
829 reg = <0x01c22000 0x400>;
840 #sound-dai-cells = <0>;
843 reg = <0x01c22400 0x400>;
854 #sound-dai-cells = <0>;
856 reg = <0x01c22c00 0x200>;
867 #sound-dai-cells = <0>;
870 reg = <0x01c22e00 0x600>;
879 reg = <0x01c25000 0x100>;
891 reg = <0x01c28000 0x400>;
892 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
902 reg = <0x01c28400 0x400>;
913 reg = <0x01c28800 0x400>;
924 reg = <0x01c28c00 0x400>;
935 reg = <0x01c29000 0x400>;
946 reg = <0x01c2ac00 0x400>;
951 pinctrl-0 = <&i2c0_pins>;
954 #size-cells = <0>;
959 reg = <0x01c2b000 0x400>;
964 pinctrl-0 = <&i2c1_pins>;
967 #size-cells = <0>;
972 reg = <0x01c2b400 0x400>;
977 pinctrl-0 = <&i2c2_pins>;
980 #size-cells = <0>;
985 reg = <0x01c68000 0x1000>;
992 pinctrl-0 = <&spi0_pins>;
997 #size-cells = <0>;
1002 reg = <0x01c69000 0x1000>;
1009 pinctrl-0 = <&spi1_pins>;
1014 #size-cells = <0>;
1020 reg = <0x01c30000 0x10000>;
1032 #size-cells = <0>;
1038 reg = <0x01c40000 0x10000>;
1060 reg = <0x01c81000 0x1000>,
1061 <0x01c82000 0x2000>,
1062 <0x01c84000 0x2000>,
1063 <0x01c86000 0x2000>;
1072 reg = <0x01c21400 0x400>;
1075 pinctrl-0 = <&pwm_pin>;
1082 reg = <0x01c62000 0x1000>;
1086 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1092 reg = <0x01cb0000 0x1000>;
1100 pinctrl-0 = <&csi_pins>;
1106 reg = <0x01ca0000 0x1000>;
1114 #size-cells = <0>;
1126 reg = <0x01ca1000 0x1000>;
1132 #phy-cells = <0>;
1138 reg = <0x01e00000 0x20000>;
1152 reg = <0x01ee0000 0x10000>;
1166 #size-cells = <0>;
1168 hdmi_in: port@0 {
1169 reg = <0>;
1184 reg = <0x01ef0000 0x10000>;
1187 clock-names = "bus", "mod", "pll-0";
1190 #phy-cells = <0>;
1196 reg = <0x01f00000 0x400>;
1209 reg = <0x01f00c00 0x400>;
1215 reg = <0x01f01400 0x100>;
1216 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1225 reg = <0x01f015c0 0x4>;
1232 reg = <0x01f02400 0x400>;
1238 #size-cells = <0>;
1244 reg = <0x01f02000 0x400>;
1250 pinctrl-0 = <&r_ir_rx_pin>;
1257 reg = <0x01f03800 0x400>;
1260 pinctrl-0 = <&r_pwm_pin>;
1267 reg = <0x01f02c00 0x400>;
1299 reg = <0x01f03400 0x400>;
1305 pinctrl-0 = <&r_rsb_pins>;
1308 #size-cells = <0>;
1314 reg = <0x01c20ca0 0x20>;