arm/mach-davinci/devices-da8xx.c

30 #define DA8XX_TPCC_BASE			0x01c00000
31 #define DA8XX_TPTC0_BASE		0x01c08000
32 #define DA8XX_TPTC1_BASE		0x01c08400
33 #define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
34 #define DA8XX_I2C0_BASE			0x01c22000
35 #define DA8XX_RTC_BASE			0x01c23000
36 #define DA8XX_PRUSS_MEM_BASE		0x01c30000
37 #define DA8XX_MMCSD0_BASE		0x01c40000
38 #define DA8XX_SPI0_BASE			0x01c41000
39 #define DA830_SPI1_BASE			0x01e12000
40 #define DA8XX_LCD_CNTRL_BASE		0x01e13000
41 #define DA850_SATA_BASE			0x01e18000
42 #define DA850_MMCSD1_BASE		0x01e1b000
43 #define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
44 #define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
45 #define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
46 #define DA8XX_EMAC_MDIO_BASE		0x01e24000
47 #define DA8XX_I2C1_BASE			0x01e28000
48 #define DA850_TPCC1_BASE		0x01e30000
49 #define DA850_TPTC2_BASE		0x01e38000
50 #define DA850_SPI1_BASE			0x01f0e000
51 #define DA8XX_DDR2_CTL_BASE		0xb0000000
53 #define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
54 #define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
55 #define DA8XX_EMAC_RAM_OFFSET		0x0000
71 		.flags	= 0,
84 		.flags	= 0,
97 		.flags	= 0,
129 	{0, 3},
136 	{0, 3},
208 	.id		= 0,
227 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
228 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
229 	{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
230 	{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
231 	{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
232 	{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
233 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
234 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
235 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
236 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
237 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
238 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
255 	{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
256 	{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
257 	{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
258 	{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
259 	{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
260 	{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
261 	{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
262 	{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
263 	{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
264 	{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
265 	{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
266 	{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
279 		da8xx_edma0_pdata.rsv = rsv[0];  in da850_register_edma()
344 	if (instance == 0)  in da8xx_register_i2c()
431 	.id		= 0,
441 	if (ret < 0)  in da8xx_register_emac()
547 	.id		= 0,
557 	case 0:  in da8xx_register_mcasp()
584 		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
630 	.pintc_base	= 0x4000,
668 	[0] = { /* registers */
682 	.id		= 0,
777 	.id		= 0,
875 		return 0;  in early_rproc_mem()
881 	return 0;  in early_rproc_mem()
898 	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",  in da8xx_rproc_reserve_cma()
901 	ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,  in da8xx_rproc_reserve_cma()
1010 	[0] = {
1023 	[0] = {
1036 	[0] = {
1051 	[0] = {
1053 		.id		= 0,
1057 			.platform_data = &da8xx_spi_pdata[0],
1073 	if (instance < 0 || instance > 1)  in da8xx_register_spi_bus()
1079 		da8xx_spi1_resources[0].start = DA850_SPI1_BASE;  in da8xx_register_spi_bus()
1080 		da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;  in da8xx_register_spi_bus()
1091 	clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);  in da850_register_sata_refclk()
1101 		.end	= DA850_SATA_BASE + 0x1fff,
1106 		.end	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,