1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2011 3*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _SUNXI_CPU_SUN4I_H 10*4882a593Smuzhiyun #define _SUNXI_CPU_SUN4I_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SUNXI_SRAM_A1_BASE 0x00000000 13*4882a593Smuzhiyun #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 16*4882a593Smuzhiyun #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 17*4882a593Smuzhiyun #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 18*4882a593Smuzhiyun #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 19*4882a593Smuzhiyun #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SUNXI_DE2_BASE 0x01000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_MACH_SUN8I_A83T 24*4882a593Smuzhiyun #define SUNXI_CPUCFG_BASE 0x01700000 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define SUNXI_SRAMC_BASE 0x01c00000 28*4882a593Smuzhiyun #define SUNXI_DRAMC_BASE 0x01c01000 29*4882a593Smuzhiyun #define SUNXI_DMA_BASE 0x01c02000 30*4882a593Smuzhiyun #define SUNXI_NFC_BASE 0x01c03000 31*4882a593Smuzhiyun #define SUNXI_TS_BASE 0x01c04000 32*4882a593Smuzhiyun #define SUNXI_SPI0_BASE 0x01c05000 33*4882a593Smuzhiyun #define SUNXI_SPI1_BASE 0x01c06000 34*4882a593Smuzhiyun #define SUNXI_MS_BASE 0x01c07000 35*4882a593Smuzhiyun #define SUNXI_TVD_BASE 0x01c08000 36*4882a593Smuzhiyun #define SUNXI_CSI0_BASE 0x01c09000 37*4882a593Smuzhiyun #ifndef CONFIG_MACH_SUNXI_H3_H5 38*4882a593Smuzhiyun #define SUNXI_TVE0_BASE 0x01c0a000 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun #define SUNXI_EMAC_BASE 0x01c0b000 41*4882a593Smuzhiyun #define SUNXI_LCD0_BASE 0x01c0C000 42*4882a593Smuzhiyun #define SUNXI_LCD1_BASE 0x01c0d000 43*4882a593Smuzhiyun #define SUNXI_VE_BASE 0x01c0e000 44*4882a593Smuzhiyun #define SUNXI_MMC0_BASE 0x01c0f000 45*4882a593Smuzhiyun #define SUNXI_MMC1_BASE 0x01c10000 46*4882a593Smuzhiyun #define SUNXI_MMC2_BASE 0x01c11000 47*4882a593Smuzhiyun #define SUNXI_MMC3_BASE 0x01c12000 48*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN4I 49*4882a593Smuzhiyun #define SUNXI_USB0_BASE 0x01c13000 50*4882a593Smuzhiyun #define SUNXI_USB1_BASE 0x01c14000 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun #define SUNXI_SS_BASE 0x01c15000 53*4882a593Smuzhiyun #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 54*4882a593Smuzhiyun #define SUNXI_HDMI_BASE 0x01c16000 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun #define SUNXI_SPI2_BASE 0x01c17000 57*4882a593Smuzhiyun #define SUNXI_SATA_BASE 0x01c18000 58*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN4I 59*4882a593Smuzhiyun #define SUNXI_PATA_BASE 0x01c19000 60*4882a593Smuzhiyun #define SUNXI_ACE_BASE 0x01c1a000 61*4882a593Smuzhiyun #define SUNXI_TVE1_BASE 0x01c1b000 62*4882a593Smuzhiyun #define SUNXI_USB2_BASE 0x01c1c000 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN6I 65*4882a593Smuzhiyun #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 66*4882a593Smuzhiyun #define SUNXI_USBPHY_BASE 0x01c19000 67*4882a593Smuzhiyun #define SUNXI_USB0_BASE 0x01c1a000 68*4882a593Smuzhiyun #define SUNXI_USB1_BASE 0x01c1b000 69*4882a593Smuzhiyun #define SUNXI_USB2_BASE 0x01c1c000 70*4882a593Smuzhiyun #define SUNXI_USB3_BASE 0x01c1d000 71*4882a593Smuzhiyun #else 72*4882a593Smuzhiyun #define SUNXI_USB0_BASE 0x01c19000 73*4882a593Smuzhiyun #define SUNXI_USB1_BASE 0x01c1a000 74*4882a593Smuzhiyun #define SUNXI_USB2_BASE 0x01c1b000 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun #define SUNXI_CSI1_BASE 0x01c1d000 78*4882a593Smuzhiyun #define SUNXI_TZASC_BASE 0x01c1e000 79*4882a593Smuzhiyun #define SUNXI_SPI3_BASE 0x01c1f000 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define SUNXI_CCM_BASE 0x01c20000 82*4882a593Smuzhiyun #define SUNXI_INTC_BASE 0x01c20400 83*4882a593Smuzhiyun #define SUNXI_PIO_BASE 0x01c20800 84*4882a593Smuzhiyun #define SUNXI_TIMER_BASE 0x01c20c00 85*4882a593Smuzhiyun #ifndef CONFIG_SUNXI_GEN_SUN6I 86*4882a593Smuzhiyun #define SUNXI_PWM_BASE 0x01c20e00 87*4882a593Smuzhiyun #endif 88*4882a593Smuzhiyun #define SUNXI_SPDIF_BASE 0x01c21000 89*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN6I 90*4882a593Smuzhiyun #define SUNXI_PWM_BASE 0x01c21400 91*4882a593Smuzhiyun #else 92*4882a593Smuzhiyun #define SUNXI_AC97_BASE 0x01c21400 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun #define SUNXI_IR0_BASE 0x01c21800 95*4882a593Smuzhiyun #define SUNXI_IR1_BASE 0x01c21c00 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define SUNXI_IIS_BASE 0x01c22400 98*4882a593Smuzhiyun #define SUNXI_LRADC_BASE 0x01c22800 99*4882a593Smuzhiyun #define SUNXI_AD_DA_BASE 0x01c22c00 100*4882a593Smuzhiyun #define SUNXI_KEYPAD_BASE 0x01c23000 101*4882a593Smuzhiyun #define SUNXI_TZPC_BASE 0x01c23400 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ 104*4882a593Smuzhiyun defined(CONFIG_MACH_SUN50I) 105*4882a593Smuzhiyun /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 106*4882a593Smuzhiyun #define SUNXI_SIDC_BASE 0x01c14000 107*4882a593Smuzhiyun #define SUNXI_SID_BASE 0x01c14200 108*4882a593Smuzhiyun #else 109*4882a593Smuzhiyun #define SUNXI_SID_BASE 0x01c23800 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define SUNXI_SJTAG_BASE 0x01c23c00 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define SUNXI_TP_BASE 0x01c25000 115*4882a593Smuzhiyun #define SUNXI_PMU_BASE 0x01c25400 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 118*4882a593Smuzhiyun #define SUNXI_CPUCFG_BASE 0x01c25c00 119*4882a593Smuzhiyun #endif 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define SUNXI_UART0_BASE 0x01c28000 122*4882a593Smuzhiyun #define SUNXI_UART1_BASE 0x01c28400 123*4882a593Smuzhiyun #define SUNXI_UART2_BASE 0x01c28800 124*4882a593Smuzhiyun #define SUNXI_UART3_BASE 0x01c28c00 125*4882a593Smuzhiyun #define SUNXI_UART4_BASE 0x01c29000 126*4882a593Smuzhiyun #define SUNXI_UART5_BASE 0x01c29400 127*4882a593Smuzhiyun #define SUNXI_UART6_BASE 0x01c29800 128*4882a593Smuzhiyun #define SUNXI_UART7_BASE 0x01c29c00 129*4882a593Smuzhiyun #define SUNXI_PS2_0_BASE 0x01c2a000 130*4882a593Smuzhiyun #define SUNXI_PS2_1_BASE 0x01c2a400 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define SUNXI_TWI0_BASE 0x01c2ac00 133*4882a593Smuzhiyun #define SUNXI_TWI1_BASE 0x01c2b000 134*4882a593Smuzhiyun #define SUNXI_TWI2_BASE 0x01c2b400 135*4882a593Smuzhiyun #ifdef CONFIG_MACH_SUN6I 136*4882a593Smuzhiyun #define SUNXI_TWI3_BASE 0x01c0b800 137*4882a593Smuzhiyun #endif 138*4882a593Smuzhiyun #ifdef CONFIG_MACH_SUN7I 139*4882a593Smuzhiyun #define SUNXI_TWI3_BASE 0x01c2b800 140*4882a593Smuzhiyun #define SUNXI_TWI4_BASE 0x01c2c000 141*4882a593Smuzhiyun #endif 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define SUNXI_CAN_BASE 0x01c2bc00 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define SUNXI_SCR_BASE 0x01c2c400 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #ifndef CONFIG_MACH_SUN6I 148*4882a593Smuzhiyun #define SUNXI_GPS_BASE 0x01c30000 149*4882a593Smuzhiyun #define SUNXI_MALI400_BASE 0x01c40000 150*4882a593Smuzhiyun #define SUNXI_GMAC_BASE 0x01c50000 151*4882a593Smuzhiyun #else 152*4882a593Smuzhiyun #define SUNXI_GMAC_BASE 0x01c30000 153*4882a593Smuzhiyun #endif 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define SUNXI_DRAM_COM_BASE 0x01c62000 156*4882a593Smuzhiyun #define SUNXI_DRAM_CTL0_BASE 0x01c63000 157*4882a593Smuzhiyun #define SUNXI_DRAM_CTL1_BASE 0x01c64000 158*4882a593Smuzhiyun #define SUNXI_DRAM_PHY0_BASE 0x01c65000 159*4882a593Smuzhiyun #define SUNXI_DRAM_PHY1_BASE 0x01c66000 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define SUNXI_GIC400_BASE 0x01c80000 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* module sram */ 164*4882a593Smuzhiyun #define SUNXI_SRAM_C_BASE 0x01d00000 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #ifndef CONFIG_MACH_SUN8I_H3 167*4882a593Smuzhiyun #define SUNXI_DE_FE0_BASE 0x01e00000 168*4882a593Smuzhiyun #else 169*4882a593Smuzhiyun #define SUNXI_TVE0_BASE 0x01e00000 170*4882a593Smuzhiyun #endif 171*4882a593Smuzhiyun #define SUNXI_DE_FE1_BASE 0x01e20000 172*4882a593Smuzhiyun #define SUNXI_DE_BE0_BASE 0x01e60000 173*4882a593Smuzhiyun #ifndef CONFIG_MACH_SUN50I_H5 174*4882a593Smuzhiyun #define SUNXI_DE_BE1_BASE 0x01e40000 175*4882a593Smuzhiyun #else 176*4882a593Smuzhiyun #define SUNXI_TVE0_BASE 0x01e40000 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun #define SUNXI_MP_BASE 0x01e80000 179*4882a593Smuzhiyun #define SUNXI_AVG_BASE 0x01ea0000 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 182*4882a593Smuzhiyun #define SUNXI_HDMI_BASE 0x01ee0000 183*4882a593Smuzhiyun #endif 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define SUNXI_RTC_BASE 0x01f00000 186*4882a593Smuzhiyun #define SUNXI_PRCM_BASE 0x01f01400 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #if defined CONFIG_SUNXI_GEN_SUN6I && \ 189*4882a593Smuzhiyun !defined CONFIG_MACH_SUN8I_A83T && \ 190*4882a593Smuzhiyun !defined CONFIG_MACH_SUN8I_R40 191*4882a593Smuzhiyun #define SUNXI_CPUCFG_BASE 0x01f01c00 192*4882a593Smuzhiyun #endif 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #define SUNXI_R_TWI_BASE 0x01f02400 195*4882a593Smuzhiyun #define SUNXI_R_UART_BASE 0x01f02800 196*4882a593Smuzhiyun #define SUNXI_R_PIO_BASE 0x01f02c00 197*4882a593Smuzhiyun #define SUN6I_P2WI_BASE 0x01f03400 198*4882a593Smuzhiyun #define SUNXI_RSB_BASE 0x01f03400 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* CoreSight Debug Module */ 201*4882a593Smuzhiyun #define SUNXI_CSDM_BASE 0x3f500000 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* SS bonding ids used for cpu identification */ 210*4882a593Smuzhiyun #define SUNXI_SS_BOND_ID_A31 4 211*4882a593Smuzhiyun #define SUNXI_SS_BOND_ID_A31S 5 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 214*4882a593Smuzhiyun void sunxi_board_init(void); 215*4882a593Smuzhiyun void sunxi_reset(void); 216*4882a593Smuzhiyun int sunxi_get_ss_bonding_id(void); 217*4882a593Smuzhiyun int sunxi_get_sid(unsigned int *sid); 218*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #endif /* _SUNXI_CPU_SUN4I_H */ 221