1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Chip specific defines for DA8XX/OMAP L1XX SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Mark A. Greer <mgreer@mvista.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under 7*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 8*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 9*4882a593Smuzhiyun * or implied. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_ARCH_DAVINCI_DA8XX_H 12*4882a593Smuzhiyun #define __ASM_ARCH_DAVINCI_DA8XX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <video/da8xx-fb.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/platform_device.h> 17*4882a593Smuzhiyun #include <linux/davinci_emac.h> 18*4882a593Smuzhiyun #include <linux/spi/spi.h> 19*4882a593Smuzhiyun #include <linux/platform_data/davinci_asp.h> 20*4882a593Smuzhiyun #include <linux/reboot.h> 21*4882a593Smuzhiyun #include <linux/regmap.h> 22*4882a593Smuzhiyun #include <linux/videodev2.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <mach/serial.h> 25*4882a593Smuzhiyun #include <mach/pm.h> 26*4882a593Smuzhiyun #include <linux/platform_data/edma.h> 27*4882a593Smuzhiyun #include <linux/platform_data/i2c-davinci.h> 28*4882a593Smuzhiyun #include <linux/platform_data/mmc-davinci.h> 29*4882a593Smuzhiyun #include <linux/platform_data/usb-davinci.h> 30*4882a593Smuzhiyun #include <linux/platform_data/spi-davinci.h> 31*4882a593Smuzhiyun #include <linux/platform_data/uio_pruss.h> 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #include <media/davinci/vpif_types.h> 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern void __iomem *da8xx_syscfg0_base; 36*4882a593Smuzhiyun extern void __iomem *da8xx_syscfg1_base; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade 40*4882a593Smuzhiyun * (than the regular 300MHz variant), the board code should set this up 41*4882a593Smuzhiyun * with the supported speed before calling da850_register_cpufreq(). 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun extern unsigned int da850_max_speed; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * The cp_intc interrupt controller for the da8xx isn't in the same 47*4882a593Smuzhiyun * chunk of physical memory space as the other registers (like it is 48*4882a593Smuzhiyun * on the davincis) so it needs to be mapped separately. It will be 49*4882a593Smuzhiyun * mapped early on when the I/O space is mapped and we'll put it just 50*4882a593Smuzhiyun * before the I/O space in the processor's virtual memory space. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define DA8XX_CP_INTC_BASE 0xfffee000 53*4882a593Smuzhiyun #define DA8XX_CP_INTC_SIZE SZ_8K 54*4882a593Smuzhiyun #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) 57*4882a593Smuzhiyun #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) 58*4882a593Smuzhiyun #define DA8XX_JTAG_ID_REG 0x18 59*4882a593Smuzhiyun #define DA8XX_HOST1CFG_REG 0x44 60*4882a593Smuzhiyun #define DA8XX_CHIPSIG_REG 0x174 61*4882a593Smuzhiyun #define DA8XX_CFGCHIP0_REG 0x17c 62*4882a593Smuzhiyun #define DA8XX_CFGCHIP1_REG 0x180 63*4882a593Smuzhiyun #define DA8XX_CFGCHIP2_REG 0x184 64*4882a593Smuzhiyun #define DA8XX_CFGCHIP3_REG 0x188 65*4882a593Smuzhiyun #define DA8XX_CFGCHIP4_REG 0x18c 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) 68*4882a593Smuzhiyun #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) 69*4882a593Smuzhiyun #define DA8XX_DEEPSLEEP_REG 0x8 70*4882a593Smuzhiyun #define DA8XX_PWRDN_REG 0x18 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define DA8XX_PSC0_BASE 0x01c10000 73*4882a593Smuzhiyun #define DA8XX_PLL0_BASE 0x01c11000 74*4882a593Smuzhiyun #define DA8XX_TIMER64P0_BASE 0x01c20000 75*4882a593Smuzhiyun #define DA8XX_TIMER64P1_BASE 0x01c21000 76*4882a593Smuzhiyun #define DA8XX_VPIF_BASE 0x01e17000 77*4882a593Smuzhiyun #define DA8XX_GPIO_BASE 0x01e26000 78*4882a593Smuzhiyun #define DA8XX_PSC1_BASE 0x01e27000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define DA8XX_DSP_L2_RAM_BASE 0x11800000 81*4882a593Smuzhiyun #define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) 82*4882a593Smuzhiyun #define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define DA8XX_AEMIF_CS2_BASE 0x60000000 85*4882a593Smuzhiyun #define DA8XX_AEMIF_CS3_BASE 0x62000000 86*4882a593Smuzhiyun #define DA8XX_AEMIF_CTL_BASE 0x68000000 87*4882a593Smuzhiyun #define DA8XX_SHARED_RAM_BASE 0x80000000 88*4882a593Smuzhiyun #define DA8XX_ARM_RAM_BASE 0xffff0000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun void da830_init(void); 91*4882a593Smuzhiyun void da830_init_irq(void); 92*4882a593Smuzhiyun void da830_init_time(void); 93*4882a593Smuzhiyun void da830_register_clocks(void); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun void da850_init(void); 96*4882a593Smuzhiyun void da850_init_irq(void); 97*4882a593Smuzhiyun void da850_init_time(void); 98*4882a593Smuzhiyun void da850_register_clocks(void); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun int da830_register_edma(struct edma_rsv_info *rsv); 101*4882a593Smuzhiyun int da850_register_edma(struct edma_rsv_info *rsv[2]); 102*4882a593Smuzhiyun int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 103*4882a593Smuzhiyun int da8xx_register_spi_bus(int instance, unsigned num_chipselect); 104*4882a593Smuzhiyun int da8xx_register_watchdog(void); 105*4882a593Smuzhiyun int da8xx_register_usb_phy(void); 106*4882a593Smuzhiyun int da8xx_register_usb20(unsigned mA, unsigned potpgt); 107*4882a593Smuzhiyun int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); 108*4882a593Smuzhiyun int da8xx_register_usb_phy_clocks(void); 109*4882a593Smuzhiyun int da850_register_sata_refclk(int rate); 110*4882a593Smuzhiyun int da8xx_register_emac(void); 111*4882a593Smuzhiyun int da8xx_register_uio_pruss(void); 112*4882a593Smuzhiyun int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); 113*4882a593Smuzhiyun int da8xx_register_mmcsd0(struct davinci_mmc_config *config); 114*4882a593Smuzhiyun int da850_register_mmcsd1(struct davinci_mmc_config *config); 115*4882a593Smuzhiyun void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); 116*4882a593Smuzhiyun int da8xx_register_rtc(void); 117*4882a593Smuzhiyun int da8xx_register_gpio(void *pdata); 118*4882a593Smuzhiyun int da850_register_cpufreq(char *async_clk); 119*4882a593Smuzhiyun int da8xx_register_cpuidle(void); 120*4882a593Smuzhiyun void __iomem *da8xx_get_mem_ctlr(void); 121*4882a593Smuzhiyun int da850_register_sata(unsigned long refclkpn); 122*4882a593Smuzhiyun int da850_register_vpif(void); 123*4882a593Smuzhiyun int da850_register_vpif_display 124*4882a593Smuzhiyun (struct vpif_display_config *display_config); 125*4882a593Smuzhiyun int da850_register_vpif_capture 126*4882a593Smuzhiyun (struct vpif_capture_config *capture_config); 127*4882a593Smuzhiyun void da8xx_rproc_reserve_cma(void); 128*4882a593Smuzhiyun int da8xx_register_rproc(void); 129*4882a593Smuzhiyun int da850_register_gpio(void); 130*4882a593Smuzhiyun int da830_register_gpio(void); 131*4882a593Smuzhiyun struct regmap *da8xx_get_cfgchip(void); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun extern struct platform_device da8xx_serial_device[]; 134*4882a593Smuzhiyun extern struct emac_platform_data da8xx_emac_pdata; 135*4882a593Smuzhiyun extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; 136*4882a593Smuzhiyun extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun extern const short da830_emif25_pins[]; 140*4882a593Smuzhiyun extern const short da830_spi0_pins[]; 141*4882a593Smuzhiyun extern const short da830_spi1_pins[]; 142*4882a593Smuzhiyun extern const short da830_mmc_sd_pins[]; 143*4882a593Smuzhiyun extern const short da830_uart0_pins[]; 144*4882a593Smuzhiyun extern const short da830_uart1_pins[]; 145*4882a593Smuzhiyun extern const short da830_uart2_pins[]; 146*4882a593Smuzhiyun extern const short da830_usb20_pins[]; 147*4882a593Smuzhiyun extern const short da830_usb11_pins[]; 148*4882a593Smuzhiyun extern const short da830_uhpi_pins[]; 149*4882a593Smuzhiyun extern const short da830_cpgmac_pins[]; 150*4882a593Smuzhiyun extern const short da830_emif3c_pins[]; 151*4882a593Smuzhiyun extern const short da830_mcasp0_pins[]; 152*4882a593Smuzhiyun extern const short da830_mcasp1_pins[]; 153*4882a593Smuzhiyun extern const short da830_mcasp2_pins[]; 154*4882a593Smuzhiyun extern const short da830_i2c0_pins[]; 155*4882a593Smuzhiyun extern const short da830_i2c1_pins[]; 156*4882a593Smuzhiyun extern const short da830_lcdcntl_pins[]; 157*4882a593Smuzhiyun extern const short da830_pwm_pins[]; 158*4882a593Smuzhiyun extern const short da830_ecap0_pins[]; 159*4882a593Smuzhiyun extern const short da830_ecap1_pins[]; 160*4882a593Smuzhiyun extern const short da830_ecap2_pins[]; 161*4882a593Smuzhiyun extern const short da830_eqep0_pins[]; 162*4882a593Smuzhiyun extern const short da830_eqep1_pins[]; 163*4882a593Smuzhiyun extern const short da850_vpif_capture_pins[]; 164*4882a593Smuzhiyun extern const short da850_vpif_display_pins[]; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun extern const short da850_i2c0_pins[]; 167*4882a593Smuzhiyun extern const short da850_i2c1_pins[]; 168*4882a593Smuzhiyun extern const short da850_lcdcntl_pins[]; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ 171