Home
last modified time | relevance | path

Searched defs:_shift (Results 76 – 100 of 135) sorted by relevance

123456

/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt6765-vcodec.c21 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2701-hif.c19 #define GATE_HIF(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2712-img.c21 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2701-eth.c19 #define GATE_ETH(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6765-img.c21 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6765-mm.c21 #define GATE_MM(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2712-bdp.c21 #define GATE_BDP(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2712-jpgdec.c21 #define GATE_JPGDEC(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2712-mfg.c21 #define GATE_MFG(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6797-img.c19 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2712-venc.c21 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6765-mipi0a.c21 #define GATE_MIPI0A(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6765-cam.c21 #define GATE_CAM(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2701-img.c21 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt6797-venc.c21 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
H A Dclk-mt2701-g3d.c19 #define GATE_G3D(_id, _name, _parent, _shift) { \ argument
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/st/
H A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_acl.c527 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
536 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
540 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
544 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
547 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap.h67 #define MUX(_id, _name, _parent_names, _reg, _shift, _width, _flags) \ argument
88 #define GATE(_id, _name, _parent_name, _reg, _shift, _flags) \ argument
108 #define DIV(_id, _name, _parent_name, _reg, _shift, _width, _flags) \ argument
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c19 #define _VOP_REG(off, _mask, _shift, _write_mask) \ argument
27 #define VOP_REG(off, _mask, _shift) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-kona.h299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Daxg-audio.c37 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ argument
53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument
133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument
319 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ argument
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument

123456