1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /************************************************************************
3*4882a593Smuzhiyun File : Clock H/w specific Information
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun Author: Pankaj Dev <pankaj.dev@st.com>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun Copyright (C) 2014 STMicroelectronics
8*4882a593Smuzhiyun ************************************************************************/
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __CLKGEN_INFO_H
11*4882a593Smuzhiyun #define __CLKGEN_INFO_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun extern spinlock_t clkgen_a9_lock;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct clkgen_field {
16*4882a593Smuzhiyun unsigned int offset;
17*4882a593Smuzhiyun unsigned int mask;
18*4882a593Smuzhiyun unsigned int shift;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
clkgen_read(void __iomem * base,struct clkgen_field * field)21*4882a593Smuzhiyun static inline unsigned long clkgen_read(void __iomem *base,
22*4882a593Smuzhiyun struct clkgen_field *field)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return (readl(base + field->offset) >> field->shift) & field->mask;
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun
clkgen_write(void __iomem * base,struct clkgen_field * field,unsigned long val)28*4882a593Smuzhiyun static inline void clkgen_write(void __iomem *base, struct clkgen_field *field,
29*4882a593Smuzhiyun unsigned long val)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun writel((readl(base + field->offset) &
32*4882a593Smuzhiyun ~(field->mask << field->shift)) | (val << field->shift),
33*4882a593Smuzhiyun base + field->offset);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define CLKGEN_FIELD(_offset, _mask, _shift) { \
39*4882a593Smuzhiyun .offset = _offset, \
40*4882a593Smuzhiyun .mask = _mask, \
41*4882a593Smuzhiyun .shift = _shift, \
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
45*4882a593Smuzhiyun &pll->data->field)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
48*4882a593Smuzhiyun &pll->data->field, val)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #endif /*__CLKGEN_INFO_H*/
51*4882a593Smuzhiyun
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