1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Owen Chen <owen.chen@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt6765-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs mm_cg_regs = {
16*4882a593Smuzhiyun .set_ofs = 0x104,
17*4882a593Smuzhiyun .clr_ofs = 0x108,
18*4882a593Smuzhiyun .sta_ofs = 0x100,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define GATE_MM(_id, _name, _parent, _shift) { \
22*4882a593Smuzhiyun .id = _id, \
23*4882a593Smuzhiyun .name = _name, \
24*4882a593Smuzhiyun .parent_name = _parent, \
25*4882a593Smuzhiyun .regs = &mm_cg_regs, \
26*4882a593Smuzhiyun .shift = _shift, \
27*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr, \
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct mtk_gate mm_clks[] = {
31*4882a593Smuzhiyun /* MM */
32*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
33*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),
34*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
35*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
36*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
37*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
38*4882a593Smuzhiyun GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
39*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
40*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
41*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),
42*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
43*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
44*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),
45*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),
46*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),
47*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),
48*4882a593Smuzhiyun GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),
49*4882a593Smuzhiyun GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),
50*4882a593Smuzhiyun GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),
51*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),
52*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
53*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),
54*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),
55*4882a593Smuzhiyun GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),
56*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),
57*4882a593Smuzhiyun GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),
58*4882a593Smuzhiyun GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),
59*4882a593Smuzhiyun GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),
60*4882a593Smuzhiyun GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),
61*4882a593Smuzhiyun GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
clk_mt6765_mm_probe(struct platform_device * pdev)64*4882a593Smuzhiyun static int clk_mt6765_mm_probe(struct platform_device *pdev)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
67*4882a593Smuzhiyun int r;
68*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (r)
77*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
78*4882a593Smuzhiyun __func__, r);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return r;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt6765_mm[] = {
84*4882a593Smuzhiyun { .compatible = "mediatek,mt6765-mmsys", },
85*4882a593Smuzhiyun {}
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static struct platform_driver clk_mt6765_mm_drv = {
89*4882a593Smuzhiyun .probe = clk_mt6765_mm_probe,
90*4882a593Smuzhiyun .driver = {
91*4882a593Smuzhiyun .name = "clk-mt6765-mm",
92*4882a593Smuzhiyun .of_match_table = of_match_clk_mt6765_mm,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun builtin_platform_driver(clk_mt6765_mm_drv);
97