1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_address.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "clk-mtk.h"
15*4882a593Smuzhiyun #include "clk-gate.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <dt-bindings/clock/mt2701-clk.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define GATE_G3D(_id, _name, _parent, _shift) { \
20*4882a593Smuzhiyun .id = _id, \
21*4882a593Smuzhiyun .name = _name, \
22*4882a593Smuzhiyun .parent_name = _parent, \
23*4882a593Smuzhiyun .regs = &g3d_cg_regs, \
24*4882a593Smuzhiyun .shift = _shift, \
25*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr, \
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct mtk_gate_regs g3d_cg_regs = {
29*4882a593Smuzhiyun .sta_ofs = 0x0,
30*4882a593Smuzhiyun .set_ofs = 0x4,
31*4882a593Smuzhiyun .clr_ofs = 0x8,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct mtk_gate g3d_clks[] = {
35*4882a593Smuzhiyun GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
clk_mt2701_g3dsys_init(struct platform_device * pdev)38*4882a593Smuzhiyun static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
41*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
42*4882a593Smuzhiyun int r;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
47*4882a593Smuzhiyun clk_data);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50*4882a593Smuzhiyun if (r)
51*4882a593Smuzhiyun dev_err(&pdev->dev,
52*4882a593Smuzhiyun "could not register clock provider: %s: %d\n",
53*4882a593Smuzhiyun pdev->name, r);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun mtk_register_reset_controller(node, 1, 0xc);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return r;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt2701_g3d[] = {
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .compatible = "mediatek,mt2701-g3dsys",
63*4882a593Smuzhiyun .data = clk_mt2701_g3dsys_init,
64*4882a593Smuzhiyun }, {
65*4882a593Smuzhiyun /* sentinel */
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
clk_mt2701_g3d_probe(struct platform_device * pdev)69*4882a593Smuzhiyun static int clk_mt2701_g3d_probe(struct platform_device *pdev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int (*clk_init)(struct platform_device *);
72*4882a593Smuzhiyun int r;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun clk_init = of_device_get_match_data(&pdev->dev);
75*4882a593Smuzhiyun if (!clk_init)
76*4882a593Smuzhiyun return -EINVAL;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun r = clk_init(pdev);
79*4882a593Smuzhiyun if (r)
80*4882a593Smuzhiyun dev_err(&pdev->dev,
81*4882a593Smuzhiyun "could not register clock provider: %s: %d\n",
82*4882a593Smuzhiyun pdev->name, r);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return r;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct platform_driver clk_mt2701_g3d_drv = {
88*4882a593Smuzhiyun .probe = clk_mt2701_g3d_probe,
89*4882a593Smuzhiyun .driver = {
90*4882a593Smuzhiyun .name = "clk-mt2701-g3d",
91*4882a593Smuzhiyun .of_match_table = of_match_clk_mt2701_g3d,
92*4882a593Smuzhiyun },
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun builtin_platform_driver(clk_mt2701_g3d_drv);
96