1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _CCU_PHASE_H_
7*4882a593Smuzhiyun #define _CCU_PHASE_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_common.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct ccu_phase {
14*4882a593Smuzhiyun u8 shift;
15*4882a593Smuzhiyun u8 width;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct ccu_common common;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \
21*4882a593Smuzhiyun struct ccu_phase _struct = { \
22*4882a593Smuzhiyun .shift = _shift, \
23*4882a593Smuzhiyun .width = _width, \
24*4882a593Smuzhiyun .common = { \
25*4882a593Smuzhiyun .reg = _reg, \
26*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
27*4882a593Smuzhiyun _parent, \
28*4882a593Smuzhiyun &ccu_phase_ops, \
29*4882a593Smuzhiyun _flags), \
30*4882a593Smuzhiyun } \
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
hw_to_ccu_phase(struct clk_hw * hw)33*4882a593Smuzhiyun static inline struct ccu_phase *hw_to_ccu_phase(struct clk_hw *hw)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct ccu_common *common = hw_to_ccu_common(hw);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return container_of(common, struct ccu_phase, common);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun extern const struct clk_ops ccu_phase_ops;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #endif /* _CCU_PHASE_H_ */
43