1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Copyright (c) 2017 MediaTek Inc.
3*4882a593Smuzhiyun * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun #include <dt-bindings/clock/mt6797-clk.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static const struct mtk_gate_regs img_cg_regs = {
14*4882a593Smuzhiyun .set_ofs = 0x0004,
15*4882a593Smuzhiyun .clr_ofs = 0x0008,
16*4882a593Smuzhiyun .sta_ofs = 0x0000,
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define GATE_IMG(_id, _name, _parent, _shift) { \
20*4882a593Smuzhiyun .id = _id, \
21*4882a593Smuzhiyun .name = _name, \
22*4882a593Smuzhiyun .parent_name = _parent, \
23*4882a593Smuzhiyun .regs = &img_cg_regs, \
24*4882a593Smuzhiyun .shift = _shift, \
25*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr, \
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct mtk_gate img_clks[] = {
29*4882a593Smuzhiyun GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
30*4882a593Smuzhiyun GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
31*4882a593Smuzhiyun GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
32*4882a593Smuzhiyun GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt6797_img[] = {
36*4882a593Smuzhiyun { .compatible = "mediatek,mt6797-imgsys", },
37*4882a593Smuzhiyun {}
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
clk_mt6797_img_probe(struct platform_device * pdev)40*4882a593Smuzhiyun static int clk_mt6797_img_probe(struct platform_device *pdev)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
43*4882a593Smuzhiyun int r;
44*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
49*4882a593Smuzhiyun clk_data);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
52*4882a593Smuzhiyun if (r)
53*4882a593Smuzhiyun dev_err(&pdev->dev,
54*4882a593Smuzhiyun "could not register clock provider: %s: %d\n",
55*4882a593Smuzhiyun pdev->name, r);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return r;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct platform_driver clk_mt6797_img_drv = {
61*4882a593Smuzhiyun .probe = clk_mt6797_img_probe,
62*4882a593Smuzhiyun .driver = {
63*4882a593Smuzhiyun .name = "clk-mt6797-img",
64*4882a593Smuzhiyun .of_match_table = of_match_clk_mt6797_img,
65*4882a593Smuzhiyun },
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun builtin_platform_driver(clk_mt6797_img_drv);
69