1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt2712-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs bdp_cg_regs = {
16*4882a593Smuzhiyun .set_ofs = 0x100,
17*4882a593Smuzhiyun .clr_ofs = 0x100,
18*4882a593Smuzhiyun .sta_ofs = 0x100,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define GATE_BDP(_id, _name, _parent, _shift) { \
22*4882a593Smuzhiyun .id = _id, \
23*4882a593Smuzhiyun .name = _name, \
24*4882a593Smuzhiyun .parent_name = _parent, \
25*4882a593Smuzhiyun .regs = &bdp_cg_regs, \
26*4882a593Smuzhiyun .shift = _shift, \
27*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_no_setclr, \
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct mtk_gate bdp_clks[] = {
31*4882a593Smuzhiyun GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
32*4882a593Smuzhiyun GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
33*4882a593Smuzhiyun GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
34*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
35*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
36*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
37*4882a593Smuzhiyun GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
38*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
39*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
40*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
41*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
42*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
43*4882a593Smuzhiyun GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
44*4882a593Smuzhiyun GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
45*4882a593Smuzhiyun GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
46*4882a593Smuzhiyun GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
47*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
48*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
49*4882a593Smuzhiyun GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
50*4882a593Smuzhiyun GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
51*4882a593Smuzhiyun GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
52*4882a593Smuzhiyun GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
53*4882a593Smuzhiyun GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
54*4882a593Smuzhiyun GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
55*4882a593Smuzhiyun GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
56*4882a593Smuzhiyun GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
57*4882a593Smuzhiyun GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
58*4882a593Smuzhiyun GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
clk_mt2712_bdp_probe(struct platform_device * pdev)61*4882a593Smuzhiyun static int clk_mt2712_bdp_probe(struct platform_device *pdev)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
64*4882a593Smuzhiyun int r;
65*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
70*4882a593Smuzhiyun clk_data);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (r != 0)
75*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
76*4882a593Smuzhiyun __func__, r);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return r;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt2712_bdp[] = {
82*4882a593Smuzhiyun { .compatible = "mediatek,mt2712-bdpsys", },
83*4882a593Smuzhiyun {}
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static struct platform_driver clk_mt2712_bdp_drv = {
87*4882a593Smuzhiyun .probe = clk_mt2712_bdp_probe,
88*4882a593Smuzhiyun .driver = {
89*4882a593Smuzhiyun .name = "clk-mt2712-bdp",
90*4882a593Smuzhiyun .of_match_table = of_match_clk_mt2712_bdp,
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun builtin_platform_driver(clk_mt2712_bdp_drv);
95