1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Shunli Wang <shunli.wang@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt2701-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs eth_cg_regs = {
16*4882a593Smuzhiyun .sta_ofs = 0x0030,
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define GATE_ETH(_id, _name, _parent, _shift) { \
20*4882a593Smuzhiyun .id = _id, \
21*4882a593Smuzhiyun .name = _name, \
22*4882a593Smuzhiyun .parent_name = _parent, \
23*4882a593Smuzhiyun .regs = ð_cg_regs, \
24*4882a593Smuzhiyun .shift = _shift, \
25*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_no_setclr_inv, \
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct mtk_gate eth_clks[] = {
29*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
30*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
31*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
32*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
33*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
34*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
35*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
36*4882a593Smuzhiyun GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt2701_eth[] = {
40*4882a593Smuzhiyun { .compatible = "mediatek,mt2701-ethsys", },
41*4882a593Smuzhiyun {}
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
clk_mt2701_eth_probe(struct platform_device * pdev)44*4882a593Smuzhiyun static int clk_mt2701_eth_probe(struct platform_device *pdev)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
47*4882a593Smuzhiyun int r;
48*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
53*4882a593Smuzhiyun clk_data);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56*4882a593Smuzhiyun if (r)
57*4882a593Smuzhiyun dev_err(&pdev->dev,
58*4882a593Smuzhiyun "could not register clock provider: %s: %d\n",
59*4882a593Smuzhiyun pdev->name, r);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun mtk_register_reset_controller(node, 1, 0x34);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return r;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct platform_driver clk_mt2701_eth_drv = {
67*4882a593Smuzhiyun .probe = clk_mt2701_eth_probe,
68*4882a593Smuzhiyun .driver = {
69*4882a593Smuzhiyun .name = "clk-mt2701-eth",
70*4882a593Smuzhiyun .of_match_table = of_match_clk_mt2701_eth,
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun builtin_platform_driver(clk_mt2701_eth_drv);
75