1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt2712-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs venc_cg_regs = {
16*4882a593Smuzhiyun .set_ofs = 0x4,
17*4882a593Smuzhiyun .clr_ofs = 0x8,
18*4882a593Smuzhiyun .sta_ofs = 0x0,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define GATE_VENC(_id, _name, _parent, _shift) { \
22*4882a593Smuzhiyun .id = _id, \
23*4882a593Smuzhiyun .name = _name, \
24*4882a593Smuzhiyun .parent_name = _parent, \
25*4882a593Smuzhiyun .regs = &venc_cg_regs, \
26*4882a593Smuzhiyun .shift = _shift, \
27*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr_inv, \
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct mtk_gate venc_clks[] = {
31*4882a593Smuzhiyun GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
32*4882a593Smuzhiyun GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
33*4882a593Smuzhiyun GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
clk_mt2712_venc_probe(struct platform_device * pdev)36*4882a593Smuzhiyun static int clk_mt2712_venc_probe(struct platform_device *pdev)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
39*4882a593Smuzhiyun int r;
40*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
45*4882a593Smuzhiyun clk_data);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (r != 0)
50*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
51*4882a593Smuzhiyun __func__, r);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return r;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt2712_venc[] = {
57*4882a593Smuzhiyun { .compatible = "mediatek,mt2712-vencsys", },
58*4882a593Smuzhiyun {}
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static struct platform_driver clk_mt2712_venc_drv = {
62*4882a593Smuzhiyun .probe = clk_mt2712_venc_probe,
63*4882a593Smuzhiyun .driver = {
64*4882a593Smuzhiyun .name = "clk-mt2712-venc",
65*4882a593Smuzhiyun .of_match_table = of_match_clk_mt2712_venc,
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun builtin_platform_driver(clk_mt2712_venc_drv);
70