1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Owen Chen <owen.chen@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "clk-mtk.h"
11*4882a593Smuzhiyun #include "clk-gate.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <dt-bindings/clock/mt6765-clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const struct mtk_gate_regs cam_cg_regs = {
16*4882a593Smuzhiyun .set_ofs = 0x4,
17*4882a593Smuzhiyun .clr_ofs = 0x8,
18*4882a593Smuzhiyun .sta_ofs = 0x0,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define GATE_CAM(_id, _name, _parent, _shift) { \
22*4882a593Smuzhiyun .id = _id, \
23*4882a593Smuzhiyun .name = _name, \
24*4882a593Smuzhiyun .parent_name = _parent, \
25*4882a593Smuzhiyun .regs = &cam_cg_regs, \
26*4882a593Smuzhiyun .shift = _shift, \
27*4882a593Smuzhiyun .ops = &mtk_clk_gate_ops_setclr, \
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct mtk_gate cam_clks[] = {
31*4882a593Smuzhiyun GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0),
32*4882a593Smuzhiyun GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1),
33*4882a593Smuzhiyun GATE_CAM(CLK_CAM, "cam", "mm_ck", 6),
34*4882a593Smuzhiyun GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7),
35*4882a593Smuzhiyun GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8),
36*4882a593Smuzhiyun GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9),
37*4882a593Smuzhiyun GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10),
38*4882a593Smuzhiyun GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11),
39*4882a593Smuzhiyun GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12),
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
clk_mt6765_cam_probe(struct platform_device * pdev)42*4882a593Smuzhiyun static int clk_mt6765_cam_probe(struct platform_device *pdev)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct clk_onecell_data *clk_data;
45*4882a593Smuzhiyun int r;
46*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (r)
55*4882a593Smuzhiyun pr_err("%s(): could not register clock provider: %d\n",
56*4882a593Smuzhiyun __func__, r);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return r;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt6765_cam[] = {
62*4882a593Smuzhiyun { .compatible = "mediatek,mt6765-camsys", },
63*4882a593Smuzhiyun {}
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct platform_driver clk_mt6765_cam_drv = {
67*4882a593Smuzhiyun .probe = clk_mt6765_cam_probe,
68*4882a593Smuzhiyun .driver = {
69*4882a593Smuzhiyun .name = "clk-mt6765-cam",
70*4882a593Smuzhiyun .of_match_table = of_match_clk_mt6765_cam,
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun builtin_platform_driver(clk_mt6765_cam_drv);
75