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Searched refs:_TSOCtrl (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c45 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
246 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
270 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
271 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c45 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
246 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
270 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
271 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c45 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
243 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
270 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
271 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c44 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
244 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
250 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
251 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
254 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
268 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
269 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
274 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c44 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
227 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
247 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
253 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
254 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
256 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
257 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
271 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
272 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
277 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DhalTSO.c121 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
351 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
362 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
363 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
365 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
377 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
378 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
379 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
405 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
406 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tso/
H A DhalTSO.c121 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
295 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
306 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
307 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
309 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
321 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
322 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
323 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
349 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
350 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tso/
H A DhalTSO.c126 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
311 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
323 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
324 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
326 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
338 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
339 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
340 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
366 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
367 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DhalTSO.c121 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
359 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
370 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
371 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
373 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
385 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
386 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
387 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
413 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
414 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DhalTSO.c126 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
358 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
371 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
372 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
374 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
386 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
387 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
388 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
414 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
415 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DhalTSO.c126 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
367 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
380 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
381 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
383 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
395 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
396 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
397 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
423 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
424 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DhalTSO.c126 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
367 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
380 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
381 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
383 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
395 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
396 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
397 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
423 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
424 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DhalTSO.c126 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
358 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO); in HAL_TSO_SetBank()
371 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndR()
372 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndR()
374 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value in HAL_TSO_REG32_IndR()
386 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address in HAL_TSO_REG32_IndW()
387 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value in HAL_TSO_REG32_IndW()
388 …_HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_… in HAL_TSO_REG32_IndW()
414 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL); in HAL_TSO_Init()
415 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL); in HAL_TSO_Init()
[all …]