Lines Matching refs:_TSOCtrl
45 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
243 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
270 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
271 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
291 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Clear()
298 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Status()
425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
429 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
884 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
887 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
890 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
911 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
945 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW_withSid()
946 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW_withSid()
949 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW_withSid()
950 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F)); in _HAL_TSO_PageTableIndW_withSid()
953 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW_withSid()
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW()
960 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW()
963 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW()
964 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000); in _HAL_TSO_PageTableIndW()
967 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW()
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndR()
974 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndR()
977 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN); in _HAL_TSO_PageTableIndR()
980 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA)); in _HAL_TSO_PageTableIndR()
1002 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]); in HAL_TSO_Set_Filein_ReadAddr()
1007 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]); in HAL_TSO_Set_Filein_ReadAddr()
1016 …REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_6… in HAL_TSO_Set_Filein_ReadLen()
1024 …REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1); in HAL_TSO_Get_Filein_ReadAddr()
1025 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Get_Filein_ReadAddr()
1037 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Set_Filein_Ctrl()
1044 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Get_Filein_Ctrl()
1061 … REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_FileinTimer_Enable()
1075 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer); in HAL_TSO_Filein_Rate()
1080 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192Mode_Enable()
1094 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192BlockMode_Enable()
1111 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRCnt()
1133 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRLevel()
1140 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1141 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1167 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)); in HAL_TSO_Cfg1_Enable()
1178 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1179 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1187 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1188 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1191 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1192 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1195 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1196 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1199 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1200 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1203 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1204 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1207 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1208 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1254 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1257 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_ChIf_Cfg()
1260 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1263 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1266 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1269 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1301 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1304 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1307 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1310 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1313 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1348 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data); in HAL_TSO_Get_ChIf_Cfg()
1355 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_File_Cfg1_Enable()
1393 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_ValidBlock_Count()
1399 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_ValidBlock_Count()
1401 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1402 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1412 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_InvalidBlock_Count()
1418 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_InvalidBlock_Count()
1420 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1421 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1493 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Set()
1494 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Set()
1505 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Get()
1506 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Get()
1518 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1); in HAL_TSO_TimeStamp_Get()
1528 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_PktChkSize_Set()
1529 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1533 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_PktChkSize_Set()
1534 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1538 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_PktChkSize_Set()
1539 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1543 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_PktChkSize_Set()
1544 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1548 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_PktChkSize_Set()
1549 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1553 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_PktChkSize_Set()
1554 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1567 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize); in HAL_TSO_RW_OutputPktSize()
1571 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3)); in HAL_TSO_RW_OutputPktSize()
1574 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PK… in HAL_TSO_RW_OutputPktSize()
1575 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_… in HAL_TSO_RW_OutputPktSize()
1583 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1584 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1588 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1589 … (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1603 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1604 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1608 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1609 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1613 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1614 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1618 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1619 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1623 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1624 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1628 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1629 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1644 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1645 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1648 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1649 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1652 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1653 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1657 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1658 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1661 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1662 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1665 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1666 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1670 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1671 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1674 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1675 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1678 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1679 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1683 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1684 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1687 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1688 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1691 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1692 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1696 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1697 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1700 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1701 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1704 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1705 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1709 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1710 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1713 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1714 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1717 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1718 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1735 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1738 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1741 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1762 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1765 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1768 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1791 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO_MODE); in HAL_TSO_TsioMode_En()
1795 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO_MODE); in HAL_TSO_TsioMode_En()
1803 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1807 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1815 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
1819 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
2113 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2118 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2163 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2168 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()