1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halTSO.c
20 // @brief TS I/O HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "regTSO.h"
25 #include "halTSO.h"
26 #include "drvSYS.h"
27 #include "halCHIP.h"
28
29 #ifdef CONFIG_MSTAR_CLKM
30 #include "drvCLKM.h"
31 #endif
32
33 //--------------------------------------------------------------------------------------------------
34 // Driver Compiler Option
35 //--------------------------------------------------------------------------------------------------
36 #define TSP_HAL_REG_SAFE_MODE 1 // Register protection access between 1 task and 1+ ISR
37
38 #define MIU_BUS 4
39 #define K6U02 (MDrv_SYS_GetChipRev() >= 0x1) // This feature/behavior is supported after K6 U02
40
41
42 //--------------------------------------------------------------------------------------------------
43 // TSP Hardware Abstraction Layer
44 //--------------------------------------------------------------------------------------------------
45 static REG_Ctrl_TSO* _TSOCtrl = NULL;
46 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
47
48 static MS_VIRT _u32TSORegBase = 0;
49
50 //-------------------------------------------------------------------------------------------------
51 // Debug Message
52 //-------------------------------------------------------------------------------------------------
53 typedef enum
54 {
55 E_HAL_TSO_DBG_LEVEL_NONE, // no debug message shown
56 E_HAL_TSO_DBG_LEVEL_ERR, // only shows error message that can't be recover
57 E_HAL_TSO_DBG_LEVEL_WARN, // error case can be recover, like retry
58 E_HAL_TSO_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
59 E_HAL_TSO_DBG_LEVEL_INFO, // information for internal parameter
60 E_HAL_TSO_DBG_LEVEL_FUNC, // Function trace and input parameter trace
61 E_HAL_TSO_DBG_LEVEL_TRACE, // debug trace
62 } EN_HAL_TSO_DBGMSG_LEVEL;
63
64 typedef enum
65 {
66 E_HAL_TSO_DBG_MODEL_NONE, // @temporarily , need to refine
67 E_HAL_TSO_DBG_MODEL_ALL,
68 } EN_HAL_TSO_DBGMSG_MODEL;
69
70 #define HAL_TSO_DBGMSG(_level,_model,_f) do {if(_u32TSODbgLevel >= (_level)&&((_u32TSODbgModel&_model)!=0)) (_f);} while(0)
71 static MS_U32 _u32TSODbgLevel = E_HAL_TSO_DBG_LEVEL_ERR;
72 static MS_U32 _u32TSODbgModel = E_HAL_TSO_DBG_MODEL_ALL;
73
74
75 //[NOTE] Jerry
76 // Some register has write order, for example, writing PCR_L will disable PCR counter
77 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
78 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
79 (reg)->H = ((value) >> 16); } while(0)
80
81 #define _HAL_REG16_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
82
83 //--------------------------------------------------------------------------------------------------
84 // Macro of bit operations
85 //--------------------------------------------------------------------------------------------------
86 #define HAS_FLAG(flag, bit) ((flag) & (bit))
87 #define SET_FLAG(flag, bit) ((flag)|= (bit))
88 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
89 #define SET_FLAG1(flag, bit) ((flag)| (bit))
90 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
91
92
93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));
94 #define _REG32_SET(reg, value); _HAL_REG32_W(reg, SET_FLAG1(_HAL_REG32_R(reg), value));
95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
96 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
97
98
99
100
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
102 #define REG_CLKGEN0_TSO_IN 0x27
103 #define REG_CLKGEN0_TSO_IN_MASK 0x001F
104 #define REG_CLKGEN0_TSO_IN_SHIFT 2
105 #define REG_CLKGEN0_TSO_IN_DISABLE 0x0001
106 #define REG_CLKGEN0_TSO_IN_INVERT 0x0002
107 // bit[4:0] -> 0: disable clock
108 // 1: invert clock
109 // bit [3:2] -> 000: select TS0_CLK
110 // 001: select TS1_CLK
111 // 010: from demod 0
112 #define REG_CLKGEN0_TSO_TRACE_MASK 0x0F00
113 #define REG_CLKGEN0_TSO_TRACE_DISABLE 0x0100
114 #define REG_CLKGEN0_TSO_TRACE_INVERT 0x0200
115 #define REG_CLKGEN0_TSO_TRACE_216M 0x0000
116
117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D
118 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK 0x001F
119 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT 0
120 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_EN_MASK 0x0020
121 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE 0x0020
122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040
123 #define HAL_TSO_OUT_DIV_SEL_172M_2N 0x0000
124 #define HAL_TSO_OUT_DIV_SEL_288M_2N 0x0040
125
126 #define REG_CLKGEN0_TSO_OUT_DIVNUM 0x2E
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0
128 #define REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT 6
129 #define REG_CLKGEN_TSO_P_TSO_OUT_MASK 0xF800
130 #define REG_CLKGEN_TSO_P_TSO_OUT_SHIFT 13
131
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F
133 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x001F
134 #define REG_CLKGEN0_TSO_OUT_CLK_DISABLE 0x0001
135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002
136 #define REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT 2
137 // bit[4:0] -> 0: disable clock
138 // 1: invert clock
139 // bit [4:2] -> 000: from demod 0, clk_dvbtc_ts_p
140 // 001: 62MHz
141 // 010: 54MHz
142 // 011: clk_p_tso_out (live in)
143 // 100: clk_p_tso_out_div8 (live in)
144 // 101: tso_out_div (clock/(N+1))
145 // 110: 86MHz
146
147 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))))
148 #define REG_CLKGEN1_DEMOD0_OUT_CLK 0x00
149 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_MASK 0x001F //demod0 div num of output clk
150 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_SHIFT 0
151 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_MASK 0x0100 //demod0 div src of output clk
152 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_SHIFT 8
153 // bit[8] -> 0: CLK_DMPLLDIV2
154 // 1: CLK_DMPLLDIV3
155
156 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
157 #define REG_CLKGEN2_TSO1_IN 0x06
158 #define REG_CLKGEN2_TSO2_IN 0x07
159 #define REG_CLKGEN2_TSO3_IN 0x08
160 #define REG_CLKGEN2_TSO4_IN 0x09
161 #define REG_CLKGEN2_TSO5_IN 0x0a
162
163 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
164 #define REG_TOP_TSO_MUX 0x3A
165 #define REG_TOP_TSO_MUX_MASK 0x0007
166 #define REG_TOP_TSO1_MUX_SHIFT 0
167 #define REG_TOP_TSO2_MUX_SHIFT 4
168 #define REG_TOP_TSO3_MUX_SHIFT 8
169 #define REG_TOP_TSO4_MUX_SHIFT 12
170
171 #define REG_TOP_TSO1_MUX 0x3B
172 #define REG_TOP_TSO5_MUX_SHIFT 0
173 #define REG_TOP_TSO6_MUX_SHIFT 4
174 // bit[2:0] -> 000: PAD_TS0
175 // 001: PAD_TS1
176 // 0111: DEMOD
177
178 #if 0 // Not used
179 #define REG_TOP_MIU_GP1_i64 0x21
180 #define REG_TOP_MIU_GP1_i64_TSO_MASK 0x0080
181 #define REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT 0x0000
182 #define REG_TOP_MIU_GP1_i64_TSO_64BIT_CLIENT 0x0080
183 #define REG_TOP_TS_CONFIG 0x57
184 #define REG_TOP_TS0_CONFIG_MASK 0x0700
185 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0100
186 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0200
187 #define REG_TOP_TS1_CONFIG_MASK 0x3800
188 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800
189 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000
190 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800
191 #define REG_TOP_TS2_CONFIG_MASK 0x4000
192 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x4000
193 #define REG_TOP_TSCB_CONFIG_MASK 0x8000
194 #define REG_TOP_TSCB_CONFIG_SERIAL_IN 0x8000
195 #define REG_TOP_TS_OUT_MODE 0x6E
196 #define REG_TOP_TS_OUT_MODE_MASK 0x0300
197 #define REG_TOP_TS_OUT_MODE_TSO 0x0200
198 #endif
199
200 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
201 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
202 #define REG_MIUDIG_MIU_SEL1 0x79
203 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080
204
205 //--------------------------------------------------------------------------------------------------
206 // Implementation
207 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_TSO * reg)208 static MS_U32 _HAL_REG32_R(REG32_TSO *reg)
209 {
210 MS_U32 value = 0;
211 value = (reg)->H << 16;
212 value |= (reg)->L;
213 return value;
214 }
215
_HAL_REG16_R(REG16_TSO * reg)216 static MS_U16 _HAL_REG16_R(REG16_TSO *reg)
217 {
218 MS_U16 value = 0;
219 value = (reg)->data;
220 return value;
221 }
222
HAL_TSO_SetBank(MS_VIRT u32BankAddr)223 void HAL_TSO_SetBank(MS_VIRT u32BankAddr)
224 {
225 _u32TSORegBase = u32BankAddr;
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706
227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612
228 }
229
230 //
231 // General API
232 //
HAL_TSO_Init(void)233 void HAL_TSO_Init(void)
234 {
235 //select MIU0, and 128bit MIU bus
236 /*
237 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
238 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
239 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
240 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
241 */
242
243 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);
244 if(K6U02)
245 {
246 _REG16_SET(&(_TSOCtrl1->REG_TSO_MIU_ABT_CONFIG_1), REG_MIU_ABT_CONFIG_1_CHECK2MI_RDY | REG_MIU_ABT_CONFIG_1_MIU_FIXED_LAST_WD_EN_DONE_Z);
247 }
248 }
249
HAL_TSO_Reset_All(MS_U8 u8Eng)250 void HAL_TSO_Reset_All(MS_U8 u8Eng)
251 {
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);
254
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
257 }
258
HAL_TSO_Reset(MS_U8 u8Eng)259 void HAL_TSO_Reset(MS_U8 u8Eng)
260 {
261 //@TODO not find in register table
262 /*
263 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
264 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
265 */
266 }
267
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)268 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
269 {
270 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem));
271 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem));
272 }
273
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL benable,MS_U16 u16init)274 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL benable, MS_U16 u16init)
275 {
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
277 MS_U16 u16data = _HAL_REG16_R(reg);
278
279 if(benable)
280 {
281 _HAL_REG16_W(reg, (u16data | u16init));
282 }
283 else
284 {
285 _HAL_REG16_W(reg, (u16data & ~u16init));
286 }
287 }
288
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)289 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
290 {
291 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
292
293 _HAL_REG16_W(reg, (_HAL_REG16_R(reg) & ~u16Int));
294 }
295
HAL_TSO_HWInt_Status(MS_U8 u8Eng)296 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
297 {
298 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
299
300 return (_HAL_REG16_R(reg) & TSO_INT_STS_MASK);
301 }
302
HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId,MS_U16 * u16Pad,MS_U16 * u16Clk)303 MS_BOOL HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId, MS_U16 *u16Pad, MS_U16 *u16Clk)
304 {
305 switch(u8Pad3WireId)
306 {
307 case 3:
308 *u16Pad = HAL_TSOIN_MUX_TS3;
309 *u16Clk = TSO_CLKIN_TS3;
310 break;
311 case 4:
312 *u16Pad = HAL_TSOIN_MUX_TS4;
313 *u16Clk = TSO_CLKIN_TS4;
314 break;
315 case 5:
316 *u16Pad = HAL_TSOIN_MUX_TS5;
317 *u16Clk = TSO_CLKIN_TS5;
318 break;
319 case 6:
320 *u16Pad = HAL_TSOIN_MUX_TS6;
321 *u16Clk = TSO_CLKIN_TS6;
322 break;
323 default:
324 printf("[%s][%d]: Not support !!\n", __FUNCTION__, __LINE__);
325 return FALSE;
326 }
327
328 return TRUE;
329 }
330
331
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)332 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
333 {
334 MS_U16 u16Reg, u16RegShift;
335
336 switch(u8TsIf)
337 {
338 case HAL_TSO_TSIF_LIVE1:
339 u16Reg = REG_TOP_TSO_MUX;
340 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
341 break;
342 case HAL_TSO_TSIF_LIVE2:
343 u16Reg = REG_TOP_TSO_MUX;
344 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
345 break;
346 case HAL_TSO_TSIF_LIVE3:
347 u16Reg = REG_TOP_TSO_MUX;
348 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
349 break;
350 case HAL_TSO_TSIF_LIVE4:
351 u16Reg = REG_TOP_TSO_MUX;
352 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
353 break;
354 case HAL_TSO_TSIF_LIVE5:
355 u16Reg = REG_TOP_TSO1_MUX;
356 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
357 break;
358 case HAL_TSO_TSIF_LIVE6:
359 u16Reg = REG_TOP_TSO1_MUX;
360 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
361 break;
362 default:
363 printf("Not support !!\n");
364 return FALSE;
365 }
366
367 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~(REG_TOP_TSO_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
368
369 //@NOTE: no need to change input pad mode dynamically (Mboot handle it...)
370
371 return TRUE;
372 }
373
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)374 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
375 {
376 //@TODO not implement
377 return TRUE;
378 }
379
380
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)381 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
382 {
383 MS_U16 u16Reg, u16RegShift;
384 MS_U16 u16data = 0;
385 REG16_TSO* reg16 = 0;
386
387 // Set pad mux
388 switch(u8TsIf)
389 {
390 case HAL_TSO_TSIF_LIVE1:
391 u16Reg = REG_TOP_TSO_MUX;
392 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
393 break;
394 case HAL_TSO_TSIF_LIVE2:
395 u16Reg = REG_TOP_TSO_MUX;
396 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
397 break;
398 case HAL_TSO_TSIF_LIVE3:
399 u16Reg = REG_TOP_TSO_MUX;
400 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
401 break;
402 case HAL_TSO_TSIF_LIVE4:
403 u16Reg = REG_TOP_TSO_MUX;
404 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
405 break;
406 case HAL_TSO_TSIF_LIVE5:
407 u16Reg = REG_TOP_TSO1_MUX;
408 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
409 break;
410 case HAL_TSO_TSIF_LIVE6:
411 u16Reg = REG_TOP_TSO1_MUX;
412 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
413 break;
414 default:
415 printf("Not support !!\n");
416 return FALSE;
417 }
418
419 *pu16Pad = (TSP_TOP_REG(u16Reg) >> u16RegShift) & REG_TOP_TSO_MUX_MASK;
420
421 switch(u8TsIf)
422 {
423 case HAL_TSO_TSIF_LIVE1:
424 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK;
425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
426 break;
427 case HAL_TSO_TSIF_LIVE2:
428 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;
429 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
430 break;
431 case HAL_TSO_TSIF_LIVE3:
432 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;
433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
434 break;
435 case HAL_TSO_TSIF_LIVE4:
436 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;
437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
438 break;
439 case HAL_TSO_TSIF_LIVE5:
440 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;
441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
442 break;
443 case HAL_TSO_TSIF_LIVE6:
444 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;
445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
446 break;
447 default:
448 printf("Not support !!\n");
449 return FALSE;
450 }
451
452 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
453 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
454 *pbClkInvert = ((u16data & REG_CLKGEN0_TSO_IN_INVERT) == REG_CLKGEN0_TSO_IN_INVERT);
455
456 return TRUE;
457 }
458
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)459 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
460 {
461 MS_BOOL isCLKGEN0 = FALSE;
462 MS_U16 u16Reg;
463 MS_U16 u16value = 0;
464
465 switch(u8TsIf)
466 {
467 case HAL_TSO_TSIF_LIVE1:
468 isCLKGEN0 = TRUE;
469 u16Reg = REG_CLKGEN0_TSO_IN;
470 break;
471 case HAL_TSO_TSIF_LIVE2:
472 u16Reg = REG_CLKGEN2_TSO1_IN;
473 break;
474 case HAL_TSO_TSIF_LIVE3:
475 u16Reg = REG_CLKGEN2_TSO2_IN;
476 break;
477 case HAL_TSO_TSIF_LIVE4:
478 u16Reg = REG_CLKGEN2_TSO3_IN;
479 break;
480 case HAL_TSO_TSIF_LIVE5:
481 u16Reg = REG_CLKGEN2_TSO4_IN;
482 break;
483 case HAL_TSO_TSIF_LIVE6:
484 u16Reg = REG_CLKGEN2_TSO5_IN;
485 break;
486 default:
487 printf("Not support !!\n");
488 return FALSE;
489 }
490
491 if(u16ClkSel == 0xFFFF)
492 {
493 return FALSE;
494 }
495
496 if(isCLKGEN0)
497 {
498 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
499 }
500 else
501 {
502 u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
503 }
504
505 if(!bEnable)
506 {
507 u16value |= REG_CLKGEN0_TSO_IN_DISABLE;
508 }
509 else
510 {
511 #ifndef CONFIG_MSTAR_CLKM
512 u16value |= (u16ClkSel << REG_CLKGEN0_TSO_IN_SHIFT);
513 #endif
514
515 if(bClkInvert)
516 {
517 u16value |= REG_CLKGEN0_TSO_IN_INVERT;
518 }
519 }
520
521 if(isCLKGEN0)
522 {
523 TSO_CLKGEN0_REG(u16Reg) = u16value;
524 }
525 else
526 {
527 TSO_CLKGEN2_REG(u16Reg) = u16value;
528 }
529
530 #ifdef CONFIG_MSTAR_CLKM
531
532 MS_S32 s32Handle;
533 char u8ClkSrcName[20] = "";
534 MS_U8 u8Idx = u8TsIf - 1;
535
536 switch(u16ClkSel)
537 {
538 case TSO_CLKIN_TS0:
539 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD0", u8Idx);
540 break;
541 case TSO_CLKIN_TS1:
542 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD1", u8Idx);
543 break;
544 case TSO_CLKIN_TS2:
545 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD2", u8Idx);
546 break;
547 case TSO_CLKIN_TS3:
548 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD3", u8Idx);
549 break;
550 case TSO_CLKIN_TS4:
551 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD4", u8Idx);
552 break;
553 case TSO_CLKIN_TS5:
554 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD5", u8Idx);
555 break;
556 default:
557 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
558 return FALSE;
559 }
560
561 switch(u8TsIf)
562 {
563 case HAL_TSO_TSIF_LIVE1:
564 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
565 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
566 break;
567 case HAL_TSO_TSIF_LIVE2:
568 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
569 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
570 break;
571 case HAL_TSO_TSIF_LIVE3:
572 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
573 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
574 break;
575 case HAL_TSO_TSIF_LIVE4:
576 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
577 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
578 break;
579 case HAL_TSO_TSIF_LIVE5:
580 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
581 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
582 break;
583 case HAL_TSO_TSIF_LIVE6:
584 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
585 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
586 break;
587 default:
588 printf("Not support !!\n");
589 return FALSE;
590 }
591
592 #endif
593
594 return TRUE;
595 }
596
597 #if 0
598 #define NPM_REG_ANAMISC 0x10C00 //0x110c00 //ana misc
599 #define NPM_REG_MIPS_PLLCLK (NPM_REG_ANAMISC+0x0002)
600 static MS_U32 _HAL_TSO_CPU_QueryClock(void)
601 {
602 MS_U32 u32Count = 0;
603 MS_U32 u32Speed = 0;
604 //here we assum that _u32TSORegBase is the same as non-PM bank
605 u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];
606 u32Count = ((u32Speed & 0xFF00) >> 8) * 12000000;
607
608 return u32Count;
609 }
610
611 static void _HAL_TSO_Delay(MS_U32 u32Us)
612 {
613 MS_U32 u32CPUClk = _HAL_TSO_CPU_QueryClock();
614 register MS_U32 u32Loop = (((u32CPUClk/1000000)/3)*(u32Us));// 3 cycles / loop
615 while(u32Loop--);
616 }
617 #endif
618
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)619 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
620 {
621 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
622 {
623 return FALSE; //not support yet
624 }
625
626 switch(u16PadSel)
627 {
628 case HAL_TSOIN_MUX_TS0:
629 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
630 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
631 break;
632 case HAL_TSOIN_MUX_TS1:
633 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
634 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
635 break;
636 case HAL_TSOIN_MUX_TS2:
637 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
638 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
639 break;
640 case HAL_TSOIN_MUX_TS3:
641 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
642 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS3IN;
643 break;
644 case HAL_TSOIN_MUX_TS4:
645 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
646 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS4IN;
647 break;
648 case HAL_TSOIN_MUX_TS5:
649 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
650 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS5IN;
651 break;
652 /*
653 case HAL_TSOIN_MUX_TSDEMOD0:
654 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
655 break;
656 */
657 case HAL_TSOIN_MUX_MEM:
658 case HAL_TSOIN_MUX_MEM1:
659 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV2N;
660 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
661 pstOutClkSet->u16OutDivNum = 0x0F; //default: 172.8/2*(15+1) = 5.4M
662 break;
663 default:
664 return FALSE;
665 }
666
667 return TRUE;
668 }
669
670
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)671 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16 *pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
672 {
673 //clock source for clock divide
674 if(bSet == TRUE)
675 {
676 /*
677 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
678 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
679 */
680
681 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
682 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
683
684 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
685 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum << REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT);
686 }
687 else
688 {
689 *pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
690 *pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT;
691 }
692
693 return TRUE;
694 }
695
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)696 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
697 {
698 if(bSet == TRUE)
699 {
700 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS6IN)
701 {
702 return FALSE;
703 }
704
705 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
706 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | ((*pu16PreTsoOutSel) << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
707 }
708 else
709 {
710 *pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN_TSO_P_TSO_OUT_MASK) >> REG_CLKGEN_TSO_P_TSO_OUT_SHIFT;
711 }
712
713 return TRUE;
714 }
715
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)716 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
717 {
718 if(bSet == TRUE)
719 {
720 if(pstOutClkSet->bEnable == FALSE)
721 {
722 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
723 return;
724 }
725
726 switch(pstOutClkSet->u16OutClk)
727 {
728 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
729 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
730 break;
731 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
732 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
733 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
734 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
735 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
736 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
737 break;
738 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
739 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
740 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
741 break;
742 default:
743 return;
744 }
745
746 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
747 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //always need TSO out clock
748 }
749 else
750 {
751 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
752 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV)
753 {
754 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
755 }
756 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
757 {
758 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
759 }
760 }
761 }
762
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)763 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
764 {
765 MS_U16 u16value = 0;
766 if(u8Eng == 0)
767 {
768 if(!bPhaseEnable)
769 {
770 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
771 }
772 else
773 {
774 u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)
775 | (u16ClkOutPhase << REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT);
776
777 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;
778 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
779 }
780 }
781 else
782 {
783 return FALSE;
784 }
785
786 return TRUE;
787 }
788
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)789 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
790 {
791 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
792
793 if(bSet == TRUE)
794 {
795 if(*pbEnable == FALSE)
796 {
797 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
798 }
799 else
800 {
801 /*
802 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
803 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
804 */
805 #ifndef CONFIG_MSTAR_CLKM
806 u16Clk |= (*pu16ClkOutSel << REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT);
807 #endif
808
809 if(*pbClkInvert)
810 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT;
811 }
812
813 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;
814
815 #ifdef CONFIG_MSTAR_CLKM
816
817 MS_S32 s32Handle;
818 MS_U8 u8NameIdx = 0;
819 char* u8ClkSrcNames[] =
820 {
821 "CLK_TSOOUT_27M",
822 "CLK_TSOOUT_62M",
823 "CLK_TSOOUT_108M",
824 "CLK_TSOOUT_FROMPAD",
825 "CLK_TSOOUT_DIV8",
826 "CLK_TSOOUT_DIV",
827 "CLK_TSOOUT_86M",
828 "CLK_TSOOUT_123M"
829 };
830
831 switch(*pu16ClkOutSel)
832 {
833 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
834 u8NameIdx = 0;
835 break;
836 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
837 u8NameIdx = 1;
838 break;
839 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
840 u8NameIdx = 2;
841 break;
842 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
843 u8NameIdx = 3;
844 break;
845 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
846 u8NameIdx = 4;
847 break;
848 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
849 u8NameIdx = 5;
850 break;
851 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
852 u8NameIdx = 6;
853 break;
854 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
855 u8NameIdx = 7;
856 break;
857 default:
858 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
859 return FALSE;
860 }
861
862 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_out");
863 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
864
865 #endif
866 }
867 else
868 {
869 *pbEnable = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_DISABLE) == 0);
870 *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT);
871 *pu16ClkOutSel = u16Clk >> REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT;
872 }
873
874 return TRUE;
875 }
876
HAL_TSO_Set_PidBypass(MS_U8 u8Eng,MS_BOOL bEnable)877 MS_BOOL HAL_TSO_Set_PidBypass(MS_U8 u8Eng, MS_BOOL bEnable)
878 {
879 if(bEnable)
880 {
881 switch(u8Eng)
882 {
883 case HAL_TSO_TSIF_LIVE1:
884 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
885 break;
886 case HAL_TSO_TSIF_LIVE2:
887 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
888 break;
889 case HAL_TSO_TSIF_LIVE3:
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
891 break;
892 case HAL_TSO_TSIF_LIVE4:
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
894 break;
895 case HAL_TSO_TSIF_LIVE5:
896 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
897 break;
898 case HAL_TSO_TSIF_LIVE6:
899 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
900 break;
901 default:
902 printf("Not support !!\n");
903 break;
904 }
905 }
906 else
907 {
908 switch(u8Eng)
909 {
910 case HAL_TSO_TSIF_LIVE1:
911 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
912 break;
913 case HAL_TSO_TSIF_LIVE2:
914 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
915 break;
916 case HAL_TSO_TSIF_LIVE3:
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
918 break;
919 case HAL_TSO_TSIF_LIVE4:
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
921 break;
922 case HAL_TSO_TSIF_LIVE5:
923 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
924 break;
925 case HAL_TSO_TSIF_LIVE6:
926 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
927 break;
928 default:
929 printf("Not support !!\n");
930 break;
931 }
932 }
933
934 return TRUE;
935 }
936
937 // ------------------------------------------------------
938 // APIS
939 //-------------------------------------------------------
940 #define TSO_PIDFLT_ADDR(FltId) (REG_PIDFLT_BASE + ((FltId) << 2))
941
_HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr,MS_U16 u16Wdata,MS_U8 u8Sid)942 static void _HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr, MS_U16 u16Wdata, MS_U8 u8Sid)
943 {
944 // addr
945 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
946 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
947
948 // Wdata
949 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
950 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F));
951
952 // Wen
953 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
954 }
955
_HAL_TSO_PageTableIndW(MS_U32 u32Addr,MS_U16 u16Wdata)956 static void _HAL_TSO_PageTableIndW(MS_U32 u32Addr, MS_U16 u16Wdata)
957 {
958 // addr
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
960 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
961
962 // Wdata
963 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
964 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000);
965
966 // Wen
967 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
968 }
969
_HAL_TSO_PageTableIndR(MS_U32 u32Addr)970 static MS_U16 _HAL_TSO_PageTableIndR(MS_U32 u32Addr)
971 {
972 // addr
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
974 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
975
976 // Ren
977 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN);
978
979 // Rdata
980 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA));
981 }
982
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)983 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
984 {
985 MS_U16 u16Temp = 0;
986
987 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
988 u16Temp = (u16Temp & (TSO_PIDFLT_IN_MASK << TSO_PIDFLT_IN_SHIFT)) | (u16PID & TSO_PIDFLT_PID_MASK);
989 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
990 }
991
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32Addr)992 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32Addr)
993 {
994 REG32_TSO *FileInRaddr;
995
996 MS_U8 u8MiuSel;
997 MS_PHY phyMiuOffsetFileinBuf;
998 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinBuf, u32Addr);
999
1000 if(u8FileEng == 0)
1001 {
1002 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]);
1003 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_CH5FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH5FILEIN_SHIFT) & REG_MIU_SEL_CH5FILEIN_MASK));
1004 }
1005 else
1006 {
1007 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]);
1008 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_2, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_2) & (~REG_MIU_SEL_CH6FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH6FILEIN_SHIFT) & REG_MIU_SEL_CH6FILEIN_MASK));
1009 }
1010
1011 _HAL_REG32_W(FileInRaddr, phyMiuOffsetFileinBuf);
1012 }
1013
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)1014 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
1015 {
1016 REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_68[1]);
1017
1018 _HAL_REG32_W(FileInRlen, u32len);
1019 }
1020
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)1021 MS_U32 HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
1022 {
1023 MS_U32 u32temp = 0;
1024 REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1);
1025 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1026
1027
1028 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1029 u32temp = (_HAL_REG32_R(TSO2MI_RADDR) << TSO_MIU_BUS);
1030 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1031
1032 return u32temp;
1033 }
1034
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)1035 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
1036 {
1037 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1038
1039 _HAL_REG16_W(FileinCtrl, (_HAL_REG16_R(FileinCtrl) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1040 }
1041
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)1042 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
1043 {
1044 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1045
1046 return (_HAL_REG16_R(FileinCtrl) & TSO_FILEIN_CTRL_MASK);
1047 }
1048
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1049 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1050 {
1051 MS_U16 u16ChIf = (u8FileEng == 0)? TSO_CFG1_TSO_TSIF5_EN : TSO_CFG1_TSO_TSIF6_EN;
1052
1053 HAL_TSO_Cfg1_Enable(0, u16ChIf, bEnable);
1054 HAL_TSO_File_Cfg1_Enable(u8FileEng, (TSO_FILE_CONFIG_TSO_FILE_IN|TSO_FILE_CONFIG_TSP_FILE_SEGMENT|TSO_FILE_CONFIG_TS_DATA_PORT_SEL), bEnable);
1055
1056 return TRUE;
1057 }
1058
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1059 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1060 {
1061 REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1062
1063 if(bEnable)
1064 {
1065 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) | TSO_FILE_CONFIG_TIMER_EN);
1066 }
1067 else
1068 {
1069 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) & ~TSO_FILE_CONFIG_TIMER_EN);
1070 }
1071 }
1072
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1073 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1074 {
1075 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer);
1076 }
1077
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1078 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1079 {
1080 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1081
1082 if(bEnable)
1083 {
1084 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_EN));
1085 }
1086 else
1087 {
1088 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_EN));
1089 }
1090 }
1091
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1092 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1093 {
1094 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1095
1096 if(bEnable)
1097 {
1098 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1099 }
1100 else
1101 {
1102 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1103 }
1104 }
1105
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1106 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1107 {
1108 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK;
1109 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT;
1110
1111 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1112 }
1113
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)1114 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)
1115 {
1116 //@TODO not implement
1117 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_FULL);
1118 return FALSE;
1119 }
1120
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)1121 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)
1122 {
1123 //@TODO not implement
1124 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_EMPTY);
1125 return FALSE;
1126 }
1127
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1128 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1129 {
1130 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK;
1131 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT;
1132
1133 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1134 }
1135
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1136 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1137 {
1138 MS_U16 u16data = ((u8FileEng == 0)? TSO_SW_RST_CMDQ : TSO_SW_RST_CMDQ1);
1139
1140 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1141 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1142
1143 return TRUE;
1144 }
1145
HAL_TSO_Cfg0_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1146 void HAL_TSO_Cfg0_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1147 {
1148 //@TODO not implement
1149 /*
1150 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG0));
1151
1152 if(benable)
1153 {
1154 u16data |= u16CfgItem;
1155 }
1156 else
1157 {
1158 u16data &= ~u16CfgItem;
1159 }
1160
1161 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG0), u16data);
1162 */
1163 }
1164
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1165 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1166 {
1167 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1));
1168
1169 if(benable)
1170 {
1171 u16data |= u16CfgItem;
1172 }
1173 else
1174 {
1175 u16data &= ~u16CfgItem;
1176 }
1177
1178 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD));
1179 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1180 }
1181
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1182 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1183 {
1184 switch(u8ChIf)
1185 {
1186 case HAL_TSO_TSIF_LIVE1:
1187 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1188 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1189 break;
1190 case HAL_TSO_TSIF_LIVE2:
1191 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1192 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1193 break;
1194 case HAL_TSO_TSIF_LIVE3:
1195 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1196 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1197 break;
1198 case HAL_TSO_TSIF_LIVE4:
1199 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1200 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1201 break;
1202 case HAL_TSO_TSIF_LIVE5:
1203 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1204 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1205 break;
1206 case HAL_TSO_TSIF_LIVE6:
1207 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1208 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1209 break;
1210 default:
1211 return FALSE;
1212 }
1213
1214 return TRUE;
1215 }
1216
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1217 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1218 {
1219 switch(u8ChIf)
1220 {
1221 case HAL_TSO_TSIF_LIVE1:
1222 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF1_EN, bEnable);
1223 break;
1224 case HAL_TSO_TSIF_LIVE2:
1225 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF2_EN, bEnable);
1226 break;
1227 case HAL_TSO_TSIF_LIVE3:
1228 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF3_EN, bEnable);
1229 break;
1230 case HAL_TSO_TSIF_LIVE4:
1231 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF4_EN, bEnable);
1232 break;
1233 case HAL_TSO_TSIF_LIVE5:
1234 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF5_EN, bEnable);
1235 break;
1236 case HAL_TSO_TSIF_LIVE6:
1237 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF6_EN, bEnable);
1238 break;
1239 default:
1240 return FALSE;
1241 }
1242
1243 return TRUE;
1244 }
1245
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1246 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1247 {
1248 REG16_TSO *reg = NULL;
1249 MS_U16 u16data = 0;
1250
1251 switch(u8ChIf)
1252 {
1253 case HAL_TSO_TSIF_LIVE1:
1254 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1255 break;
1256 case HAL_TSO_TSIF_LIVE2:
1257 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1258 break;
1259 case HAL_TSO_TSIF_LIVE3:
1260 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1261 break;
1262 case HAL_TSO_TSIF_LIVE4:
1263 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1264 break;
1265 case HAL_TSO_TSIF_LIVE5:
1266 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1267 break;
1268 case HAL_TSO_TSIF_LIVE6:
1269 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1270 break;
1271 default:
1272 return FALSE;
1273 }
1274
1275 u16data = _HAL_REG16_R(reg);
1276
1277 if(bEnable)
1278 {
1279 u16data |= u16Cfg;
1280 }
1281 else
1282 {
1283 u16data &= ~u16Cfg;
1284 }
1285
1286 _HAL_REG16_W(reg, u16data);
1287 return TRUE;
1288 }
1289
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1290 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1291 {
1292 REG16_TSO* pReg = NULL;
1293 MS_U16 u16data = 0;
1294
1295 *pu16Cfg = 0;
1296 *pbEnable = FALSE;
1297
1298 switch(u8ChIf)
1299 {
1300 case HAL_TSO_TSIF_LIVE1:
1301 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1302 break;
1303 case HAL_TSO_TSIF_LIVE2:
1304 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1305 break;
1306 case HAL_TSO_TSIF_LIVE3:
1307 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1308 break;
1309 case HAL_TSO_TSIF_LIVE4:
1310 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1311 break;
1312 case HAL_TSO_TSIF_LIVE5:
1313 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1314 break;
1315 case HAL_TSO_TSIF_LIVE6:
1316 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1317 break;
1318 default:
1319 return FALSE;
1320 }
1321
1322 *pu16Cfg = _HAL_REG16_R(pReg);
1323
1324 switch(u8ChIf)
1325 {
1326 case HAL_TSO_TSIF_LIVE1:
1327 u16data = TSO_CFG1_TSO_TSIF1_EN;
1328 break;
1329 case HAL_TSO_TSIF_LIVE2:
1330 u16data = TSO_CFG1_TSO_TSIF2_EN;
1331 break;
1332 case HAL_TSO_TSIF_LIVE3:
1333 u16data = TSO_CFG1_TSO_TSIF3_EN;
1334 break;
1335 case HAL_TSO_TSIF_LIVE4:
1336 u16data = TSO_CFG1_TSO_TSIF4_EN;
1337 break;
1338 case HAL_TSO_TSIF_LIVE5:
1339 u16data = TSO_CFG1_TSO_TSIF5_EN;
1340 break;
1341 case HAL_TSO_TSIF_LIVE6:
1342 u16data = TSO_CFG1_TSO_TSIF6_EN;
1343 break;
1344 default:
1345 return FALSE;
1346 }
1347
1348 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data);
1349
1350 return TRUE;
1351 }
1352
HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1353 void HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1354 {
1355 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1356 MS_U16 u16data = _HAL_REG16_R(reg);
1357
1358 if(benable)
1359 {
1360 u16data |= u16CfgItem;
1361 }
1362 else
1363 {
1364 u16data &= ~u16CfgItem;
1365 }
1366
1367 _HAL_REG16_W(reg, u16data);
1368 }
1369
1370
1371
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U32 u32CfgItem,MS_BOOL benable)1372 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U32 u32CfgItem, MS_BOOL benable)
1373 {
1374 //@TODO not implement
1375 /*
1376 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG4));
1377
1378 if(benable)
1379 {
1380 u16data |= u32CfgItem;
1381 }
1382 else
1383 {
1384 u16data &= ~u32CfgItem;
1385 }
1386
1387 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG4), u16data);
1388 */
1389 }
1390
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1391 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1392 {
1393 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1394
1395 if(bWrite)
1396 {
1397 u16data &= ~TSO_CONFIG2_VALID_BYTE_CNT_MASK;
1398 u16data |= (*pu16ValidBlockCnt << TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1399 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1400
1401 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1402 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1403 }
1404 else
1405 {
1406 *pu16ValidBlockCnt = ((u16data & TSO_CONFIG2_VALID_BYTE_CNT_MASK) >> TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1407 }
1408 }
1409
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1410 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1411 {
1412 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1413
1414 if(bWrite)
1415 {
1416 u16data &= ~TSO_CONFIG2_INVALID_BYTE_CNT_MASK;
1417 u16data |= (*pu16InvalidBlockCnt << TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT);
1418 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1419
1420 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1421 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1422 }
1423 else
1424 {
1425 *pu16InvalidBlockCnt = (u16data & TSO_CONFIG2_INVALID_BYTE_CNT_MASK) >> TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT;
1426 }
1427 }
1428
HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)1429 MS_U32 HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)
1430 {
1431 //@TODO not implement
1432 //return (_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK);
1433 return 0;
1434 }
1435
HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)1436 MS_U32 HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)
1437 {
1438 //@TODO not implement
1439 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK) >> TSO_HD_ADP_FIELD_SHIFT);
1440 return 0;
1441 }
1442
HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)1443 MS_U32 HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)
1444 {
1445 //@TODO not implement
1446 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PID_MASK) >> TSO_HD_PID_SHIFT);
1447 return 0;
1448 }
1449
HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)1450 MS_U32 HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)
1451 {
1452 //@TODO not implement
1453 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_SCRM_FIELD_MASK) >> TSO_HD_SCRM_FIELD_SHIFT);
1454 return 0;
1455 }
1456
HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)1457 MS_U32 HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)
1458 {
1459 //@TODO not implement
1460 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_TS_PRIORITY_MASK) >> TSO_HD_TS_PRIORITY_SHIFT);
1461 return 0;
1462 }
1463
HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)1464 MS_U32 HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)
1465 {
1466 //@TODO not implement
1467 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_START_IND_MASK) >> TSO_HD_PAYLOAD_START_IND_SHIFT);
1468 return 0;
1469 }
1470
HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)1471 MS_U32 HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)
1472 {
1473 //@TODO not implement
1474 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_ERR_IND_MASK) >> TSO_HD_PAYLOAD_ERR_IND_SHIFT);
1475 return 0;
1476 }
1477
HAL_TSO_Get_Pid_Info(MS_U8 u8Eng,MS_U16 * pu16matchpid,MS_BOOL * pbchanged)1478 void HAL_TSO_Get_Pid_Info(MS_U8 u8Eng, MS_U16 *pu16matchpid, MS_BOOL *pbchanged)
1479 {
1480 //@TODO not implement
1481 /*
1482 MS_U16 u16temp;
1483
1484 u16temp = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_PID_Info));
1485
1486 *pu16matchpid = u16temp & TSO_PID_INFO_MATCH_PID_MASK;
1487 *pbchanged = (((u16temp & TSO_PID_INFO_MATCH_PID_CHANGE_MASK) > 0) ? TRUE: FALSE);
1488 */
1489 }
1490
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1491 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1492 {
1493 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1494 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1495
1496
1497 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1498 _HAL_REG32_W(LPCR2, u32lpcr2);
1499 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1500 }
1501
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1502 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1503 {
1504 MS_U32 u32temp = 0;
1505 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1506 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1507
1508
1509 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1510 u32temp = _HAL_REG32_R(LPCR2);
1511 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1512
1513 return u32temp;
1514 }
1515
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1516 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1517 {
1518 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1);
1519
1520 return _HAL_REG32_R(TIMESTAMP);
1521 }
1522
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1523 void HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1524 {
1525 switch(u8If)
1526 {
1527 case HAL_TSO_TSIF_LIVE1:
1528 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1529 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1530 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1531 break;
1532 case HAL_TSO_TSIF_LIVE2:
1533 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1534 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1535 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1536 break;
1537 case HAL_TSO_TSIF_LIVE3:
1538 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1539 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1540 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1541 break;
1542 case HAL_TSO_TSIF_LIVE4:
1543 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1544 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1545 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1546 break;
1547 case HAL_TSO_TSIF_LIVE5:
1548 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1549 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1550 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1551 break;
1552 case HAL_TSO_TSIF_LIVE6:
1553 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1554 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1555 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1556 break;
1557 default:
1558 printf("Not support !!\n");
1559 break;
1560 }
1561 }
1562
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1563 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1564 {
1565 if(bWrite)
1566 {
1567 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize);
1568 }
1569 else
1570 {
1571 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3));
1572 }
1573
1574 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1575 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1576 }
1577
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1578 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1579 {
1580 switch(u8FileEng)
1581 {
1582 case 0:
1583 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1584 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK)
1585 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN_SHIFT)) & TSO_PKT_CHK_SIZE_FIN_MASK));
1586 break;
1587 case 1:
1588 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1589 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK)
1590 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN1_SHIFT)) & TSO_PKT_CHK_SIZE_FIN1_MASK));
1591 break;
1592 default:
1593 printf("Not support !!\n");
1594 break;
1595 }
1596 }
1597
HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1598 void HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1599 {
1600 switch(u8If)
1601 {
1602 case HAL_TSO_TSIF_LIVE1:
1603 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1604 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1605 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1606 break;
1607 case HAL_TSO_TSIF_LIVE2:
1608 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1609 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1610 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1611 break;
1612 case HAL_TSO_TSIF_LIVE3:
1613 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1614 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1615 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1616 break;
1617 case HAL_TSO_TSIF_LIVE4:
1618 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1619 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1620 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1621 break;
1622 case HAL_TSO_TSIF_LIVE5:
1623 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1624 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1625 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1626 break;
1627 case HAL_TSO_TSIF_LIVE6:
1628 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1629 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1630 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1631 break;
1632 default:
1633 printf("Not support !!\n");
1634 break;
1635 }
1636 }
1637
1638
HAL_TSO_Livein_Input_Config(MS_U8 u8Eng,MS_U8 u8PktInputMode,MS_U8 u8PktSyncByte,MS_U8 u8PktHeaderLength)1639 void HAL_TSO_Livein_Input_Config(MS_U8 u8Eng, MS_U8 u8PktInputMode, MS_U8 u8PktSyncByte, MS_U8 u8PktHeaderLength)
1640 {
1641 switch(u8Eng)
1642 {
1643 case HAL_TSO_TSIF_LIVE1:
1644 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1645 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK)
1646 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK));
1647
1648 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1649 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK)
1650 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK));
1651
1652 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1653 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK)
1654 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK));
1655 break;
1656 case HAL_TSO_TSIF_LIVE2:
1657 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1658 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK)
1659 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK));
1660
1661 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1662 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK)
1663 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK));
1664
1665 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1666 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK)
1667 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK));
1668 break;
1669 case HAL_TSO_TSIF_LIVE3:
1670 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1671 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK)
1672 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK));
1673
1674 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1675 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK)
1676 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK));
1677
1678 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1679 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK)
1680 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK));
1681 break;
1682 case HAL_TSO_TSIF_LIVE4:
1683 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1684 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK)
1685 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK));
1686
1687 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1688 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK)
1689 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK));
1690
1691 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1692 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK)
1693 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK));
1694 break;
1695 case HAL_TSO_TSIF_LIVE5:
1696 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1697 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK)
1698 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK));
1699
1700 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1701 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK)
1702 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK));
1703
1704 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1705 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK)
1706 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK));
1707 break;
1708 case HAL_TSO_TSIF_LIVE6:
1709 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1710 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK)
1711 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK));
1712
1713 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1714 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK)
1715 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK));
1716
1717 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1718 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK)
1719 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK));
1720 break;
1721 default:
1722 printf("Not support !!\n");
1723 break;
1724 }
1725 }
1726
1727
HAL_TSO_Livein_3Wire(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1728 void HAL_TSO_Livein_3Wire(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1729 {
1730 if(bEnable)
1731 {
1732 switch(u8ChIf)
1733 {
1734 case HAL_TSO_TSIF_LIVE1:
1735 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1736 break;
1737 case HAL_TSO_TSIF_LIVE2:
1738 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1739 break;
1740 case HAL_TSO_TSIF_LIVE3:
1741 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1742 break;
1743 case HAL_TSO_TSIF_LIVE4:
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1745 break;
1746 case HAL_TSO_TSIF_LIVE5:
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1748 break;
1749 case HAL_TSO_TSIF_LIVE6:
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1751 break;
1752 default:
1753 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1754 break;
1755 }
1756 }
1757 else
1758 {
1759 switch(u8ChIf)
1760 {
1761 case HAL_TSO_TSIF_LIVE1:
1762 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1763 break;
1764 case HAL_TSO_TSIF_LIVE2:
1765 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1766 break;
1767 case HAL_TSO_TSIF_LIVE3:
1768 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1769 break;
1770 case HAL_TSO_TSIF_LIVE4:
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1772 break;
1773 case HAL_TSO_TSIF_LIVE5:
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1775 break;
1776 case HAL_TSO_TSIF_LIVE6:
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1778 break;
1779 default:
1780 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1781 break;
1782 }
1783
1784 }
1785 }
1786
HAL_TSO_TsioMode_En(MS_BOOL bEnable)1787 void HAL_TSO_TsioMode_En(MS_BOOL bEnable)
1788 {
1789 if(bEnable)
1790 {
1791 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO_MODE);
1792 }
1793 else
1794 {
1795 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO_MODE);
1796 }
1797 }
1798
HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)1799 void HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)
1800 {
1801 if(bEnable)
1802 {
1803 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO2OPIF);
1804 }
1805 else
1806 {
1807 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_TSIO2OPIF);
1808 }
1809 }
1810
HAL_TSO_SerialMode_En(MS_BOOL bEnable)1811 void HAL_TSO_SerialMode_En(MS_BOOL bEnable)
1812 {
1813 if(bEnable)
1814 {
1815 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1816 }
1817 else
1818 {
1819 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1820 }
1821 }
1822
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1823 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1824 {
1825 REG32_TSO *Base = NULL;
1826 REG16_TSO *Size = NULL, *TX_Config = NULL;
1827 // Check MIU select
1828 MS_U8 u8MiuSel;
1829 MS_PHY phyMiuOffsetSVQBuf;
1830 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSVQBuf, phyBufAddr);
1831 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQRX_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQRX_SHIFT) & REG_MIU_SEL_SVQRX_MASK));
1832
1833
1834 switch(u8ChIf)
1835 {
1836 case HAL_TSO_TSIF_LIVE1:
1837 Base = &(_TSOCtrl1->SVQ1_BASE);
1838 Size = &(_TSOCtrl1->SVQ1_SIZE_200BYTE);
1839 TX_Config = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1840 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX1_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX1_SHIFT) & REG_MIU_SEL_SVQTX1_MASK));
1841 break;
1842 case HAL_TSO_TSIF_LIVE2:
1843 Base = &(_TSOCtrl1->SVQ2_BASE);
1844 Size = &(_TSOCtrl1->SVQ2_SIZE_200BYTE);
1845 TX_Config = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1846 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX2_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX2_SHIFT) & REG_MIU_SEL_SVQTX2_MASK));
1847 break;
1848 case HAL_TSO_TSIF_LIVE3:
1849 Base = &(_TSOCtrl1->SVQ3_BASE);
1850 Size = &(_TSOCtrl1->SVQ3_SIZE_200BYTE);
1851 TX_Config = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1852 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX3_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX3_SHIFT) & REG_MIU_SEL_SVQTX3_MASK));
1853 break;
1854 case HAL_TSO_TSIF_LIVE4:
1855 Base = &(_TSOCtrl1->SVQ4_BASE);
1856 Size = &(_TSOCtrl1->SVQ4_SIZE_200BYTE);
1857 TX_Config = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1858 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX4_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX4_SHIFT) & REG_MIU_SEL_SVQTX4_MASK));
1859 break;
1860 case HAL_TSO_TSIF_LIVE5:
1861 Base = &(_TSOCtrl1->SVQ5_BASE);
1862 Size = &(_TSOCtrl1->SVQ5_SIZE_200BYTE);
1863 TX_Config = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1864 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX5_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX5_SHIFT) & REG_MIU_SEL_SVQTX5_MASK));
1865 break;
1866 case HAL_TSO_TSIF_LIVE6:
1867 Base = &(_TSOCtrl1->SVQ6_BASE);
1868 Size = &(_TSOCtrl1->SVQ6_SIZE_200BYTE);
1869 TX_Config = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1870 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX6_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX6_SHIFT) & REG_MIU_SEL_SVQTX6_MASK));
1871 break;
1872 default:
1873 printf("Not support !!\n");
1874 return FALSE;
1875 }
1876
1877 _HAL_REG32_W(Base, ((phyMiuOffsetSVQBuf >> TSO_MIU_BUS) & TSO1_SVQ1_BASE_MASK));
1878 _HAL_REG16_W(Size, ((u32BufSize / TSO_SVQ_UNIT_SIZE) & TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK));
1879 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1880 _REG16_CLR(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1881 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);
1882
1883 return TRUE;
1884 }
1885
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1886 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1887 {
1888 REG16_TSO* p16Reg = NULL;
1889
1890 if(u8Eng > 0)
1891 {
1892 return FALSE;
1893 }
1894
1895 switch(u8ChIf)
1896 {
1897 case HAL_TSO_TSIF_LIVE1:
1898 p16Reg = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1899 break;
1900 case HAL_TSO_TSIF_LIVE2:
1901 p16Reg = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1902 break;
1903 case HAL_TSO_TSIF_LIVE3:
1904 p16Reg = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1905 break;
1906 case HAL_TSO_TSIF_LIVE4:
1907 p16Reg = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1908 break;
1909 case HAL_TSO_TSIF_LIVE5:
1910 p16Reg = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1911 break;
1912 case HAL_TSO_TSIF_LIVE6:
1913 p16Reg = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1914 break;
1915 default:
1916 printf("Not support !!\n");
1917 return FALSE;
1918 }
1919
1920 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1921 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1922 return TRUE;
1923 }
1924
HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem,MS_BOOL benable)1925 void HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem, MS_BOOL benable)
1926 {
1927 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG));
1928
1929 if(benable)
1930 {
1931 u16data |= u16CfgItem;
1932 }
1933 else
1934 {
1935 u16data &= ~u16CfgItem;
1936 }
1937
1938 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), u16data);
1939 }
1940
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1941 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1942 {
1943 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), (_HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG)) & ~TSO1_SVQ_RX_CONFIG_MODE_MASK) | u16mode);
1944
1945 return TRUE;
1946 }
1947
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1948 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1949 {
1950 MS_U32 u32data = 0;
1951 MS_U32 u32Shift = 0;
1952
1953 *pu16Status = 0;
1954 u32data = _HAL_REG32_R(&(_TSOCtrl1->SVQ_STATUS));
1955
1956 switch(u8ChIf)
1957 {
1958 case HAL_TSO_TSIF_LIVE1:
1959 u32Shift = TSO_SVQ1_STS_SHIFT;
1960 break;
1961 case HAL_TSO_TSIF_LIVE2:
1962 u32Shift = TSO_SVQ2_STS_SHIFT;
1963 break;
1964 case HAL_TSO_TSIF_LIVE3:
1965 u32Shift = TSO_SVQ3_STS_SHIFT;
1966 break;
1967 case HAL_TSO_TSIF_LIVE4:
1968 u32Shift = TSO_SVQ4_STS_SHIFT;
1969 break;
1970 case HAL_TSO_TSIF_LIVE5:
1971 u32Shift = TSO_SVQ5_STS_SHIFT;
1972 break;
1973 case HAL_TSO_TSIF_LIVE6:
1974 u32Shift = TSO_SVQ6_STS_SHIFT;
1975 break;
1976 default:
1977 return FALSE;
1978 }
1979
1980 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1981
1982 return TRUE;
1983 }
1984
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1985 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1986 {
1987 //@TODO not implement
1988 return TRUE;
1989 }
1990
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1991 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1992 {
1993 //@TODO not implement
1994 return TRUE;
1995 }
1996
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1997 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1998 {
1999 REG16_TSO* p16Reg = NULL;
2000
2001 switch(u8ChIf)
2002 {
2003 case HAL_TSO_TSIF_LIVE1:
2004 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_1_CONFIG_0);
2005 break;
2006 case HAL_TSO_TSIF_LIVE2:
2007 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_2_CONFIG_0);
2008 break;
2009 case HAL_TSO_TSIF_LIVE3:
2010 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_3_CONFIG_0);
2011 break;
2012 case HAL_TSO_TSIF_LIVE4:
2013 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_4_CONFIG_0);
2014 break;
2015 case HAL_TSO_TSIF_LIVE5:
2016 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_5_CONFIG_0);
2017 break;
2018 case HAL_TSO_TSIF_LIVE6:
2019 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_6_CONFIG_0);
2020 break;
2021 default:
2022 return FALSE;
2023 }
2024
2025 if(beSet == TRUE)
2026 {
2027 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2028 }
2029 else
2030 {
2031 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2032 }
2033
2034 return TRUE;
2035
2036 }
2037
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)2038 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
2039 {
2040 MS_U16 u16Temp = 0;
2041
2042 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2043 u16Temp = (u16Temp & TSO_PIDFLT_PID_MASK) | ((u16InputSrc & TSO_PIDFLT_IN_MASK) << TSO_PIDFLT_IN_SHIFT);
2044 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
2045 }
2046
HAL_TSO_Flt_SetSid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8Sid)2047 void HAL_TSO_Flt_SetSid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8Sid)
2048 {
2049 MS_U16 u16Temp = 0;
2050
2051 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2052 _HAL_TSO_PageTableIndW_withSid(TSO_PIDFLT_ADDR(u16FltId), u16Temp, u8Sid);
2053 }
2054
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)2055 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
2056 {
2057 //@TODO not implement
2058 return TRUE;
2059 }
2060
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)2061 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
2062 {
2063 //@TODO not implement
2064 return TRUE;
2065 }
2066
HAL_TSO_SaveRegs(void)2067 void HAL_TSO_SaveRegs(void)
2068 {
2069 //@TODO not implement
2070 }
2071
HAL_TSO_RestoreRegs(void)2072 void HAL_TSO_RestoreRegs(void)
2073 {
2074 //@TODO not implement
2075 }
2076
2077 #ifdef CONFIG_MSTAR_CLKM
HAL_TSO_PowerCtrl(MS_BOOL bOn)2078 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2079 {
2080 MS_S32 s32ClkHandle;
2081
2082 if (bOn)
2083 {
2084 // Enable TSO out Clock
2085 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2086 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOOUT_DIV");
2087
2088 // Enable TSO in Clock
2089 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2090 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOIN0_PAD0");
2091
2092 // Enable TSO1 in Clock
2093 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2094 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN1_PAD0");
2095
2096 // Enable TSO2 in Clock
2097 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2098 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN2_PAD0");
2099
2100 // Enable TSO3 in Clock
2101 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2102 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN3_PAD0");
2103
2104 // Enable TSO4 in Clock
2105 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2106 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN4_PAD0");
2107
2108 // Enable TSO5 in Clock
2109 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2110 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN5_PAD0");
2111
2112 // Disable MCM
2113 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2114 }
2115 else
2116 {
2117 // Enable MCM
2118 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2119
2120 // Disabel TSO out Clock
2121 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2122 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2123
2124 // Disabel TSO in Clock
2125 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2126 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2127
2128 // Disabel TSO1 in Clock
2129 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2130 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2131
2132 // Disabel TSO2 in Clock
2133 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2134 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2135
2136 // Disabel TSO3 in Clock
2137 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2138 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2139
2140 // Disabel TSO4 in Clock
2141 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2142 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2143
2144 // Disabel TSO5 in Clock
2145 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2146 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2147 }
2148 }
2149 #else
HAL_TSO_PowerCtrl(MS_BOOL bOn)2150 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2151 {
2152 if (bOn)
2153 {
2154 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
2155 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2156 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2157 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2158 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2159 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2160 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2161
2162 // Disable MCM
2163 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2164 }
2165 else
2166 {
2167 // Enable MCM
2168 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2169
2170 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
2171 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2172 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2173 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2174 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2175 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2176 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2177 }
2178 }
2179 #endif
2180
2181