1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halTSO.c
20 // @brief TS I/O HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "regTSO.h"
25 #include "halTSO.h"
26 #include "drvSYS.h"
27
28 #ifdef CONFIG_MSTAR_CLKM
29 #include "drvCLKM.h"
30 #endif
31
32 //--------------------------------------------------------------------------------------------------
33 // Driver Compiler Option
34 //--------------------------------------------------------------------------------------------------
35 #define TSP_HAL_REG_SAFE_MODE 1 // Register protection access between 1 task and 1+ ISR
36
37 #define MIU_BUS 4
38
39 #define KANOU02 (MDrv_SYS_GetChipRev() >= 0x1) // This feature/behavior is supported after Kano U02
40
41
42 //--------------------------------------------------------------------------------------------------
43 // TSP Hardware Abstraction Layer
44 //--------------------------------------------------------------------------------------------------
45 static REG_Ctrl_TSO* _TSOCtrl = NULL;
46 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
47
48 static MS_VIRT _u32TSORegBase = 0;
49
50 //-------------------------------------------------------------------------------------------------
51 // Debug Message
52 //-------------------------------------------------------------------------------------------------
53 typedef enum
54 {
55 E_HAL_TSO_DBG_LEVEL_NONE, // no debug message shown
56 E_HAL_TSO_DBG_LEVEL_ERR, // only shows error message that can't be recover
57 E_HAL_TSO_DBG_LEVEL_WARN, // error case can be recover, like retry
58 E_HAL_TSO_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
59 E_HAL_TSO_DBG_LEVEL_INFO, // information for internal parameter
60 E_HAL_TSO_DBG_LEVEL_FUNC, // Function trace and input parameter trace
61 E_HAL_TSO_DBG_LEVEL_TRACE, // debug trace
62 } EN_HAL_TSO_DBGMSG_LEVEL;
63
64 typedef enum
65 {
66 E_HAL_TSO_DBG_MODEL_NONE, // @temporarily , need to refine
67 E_HAL_TSO_DBG_MODEL_ALL,
68 } EN_HAL_TSO_DBGMSG_MODEL;
69
70 #define HAL_TSO_DBGMSG(_level,_model,_f) do {if(_u32TSODbgLevel >= (_level)&&((_u32TSODbgModel&_model)!=0)) (_f);} while(0)
71 static MS_U32 _u32TSODbgLevel = E_HAL_TSO_DBG_LEVEL_ERR;
72 static MS_U32 _u32TSODbgModel = E_HAL_TSO_DBG_MODEL_ALL;
73
74
75 //[NOTE] Jerry
76 // Some register has write order, for example, writing PCR_L will disable PCR counter
77 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
78 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
79 (reg)->H = ((value) >> 16); } while(0)
80
81 #define _HAL_REG16_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
82
83 //--------------------------------------------------------------------------------------------------
84 // Macro of bit operations
85 //--------------------------------------------------------------------------------------------------
86 #define HAS_FLAG(flag, bit) ((flag) & (bit))
87 #define SET_FLAG(flag, bit) ((flag)|= (bit))
88 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
89 #define SET_FLAG1(flag, bit) ((flag)| (bit))
90 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
91
92
93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));
94 #define _REG32_SET(reg, value); _HAL_REG32_W(reg, SET_FLAG1(_HAL_REG32_R(reg), value));
95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
96 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
97
98
99
100
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
102 #define REG_CLKGEN0_TSO_IN 0x27
103 #define REG_CLKGEN0_TSO_IN_MASK 0x001F
104 #define REG_CLKGEN0_TSO_IN_SHIFT 2
105 #define REG_CLKGEN0_TSO_IN_DISABLE 0x0001
106 #define REG_CLKGEN0_TSO_IN_INVERT 0x0002
107 // bit[4:0] -> 0: disable clock
108 // 1: invert clock
109 // bit [3:2] -> 000: select TS0_CLK
110 // 001: select TS1_CLK
111 // 010: from demod 0
112 #define REG_CLKGEN0_TSO_TRACE_MASK 0x0F00
113 #define REG_CLKGEN0_TSO_TRACE_DISABLE 0x0100
114 #define REG_CLKGEN0_TSO_TRACE_INVERT 0x0200
115 #define REG_CLKGEN0_TSO_TRACE_216M 0x0000
116
117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D
118 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK 0x001F
119 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT 0
120 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_EN_MASK 0x0020
121 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE 0x0020
122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040
123 #define HAL_TSO_OUT_DIV_SEL_172M_2N 0x0000
124 #define HAL_TSO_OUT_DIV_SEL_288M_2N 0x0040
125
126 #define REG_CLKGEN0_TSO_OUT_DIVNUM 0x2E
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0
128 #define REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT 6
129 #define REG_CLKGEN_TSO_P_TSO_OUT_MASK 0xF800
130 #define REG_CLKGEN_TSO_P_TSO_OUT_SHIFT 13
131
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F
133 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x001F
134 #define REG_CLKGEN0_TSO_OUT_CLK_DISABLE 0x0001
135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002
136 #define REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT 2
137 // bit[4:0] -> 0: disable clock
138 // 1: invert clock
139 // bit [4:2] -> 000: from demod 0, clk_dvbtc_ts_p
140 // 001: 62MHz
141 // 010: 54MHz
142 // 011: clk_p_tso_out (live in)
143 // 100: clk_p_tso_out_div8 (live in)
144 // 101: tso_out_div (clock/(N+1))
145 // 110: 86MHz
146
147 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))))
148 #define REG_CLKGEN1_DEMOD0_OUT_CLK 0x00
149 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_MASK 0x001F //demod0 div num of output clk
150 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_SHIFT 0
151 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_MASK 0x0100 //demod0 div src of output clk
152 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_SHIFT 8
153 // bit[8] -> 0: CLK_DMPLLDIV2
154 // 1: CLK_DMPLLDIV3
155
156 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
157 #define REG_CLKGEN2_TSO1_IN 0x06
158 #define REG_CLKGEN2_TSO2_IN 0x07
159 #define REG_CLKGEN2_TSO3_IN 0x08
160 #define REG_CLKGEN2_TSO4_IN 0x09
161 #define REG_CLKGEN2_TSO5_IN 0x0a
162
163 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
164 #define REG_TOP_TSO_MUX 0x3A
165 #define REG_TOP_TSO_MUX_MASK 0x0007
166 #define REG_TOP_TSO1_MUX_SHIFT 0
167 #define REG_TOP_TSO2_MUX_SHIFT 4
168 #define REG_TOP_TSO3_MUX_SHIFT 8
169 #define REG_TOP_TSO4_MUX_SHIFT 12
170
171 #define REG_TOP_TSO1_MUX 0x3B
172 #define REG_TOP_TSO5_MUX_SHIFT 0
173 #define REG_TOP_TSO6_MUX_SHIFT 4
174 // bit[2:0] -> 000: PAD_TS0
175 // 001: PAD_TS1
176 // 0111: DEMOD
177
178 #if 0 // Not used
179 #define REG_TOP_MIU_GP1_i64 0x21
180 #define REG_TOP_MIU_GP1_i64_TSO_MASK 0x0080
181 #define REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT 0x0000
182 #define REG_TOP_MIU_GP1_i64_TSO_64BIT_CLIENT 0x0080
183 #define REG_TOP_TS_CONFIG 0x57
184 #define REG_TOP_TS0_CONFIG_MASK 0x0700
185 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0100
186 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0200
187 #define REG_TOP_TS1_CONFIG_MASK 0x3800
188 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800
189 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000
190 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800
191 #define REG_TOP_TS2_CONFIG_MASK 0x4000
192 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x4000
193 #define REG_TOP_TSCB_CONFIG_MASK 0x8000
194 #define REG_TOP_TSCB_CONFIG_SERIAL_IN 0x8000
195 #define REG_TOP_TS_OUT_MODE 0x6E
196 #define REG_TOP_TS_OUT_MODE_MASK 0x0300
197 #define REG_TOP_TS_OUT_MODE_TSO 0x0200
198 #endif
199
200 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
201 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
202 #define REG_MIUDIG_MIU_SEL1 0x79
203 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080
204
205 //--------------------------------------------------------------------------------------------------
206 // Implementation
207 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_TSO * reg)208 static MS_U32 _HAL_REG32_R(REG32_TSO *reg)
209 {
210 MS_U32 value = 0;
211 value = (reg)->H << 16;
212 value |= (reg)->L;
213 return value;
214 }
215
_HAL_REG16_R(REG16_TSO * reg)216 static MS_U16 _HAL_REG16_R(REG16_TSO *reg)
217 {
218 MS_U16 value = 0;
219 value = (reg)->data;
220 return value;
221 }
222
HAL_TSO_SetBank(MS_VIRT u32BankAddr)223 void HAL_TSO_SetBank(MS_VIRT u32BankAddr)
224 {
225 _u32TSORegBase = u32BankAddr;
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706
227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612
228 }
229
230 //
231 // General API
232 //
HAL_TSO_Init(void)233 void HAL_TSO_Init(void)
234 {
235 //select MIU0, and 128bit MIU bus
236 /*
237 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
238 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
239 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
240 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
241 */
242
243 //KANO U02 ECO
244 if(KANOU02)
245 {
246 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);
247 }
248 }
249
HAL_TSO_Reset_All(MS_U8 u8Eng)250 void HAL_TSO_Reset_All(MS_U8 u8Eng)
251 {
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);
254
255 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
257 }
258
HAL_TSO_Reset(MS_U8 u8Eng)259 void HAL_TSO_Reset(MS_U8 u8Eng)
260 {
261 //@TODO not find in register table
262 /*
263 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
264 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
265 */
266 }
267
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)268 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
269 {
270 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem));
271 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem));
272 }
273
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL benable,MS_U16 u16init)274 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL benable, MS_U16 u16init)
275 {
276 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
277 MS_U16 u16data = _HAL_REG16_R(reg);
278
279 if(benable)
280 {
281 _HAL_REG16_W(reg, (u16data | u16init));
282 }
283 else
284 {
285 _HAL_REG16_W(reg, (u16data & ~u16init));
286 }
287 }
288
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)289 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
290 {
291 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
292
293 _HAL_REG16_W(reg, (_HAL_REG16_R(reg) & ~u16Int));
294 }
295
HAL_TSO_HWInt_Status(MS_U8 u8Eng)296 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
297 {
298 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
299
300 return (_HAL_REG16_R(reg) & TSO_INT_STS_MASK);
301 }
302
HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId,MS_U16 * u16Pad,MS_U16 * u16Clk)303 MS_BOOL HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId, MS_U16 *u16Pad, MS_U16 *u16Clk)
304 {
305 switch(u8Pad3WireId)
306 {
307 case 0:
308 *u16Pad = HAL_TSOIN_MUX_TS3;
309 *u16Clk = TSO_CLKIN_TS3;
310 break;
311 case 1:
312 *u16Pad = HAL_TSOIN_MUX_TS4;
313 *u16Clk = TSO_CLKIN_TS4;
314 break;
315 case 2:
316 *u16Pad = HAL_TSOIN_MUX_TS5;
317 *u16Clk = TSO_CLKIN_TS5;
318 break;
319 case 3:
320 *u16Pad = HAL_TSOIN_MUX_TS6;
321 *u16Clk = TSO_CLKIN_TS6;
322 break;
323 default:
324 printf("[%s][%d]: Not support !!\n", __FUNCTION__, __LINE__);
325 return FALSE;
326 }
327
328 return TRUE;
329 }
330
331
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)332 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
333 {
334 MS_U16 u16Reg, u16RegShift;
335
336 switch(u8TsIf)
337 {
338 case HAL_TSO_TSIF_LIVE1:
339 u16Reg = REG_TOP_TSO_MUX;
340 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
341 break;
342 case HAL_TSO_TSIF_LIVE2:
343 u16Reg = REG_TOP_TSO_MUX;
344 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
345 break;
346 case HAL_TSO_TSIF_LIVE3:
347 u16Reg = REG_TOP_TSO_MUX;
348 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
349 break;
350 case HAL_TSO_TSIF_LIVE4:
351 u16Reg = REG_TOP_TSO_MUX;
352 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
353 break;
354 case HAL_TSO_TSIF_LIVE5:
355 u16Reg = REG_TOP_TSO1_MUX;
356 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
357 break;
358 case HAL_TSO_TSIF_LIVE6:
359 u16Reg = REG_TOP_TSO1_MUX;
360 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
361 break;
362 default:
363 printf("Not support !!\n");
364 return FALSE;
365 }
366
367 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~(REG_TOP_TSO_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
368
369 //@NOTE: no need to change input pad mode dynamically (Mboot handle it...)
370
371 return TRUE;
372 }
373
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)374 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
375 {
376 //@TODO not implement
377 return TRUE;
378 }
379
380
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)381 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
382 {
383 MS_U16 u16Reg, u16RegShift;
384 MS_U16 u16data = 0;
385 REG16_TSO* reg16 = 0;
386
387 // Set pad mux
388 switch(u8TsIf)
389 {
390 case HAL_TSO_TSIF_LIVE1:
391 u16Reg = REG_TOP_TSO_MUX;
392 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
393 break;
394 case HAL_TSO_TSIF_LIVE2:
395 u16Reg = REG_TOP_TSO_MUX;
396 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
397 break;
398 case HAL_TSO_TSIF_LIVE3:
399 u16Reg = REG_TOP_TSO_MUX;
400 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
401 break;
402 case HAL_TSO_TSIF_LIVE4:
403 u16Reg = REG_TOP_TSO_MUX;
404 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
405 break;
406 case HAL_TSO_TSIF_LIVE5:
407 u16Reg = REG_TOP_TSO1_MUX;
408 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
409 break;
410 case HAL_TSO_TSIF_LIVE6:
411 u16Reg = REG_TOP_TSO1_MUX;
412 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
413 break;
414 default:
415 printf("Not support !!\n");
416 return FALSE;
417 }
418
419 *pu16Pad = (TSP_TOP_REG(u16Reg) >> u16RegShift) & REG_TOP_TSO_MUX_MASK;
420
421 switch(u8TsIf)
422 {
423 case HAL_TSO_TSIF_LIVE1:
424 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK;
425 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
426 break;
427 case HAL_TSO_TSIF_LIVE2:
428 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;
429 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
430 break;
431 case HAL_TSO_TSIF_LIVE3:
432 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;
433 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
434 break;
435 case HAL_TSO_TSIF_LIVE4:
436 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;
437 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
438 break;
439 case HAL_TSO_TSIF_LIVE5:
440 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;
441 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
442 break;
443 case HAL_TSO_TSIF_LIVE6:
444 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;
445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
446 break;
447 }
448
449 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
450 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
451 *pbClkInvert = ((u16data & REG_CLKGEN0_TSO_IN_INVERT) == REG_CLKGEN0_TSO_IN_INVERT);
452
453 return TRUE;
454 }
455
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)456 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
457 {
458 MS_BOOL isCLKGEN0 = FALSE;
459 MS_U16 u16Reg;
460 MS_U16 u16value = 0;
461
462 switch(u8TsIf)
463 {
464 case HAL_TSO_TSIF_LIVE1:
465 isCLKGEN0 = TRUE;
466 u16Reg = REG_CLKGEN0_TSO_IN;
467 break;
468 case HAL_TSO_TSIF_LIVE2:
469 u16Reg = REG_CLKGEN2_TSO1_IN;
470 break;
471 case HAL_TSO_TSIF_LIVE3:
472 u16Reg = REG_CLKGEN2_TSO2_IN;
473 break;
474 case HAL_TSO_TSIF_LIVE4:
475 u16Reg = REG_CLKGEN2_TSO3_IN;
476 break;
477 case HAL_TSO_TSIF_LIVE5:
478 u16Reg = REG_CLKGEN2_TSO4_IN;
479 break;
480 case HAL_TSO_TSIF_LIVE6:
481 u16Reg = REG_CLKGEN2_TSO5_IN;
482 break;
483 default:
484 printf("Not support !!\n");
485 return FALSE;
486 }
487
488 if(u16ClkSel == 0xFFFF)
489 {
490 return FALSE;
491 }
492
493 if(isCLKGEN0)
494 {
495 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
496 }
497 else
498 {
499 u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
500 }
501
502 if(!bEnable)
503 {
504 u16value |= REG_CLKGEN0_TSO_IN_DISABLE;
505 }
506 else
507 {
508 #ifndef CONFIG_MSTAR_CLKM
509 u16value |= (u16ClkSel << REG_CLKGEN0_TSO_IN_SHIFT);
510 #endif
511
512 if(bClkInvert)
513 {
514 u16value |= REG_CLKGEN0_TSO_IN_INVERT;
515 }
516 }
517
518 if(isCLKGEN0)
519 {
520 TSO_CLKGEN0_REG(u16Reg) = u16value;
521 }
522 else
523 {
524 TSO_CLKGEN2_REG(u16Reg) = u16value;
525 }
526
527 #ifdef CONFIG_MSTAR_CLKM
528
529 MS_S32 s32Handle;
530 char u8ClkSrcName[20] = "";
531 MS_U8 u8Idx = u8TsIf - 1;
532
533 switch(u16ClkSel)
534 {
535 case TSO_CLKIN_TS0:
536 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD0", u8Idx);
537 break;
538 case TSO_CLKIN_TS1:
539 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD1", u8Idx);
540 break;
541 case TSO_CLKIN_TS2:
542 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD2", u8Idx);
543 break;
544 case TSO_CLKIN_TS3:
545 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD3", u8Idx);
546 break;
547 case TSO_CLKIN_TS4:
548 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD4", u8Idx);
549 break;
550 case TSO_CLKIN_TS5:
551 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD5", u8Idx);
552 break;
553 default:
554 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
555 return FALSE;
556 }
557
558 switch(u8TsIf)
559 {
560 case HAL_TSO_TSIF_LIVE1:
561 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
562 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
563 break;
564 case HAL_TSO_TSIF_LIVE2:
565 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
566 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
567 break;
568 case HAL_TSO_TSIF_LIVE3:
569 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
570 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
571 break;
572 case HAL_TSO_TSIF_LIVE4:
573 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
574 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
575 break;
576 case HAL_TSO_TSIF_LIVE5:
577 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
578 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
579 break;
580 case HAL_TSO_TSIF_LIVE6:
581 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
582 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
583 break;
584 default:
585 printf("Not support !!\n");
586 return FALSE;
587 }
588
589 #endif
590
591 return TRUE;
592 }
593
594 #if 0
595 #define NPM_REG_ANAMISC 0x10C00 //0x110c00 //ana misc
596 #define NPM_REG_MIPS_PLLCLK (NPM_REG_ANAMISC+0x0002)
597 static MS_U32 _HAL_TSO_CPU_QueryClock(void)
598 {
599 MS_U32 u32Count = 0;
600 MS_U32 u32Speed = 0;
601 //here we assum that _u32TSORegBase is the same as non-PM bank
602 u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];
603 u32Count = ((u32Speed & 0xFF00) >> 8) * 12000000;
604
605 return u32Count;
606 }
607
608 static void _HAL_TSO_Delay(MS_U32 u32Us)
609 {
610 MS_U32 u32CPUClk = _HAL_TSO_CPU_QueryClock();
611 register MS_U32 u32Loop = (((u32CPUClk/1000000)/3)*(u32Us));// 3 cycles / loop
612 while(u32Loop--);
613 }
614 #endif
615
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)616 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
617 {
618 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
619 {
620 return FALSE; //not support yet
621 }
622
623 switch(u16PadSel)
624 {
625 case HAL_TSOIN_MUX_TS0:
626 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
627 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
628 break;
629 case HAL_TSOIN_MUX_TS1:
630 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
631 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
632 break;
633 case HAL_TSOIN_MUX_TS2:
634 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
635 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
636 break;
637 case HAL_TSOIN_MUX_TS3:
638 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
639 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS3IN;
640 break;
641 case HAL_TSOIN_MUX_TS4:
642 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
643 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS4IN;
644 break;
645 case HAL_TSOIN_MUX_TS5:
646 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
647 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS5IN;
648 break;
649 /*
650 case HAL_TSOIN_MUX_TSDEMOD0:
651 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
652 break;
653 */
654 case HAL_TSOIN_MUX_MEM:
655 case HAL_TSOIN_MUX_MEM1:
656 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV;
657 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
658 pstOutClkSet->u16OutDivNum = 0x1F; //default: 172.8/(31+1) = 5.4M
659 break;
660 default:
661 return FALSE;
662 }
663
664 return TRUE;
665 }
666
667
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)668 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16 *pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
669 {
670 //clock source for clock divide
671 if(bSet == TRUE)
672 {
673 /*
674 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
675 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
676 */
677
678 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
679 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
680
681 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
682 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum << REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT);
683 }
684 else
685 {
686 *pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
687 *pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT;
688 }
689
690 return TRUE;
691 }
692
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)693 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
694 {
695 if(bSet == TRUE)
696 {
697 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS6IN)
698 {
699 return FALSE;
700 }
701
702 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
703 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | ((*pu16PreTsoOutSel) << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
704 }
705 else
706 {
707 *pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN_TSO_P_TSO_OUT_MASK) >> REG_CLKGEN_TSO_P_TSO_OUT_SHIFT;
708 }
709
710 return TRUE;
711 }
712
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)713 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
714 {
715 if(bSet == TRUE)
716 {
717 if(pstOutClkSet->bEnable == FALSE)
718 {
719 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
720 return;
721 }
722
723 switch(pstOutClkSet->u16OutClk)
724 {
725 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
726 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
727 break;
728 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
729 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
730 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
731 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
732 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
733 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
734 break;
735 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
736 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
737 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
738 break;
739 default:
740 return;
741 }
742
743 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
744 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //always need TSO out clock
745 }
746 else
747 {
748 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
749 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV)
750 {
751 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
752 }
753 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
754 {
755 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
756 }
757 }
758 }
759
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)760 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
761 {
762 MS_U16 u16value = 0;
763 if(u8Eng == 0)
764 {
765 if(!bPhaseEnable)
766 {
767 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
768 }
769 else
770 {
771 u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)
772 | (u16ClkOutPhase << REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT);
773
774 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;
775 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
776 }
777 }
778 else
779 {
780 return FALSE;
781 }
782
783 return TRUE;
784 }
785
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)786 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
787 {
788 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
789
790 if(bSet == TRUE)
791 {
792 if(*pbEnable == FALSE)
793 {
794 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
795 }
796 else
797 {
798 /*
799 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
800 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
801 */
802 #ifndef CONFIG_MSTAR_CLKM
803 u16Clk |= (*pu16ClkOutSel << REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT);
804 #endif
805
806 if(*pbClkInvert)
807 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT;
808 }
809
810 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;
811
812 #ifdef CONFIG_MSTAR_CLKM
813
814 MS_S32 s32Handle;
815 MS_U8 u8NameIdx = 0;
816 char* u8ClkSrcNames[] =
817 {
818 "CLK_TSOOUT_27M",
819 "CLK_TSOOUT_62M",
820 "CLK_TSOOUT_108M",
821 "CLK_TSOOUT_FROMPAD",
822 "CLK_TSOOUT_DIV8",
823 "CLK_TSOOUT_DIV",
824 "CLK_TSOOUT_86M",
825 "CLK_TSOOUT_123M"
826 };
827
828 switch(*pu16ClkOutSel)
829 {
830 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
831 u8NameIdx = 0;
832 break;
833 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
834 u8NameIdx = 1;
835 break;
836 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
837 u8NameIdx = 2;
838 break;
839 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
840 u8NameIdx = 3;
841 break;
842 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
843 u8NameIdx = 4;
844 break;
845 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
846 u8NameIdx = 5;
847 break;
848 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
849 u8NameIdx = 6;
850 break;
851 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
852 u8NameIdx = 7;
853 break;
854 default:
855 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
856 return FALSE;
857 }
858
859 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_out");
860 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
861
862 #endif
863 }
864 else
865 {
866 *pbEnable = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_DISABLE) == 0);
867 *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT);
868 *pu16ClkOutSel = u16Clk >> REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT;
869 }
870
871 return TRUE;
872 }
873
HAL_TSO_Set_PidBypass(MS_U8 u8Eng,MS_BOOL bEnable)874 MS_BOOL HAL_TSO_Set_PidBypass(MS_U8 u8Eng, MS_BOOL bEnable)
875 {
876 if(bEnable)
877 {
878 switch(u8Eng)
879 {
880 case HAL_TSO_TSIF_LIVE1:
881 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
882 break;
883 case HAL_TSO_TSIF_LIVE2:
884 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
885 break;
886 case HAL_TSO_TSIF_LIVE3:
887 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
888 break;
889 case HAL_TSO_TSIF_LIVE4:
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
891 break;
892 case HAL_TSO_TSIF_LIVE5:
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
894 break;
895 case HAL_TSO_TSIF_LIVE6:
896 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
897 break;
898 default:
899 printf("Not support !!\n");
900 break;
901 }
902 }
903 else
904 {
905 switch(u8Eng)
906 {
907 case HAL_TSO_TSIF_LIVE1:
908 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
909 break;
910 case HAL_TSO_TSIF_LIVE2:
911 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
912 break;
913 case HAL_TSO_TSIF_LIVE3:
914 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
915 break;
916 case HAL_TSO_TSIF_LIVE4:
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
918 break;
919 case HAL_TSO_TSIF_LIVE5:
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
921 break;
922 case HAL_TSO_TSIF_LIVE6:
923 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
924 break;
925 default:
926 printf("Not support !!\n");
927 break;
928 }
929 }
930
931 return TRUE;
932 }
933
934 // ------------------------------------------------------
935 // APIS
936 //-------------------------------------------------------
937 #define TSO_PIDFLT_ADDR(FltId) (REG_PIDFLT_BASE + ((FltId) << 2))
938
_HAL_TSO_PageTableIndW(MS_U32 u32Addr,MS_U16 u16Wdata)939 static void _HAL_TSO_PageTableIndW(MS_U32 u32Addr, MS_U16 u16Wdata)
940 {
941 // addr
942 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
943 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
944
945 // Wdata
946 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
947 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000);
948
949 // Wen
950 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
951 }
952
_HAL_TSO_PageTableIndR(MS_U32 u32Addr)953 static MS_U16 _HAL_TSO_PageTableIndR(MS_U32 u32Addr)
954 {
955 // addr
956 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
957 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
958
959 // Ren
960 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN);
961
962 // Rdata
963 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA));
964 }
965
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)966 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
967 {
968 MS_U16 u16Temp = 0;
969
970 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
971 u16Temp = (u16Temp & (TSO_PIDFLT_IN_MASK << TSO_PIDFLT_IN_SHIFT)) | (u16PID & TSO_PIDFLT_PID_MASK);
972 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
973 }
974
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32Addr)975 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32Addr)
976 {
977 REG32_TSO *FileInRaddr = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[0]) : &(_TSOCtrl->CFG_TSO_65_68[0]);
978
979 _HAL_REG32_W(FileInRaddr, u32Addr);
980 }
981
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)982 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
983 {
984 REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_68[1]);
985
986 _HAL_REG32_W(FileInRlen, u32len);
987 }
988
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)989 MS_U32 HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
990 {
991 MS_U32 u32temp = 0;
992 REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1);
993 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
994
995
996 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
997 u32temp = (_HAL_REG32_R(TSO2MI_RADDR) << TSO_MIU_BUS);
998 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
999
1000 return u32temp;
1001 }
1002
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)1003 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
1004 {
1005 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1006
1007 _HAL_REG16_W(FileinCtrl, (_HAL_REG16_R(FileinCtrl) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1008 }
1009
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)1010 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
1011 {
1012 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1013
1014 return (_HAL_REG16_R(FileinCtrl) & TSO_FILEIN_CTRL_MASK);
1015 }
1016
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1017 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1018 {
1019 MS_U16 u16ChIf = (u8FileEng == 0)? TSO_CFG1_TSO_TSIF5_EN : TSO_CFG1_TSO_TSIF6_EN;
1020
1021 HAL_TSO_Cfg1_Enable(0, u16ChIf, bEnable);
1022 HAL_TSO_File_Cfg1_Enable(u8FileEng, (TSO_FILE_CONFIG_TSO_FILE_IN|TSO_FILE_CONFIG_TSP_FILE_SEGMENT|TSO_FILE_CONFIG_TS_DATA_PORT_SEL), bEnable);
1023
1024 return TRUE;
1025 }
1026
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1027 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1028 {
1029 REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1030
1031 if(bEnable)
1032 {
1033 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) | TSO_FILE_CONFIG_TIMER_EN);
1034 }
1035 else
1036 {
1037 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) & ~TSO_FILE_CONFIG_TIMER_EN);
1038 }
1039 }
1040
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1041 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1042 {
1043 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer);
1044 }
1045
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1046 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1047 {
1048 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1049
1050 if(bEnable)
1051 {
1052 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_EN));
1053 }
1054 else
1055 {
1056 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_EN));
1057 }
1058 }
1059
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1060 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1061 {
1062 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1063
1064 if(bEnable)
1065 {
1066 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1067 }
1068 else
1069 {
1070 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1071 }
1072 }
1073
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1074 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1075 {
1076 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK;
1077 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT;
1078
1079 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1080 }
1081
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)1082 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)
1083 {
1084 //@TODO not implement
1085 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_FULL);
1086 return FALSE;
1087 }
1088
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)1089 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)
1090 {
1091 //@TODO not implement
1092 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_EMPTY);
1093 return FALSE;
1094 }
1095
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1096 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1097 {
1098 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK;
1099 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT;
1100
1101 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1102 }
1103
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1104 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1105 {
1106 MS_U16 u16data = ((u8FileEng == 0)? TSO_SW_RST_CMDQ : TSO_SW_RST_CMDQ1);
1107
1108 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1109 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1110
1111 return TRUE;
1112 }
1113
HAL_TSO_Cfg0_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1114 void HAL_TSO_Cfg0_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1115 {
1116 //@TODO not implement
1117 /*
1118 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG0));
1119
1120 if(benable)
1121 {
1122 u16data |= u16CfgItem;
1123 }
1124 else
1125 {
1126 u16data &= ~u16CfgItem;
1127 }
1128
1129 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG0), u16data);
1130 */
1131 }
1132
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1133 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1134 {
1135 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1));
1136
1137 if(benable)
1138 {
1139 u16data |= u16CfgItem;
1140 }
1141 else
1142 {
1143 u16data &= ~u16CfgItem;
1144 }
1145
1146 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD));
1147 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1148 }
1149
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1150 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1151 {
1152 switch(u8ChIf)
1153 {
1154 case HAL_TSO_TSIF_LIVE1:
1155 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1156 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1157 break;
1158 case HAL_TSO_TSIF_LIVE2:
1159 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1160 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1161 break;
1162 case HAL_TSO_TSIF_LIVE3:
1163 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1164 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1165 break;
1166 case HAL_TSO_TSIF_LIVE4:
1167 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1168 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1169 break;
1170 case HAL_TSO_TSIF_LIVE5:
1171 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1172 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1173 break;
1174 case HAL_TSO_TSIF_LIVE6:
1175 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1176 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1177 break;
1178 default:
1179 return FALSE;
1180 }
1181
1182 return TRUE;
1183 }
1184
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1185 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1186 {
1187 switch(u8ChIf)
1188 {
1189 case HAL_TSO_TSIF_LIVE1:
1190 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF1_EN, bEnable);
1191 break;
1192 case HAL_TSO_TSIF_LIVE2:
1193 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF2_EN, bEnable);
1194 break;
1195 case HAL_TSO_TSIF_LIVE3:
1196 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF3_EN, bEnable);
1197 break;
1198 case HAL_TSO_TSIF_LIVE4:
1199 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF4_EN, bEnable);
1200 break;
1201 case HAL_TSO_TSIF_LIVE5:
1202 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF5_EN, bEnable);
1203 break;
1204 case HAL_TSO_TSIF_LIVE6:
1205 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF6_EN, bEnable);
1206 break;
1207 default:
1208 return FALSE;
1209 }
1210
1211 return TRUE;
1212 }
1213
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1214 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1215 {
1216 REG16_TSO *reg = NULL;
1217 MS_U16 u16data = 0;
1218
1219 switch(u8ChIf)
1220 {
1221 case HAL_TSO_TSIF_LIVE1:
1222 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1223 break;
1224 case HAL_TSO_TSIF_LIVE2:
1225 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1226 break;
1227 case HAL_TSO_TSIF_LIVE3:
1228 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1229 break;
1230 case HAL_TSO_TSIF_LIVE4:
1231 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1232 break;
1233 case HAL_TSO_TSIF_LIVE5:
1234 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1235 break;
1236 case HAL_TSO_TSIF_LIVE6:
1237 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1238 break;
1239 default:
1240 return FALSE;
1241 }
1242
1243 u16data = _HAL_REG16_R(reg);
1244
1245 if(bEnable)
1246 {
1247 u16data |= u16Cfg;
1248 }
1249 else
1250 {
1251 u16data &= ~u16Cfg;
1252 }
1253
1254 _HAL_REG16_W(reg, u16data);
1255 return TRUE;
1256 }
1257
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1258 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1259 {
1260 REG16_TSO* pReg = NULL;
1261 MS_U16 u16data = 0;
1262
1263 *pu16Cfg = 0;
1264 *pbEnable = FALSE;
1265
1266 switch(u8ChIf)
1267 {
1268 case HAL_TSO_TSIF_LIVE1:
1269 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1270 break;
1271 case HAL_TSO_TSIF_LIVE2:
1272 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1273 break;
1274 case HAL_TSO_TSIF_LIVE3:
1275 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1276 break;
1277 case HAL_TSO_TSIF_LIVE4:
1278 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1279 break;
1280 case HAL_TSO_TSIF_LIVE5:
1281 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1282 break;
1283 case HAL_TSO_TSIF_LIVE6:
1284 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1285 break;
1286 default:
1287 return FALSE;
1288 }
1289
1290 *pu16Cfg = _HAL_REG16_R(pReg);
1291
1292 switch(u8ChIf)
1293 {
1294 case HAL_TSO_TSIF_LIVE1:
1295 u16data = TSO_CFG1_TSO_TSIF1_EN;
1296 break;
1297 case HAL_TSO_TSIF_LIVE2:
1298 u16data = TSO_CFG1_TSO_TSIF2_EN;
1299 break;
1300 case HAL_TSO_TSIF_LIVE3:
1301 u16data = TSO_CFG1_TSO_TSIF3_EN;
1302 break;
1303 case HAL_TSO_TSIF_LIVE4:
1304 u16data = TSO_CFG1_TSO_TSIF4_EN;
1305 break;
1306 case HAL_TSO_TSIF_LIVE5:
1307 u16data = TSO_CFG1_TSO_TSIF5_EN;
1308 break;
1309 case HAL_TSO_TSIF_LIVE6:
1310 u16data = TSO_CFG1_TSO_TSIF6_EN;
1311 break;
1312 }
1313
1314 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data);
1315
1316 return TRUE;
1317 }
1318
HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1319 void HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1320 {
1321 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1322 MS_U16 u16data = _HAL_REG16_R(reg);
1323
1324 if(benable)
1325 {
1326 u16data |= u16CfgItem;
1327 }
1328 else
1329 {
1330 u16data &= ~u16CfgItem;
1331 }
1332
1333 _HAL_REG16_W(reg, u16data);
1334 }
1335
1336
1337
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U32 u32CfgItem,MS_BOOL benable)1338 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U32 u32CfgItem, MS_BOOL benable)
1339 {
1340 //@TODO not implement
1341 /*
1342 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG4));
1343
1344 if(benable)
1345 {
1346 u16data |= u32CfgItem;
1347 }
1348 else
1349 {
1350 u16data &= ~u32CfgItem;
1351 }
1352
1353 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG4), u16data);
1354 */
1355 }
1356
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1357 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1358 {
1359 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1360
1361 if(bWrite)
1362 {
1363 u16data &= ~TSO_CONFIG2_VALID_BYTE_CNT_MASK;
1364 u16data |= (*pu16ValidBlockCnt << TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1365 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1366
1367 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1368 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1369 }
1370 else
1371 {
1372 *pu16ValidBlockCnt = ((u16data & TSO_CONFIG2_VALID_BYTE_CNT_MASK) >> TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1373 }
1374 }
1375
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1376 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1377 {
1378 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1379
1380 if(bWrite)
1381 {
1382 u16data &= ~TSO_CONFIG2_INVALID_BYTE_CNT_MASK;
1383 u16data |= (*pu16InvalidBlockCnt << TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT);
1384 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1385
1386 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1387 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1388 }
1389 else
1390 {
1391 *pu16InvalidBlockCnt = (u16data & TSO_CONFIG2_INVALID_BYTE_CNT_MASK) >> TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT;
1392 }
1393 }
1394
HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)1395 MS_U32 HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)
1396 {
1397 //@TODO not implement
1398 //return (_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK);
1399 return 0;
1400 }
1401
HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)1402 MS_U32 HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)
1403 {
1404 //@TODO not implement
1405 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK) >> TSO_HD_ADP_FIELD_SHIFT);
1406 return 0;
1407 }
1408
HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)1409 MS_U32 HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)
1410 {
1411 //@TODO not implement
1412 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PID_MASK) >> TSO_HD_PID_SHIFT);
1413 return 0;
1414 }
1415
HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)1416 MS_U32 HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)
1417 {
1418 //@TODO not implement
1419 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_SCRM_FIELD_MASK) >> TSO_HD_SCRM_FIELD_SHIFT);
1420 return 0;
1421 }
1422
HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)1423 MS_U32 HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)
1424 {
1425 //@TODO not implement
1426 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_TS_PRIORITY_MASK) >> TSO_HD_TS_PRIORITY_SHIFT);
1427 return 0;
1428 }
1429
HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)1430 MS_U32 HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)
1431 {
1432 //@TODO not implement
1433 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_START_IND_MASK) >> TSO_HD_PAYLOAD_START_IND_SHIFT);
1434 return 0;
1435 }
1436
HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)1437 MS_U32 HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)
1438 {
1439 //@TODO not implement
1440 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_ERR_IND_MASK) >> TSO_HD_PAYLOAD_ERR_IND_SHIFT);
1441 return 0;
1442 }
1443
HAL_TSO_Get_Pid_Info(MS_U8 u8Eng,MS_U16 * pu16matchpid,MS_BOOL * pbchanged)1444 void HAL_TSO_Get_Pid_Info(MS_U8 u8Eng, MS_U16 *pu16matchpid, MS_BOOL *pbchanged)
1445 {
1446 //@TODO not implement
1447 /*
1448 MS_U16 u16temp;
1449
1450 u16temp = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_PID_Info));
1451
1452 *pu16matchpid = u16temp & TSO_PID_INFO_MATCH_PID_MASK;
1453 *pbchanged = (((u16temp & TSO_PID_INFO_MATCH_PID_CHANGE_MASK) > 0) ? TRUE: FALSE);
1454 */
1455 }
1456
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1457 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1458 {
1459 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1460 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1461
1462
1463 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1464 _HAL_REG32_W(LPCR2, u32lpcr2);
1465 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1466 }
1467
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1468 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1469 {
1470 MS_U32 u32temp = 0;
1471 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1472 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1473
1474
1475 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1476 u32temp = _HAL_REG32_R(LPCR2);
1477 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1478
1479 return u32temp;
1480 }
1481
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1482 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1483 {
1484 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1);
1485
1486 return _HAL_REG32_R(TIMESTAMP);
1487 }
1488
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1489 void HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1490 {
1491 switch(u8If)
1492 {
1493 case HAL_TSO_TSIF_LIVE1:
1494 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1495 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1496 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1497 break;
1498 case HAL_TSO_TSIF_LIVE2:
1499 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1500 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1501 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1502 break;
1503 case HAL_TSO_TSIF_LIVE3:
1504 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1505 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1506 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1507 break;
1508 case HAL_TSO_TSIF_LIVE4:
1509 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1510 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1511 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1512 break;
1513 case HAL_TSO_TSIF_LIVE5:
1514 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1515 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1516 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1517 break;
1518 case HAL_TSO_TSIF_LIVE6:
1519 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1520 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1521 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1522 break;
1523 default:
1524 printf("Not support !!\n");
1525 break;
1526 }
1527 }
1528
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1529 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1530 {
1531 if(bWrite)
1532 {
1533 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize);
1534 }
1535 else
1536 {
1537 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3));
1538 }
1539
1540 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1541 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1542 }
1543
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1544 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1545 {
1546 switch(u8FileEng)
1547 {
1548 case 0:
1549 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1550 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK)
1551 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN_SHIFT)) & TSO_PKT_CHK_SIZE_FIN_MASK));
1552 break;
1553 case 1:
1554 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1555 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK)
1556 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN1_SHIFT)) & TSO_PKT_CHK_SIZE_FIN1_MASK));
1557 break;
1558 default:
1559 printf("Not support !!\n");
1560 break;
1561 }
1562 }
1563
HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1564 void HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1565 {
1566 switch(u8If)
1567 {
1568 case HAL_TSO_TSIF_LIVE1:
1569 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1570 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1571 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1572 break;
1573 case HAL_TSO_TSIF_LIVE2:
1574 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1575 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1576 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1577 break;
1578 case HAL_TSO_TSIF_LIVE3:
1579 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1580 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1581 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1582 break;
1583 case HAL_TSO_TSIF_LIVE4:
1584 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1585 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1586 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1587 break;
1588 case HAL_TSO_TSIF_LIVE5:
1589 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1590 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1591 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1592 break;
1593 case HAL_TSO_TSIF_LIVE6:
1594 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1595 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1596 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1597 break;
1598 default:
1599 printf("Not support !!\n");
1600 break;
1601 }
1602 }
1603
1604
HAL_TSO_Livein_Input_Config(MS_U8 u8Eng,MS_U8 u8PktInputMode,MS_U8 u8PktSyncByte,MS_U8 u8PktHeaderLength)1605 void HAL_TSO_Livein_Input_Config(MS_U8 u8Eng, MS_U8 u8PktInputMode, MS_U8 u8PktSyncByte, MS_U8 u8PktHeaderLength)
1606 {
1607 switch(u8Eng)
1608 {
1609 case HAL_TSO_TSIF_LIVE1:
1610 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1611 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK)
1612 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK));
1613
1614 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1615 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK)
1616 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK));
1617
1618 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1619 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK)
1620 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK));
1621 break;
1622 case HAL_TSO_TSIF_LIVE2:
1623 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1624 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK)
1625 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK));
1626
1627 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1628 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK)
1629 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK));
1630
1631 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1632 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK)
1633 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK));
1634 break;
1635 case HAL_TSO_TSIF_LIVE3:
1636 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1637 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK)
1638 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK));
1639
1640 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1641 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK)
1642 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK));
1643
1644 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1645 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK)
1646 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK));
1647 break;
1648 case HAL_TSO_TSIF_LIVE4:
1649 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1650 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK)
1651 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK));
1652
1653 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1654 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK)
1655 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK));
1656
1657 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1658 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK)
1659 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK));
1660 break;
1661 case HAL_TSO_TSIF_LIVE5:
1662 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1663 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK)
1664 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK));
1665
1666 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1667 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK)
1668 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK));
1669
1670 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1671 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK)
1672 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK));
1673 break;
1674 case HAL_TSO_TSIF_LIVE6:
1675 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1676 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK)
1677 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK));
1678
1679 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1680 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK)
1681 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK));
1682
1683 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1684 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK)
1685 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK));
1686 break;
1687 default:
1688 printf("Not support !!\n");
1689 break;
1690 }
1691 }
1692
1693
HAL_TSO_Livein_3Wire(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1694 void HAL_TSO_Livein_3Wire(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1695 {
1696 if(bEnable)
1697 {
1698 switch(u8ChIf)
1699 {
1700 case HAL_TSO_TSIF_LIVE1:
1701 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1702 break;
1703 case HAL_TSO_TSIF_LIVE2:
1704 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1705 break;
1706 case HAL_TSO_TSIF_LIVE3:
1707 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1708 break;
1709 case HAL_TSO_TSIF_LIVE4:
1710 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1711 break;
1712 case HAL_TSO_TSIF_LIVE5:
1713 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1714 break;
1715 case HAL_TSO_TSIF_LIVE6:
1716 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1717 break;
1718 default:
1719 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1720 break;
1721 }
1722 }
1723 else
1724 {
1725 switch(u8ChIf)
1726 {
1727 case HAL_TSO_TSIF_LIVE1:
1728 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1729 break;
1730 case HAL_TSO_TSIF_LIVE2:
1731 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1732 break;
1733 case HAL_TSO_TSIF_LIVE3:
1734 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1735 break;
1736 case HAL_TSO_TSIF_LIVE4:
1737 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1738 break;
1739 case HAL_TSO_TSIF_LIVE5:
1740 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1741 break;
1742 case HAL_TSO_TSIF_LIVE6:
1743 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1744 break;
1745 default:
1746 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1747 break;
1748 }
1749
1750 }
1751 }
1752
HAL_TSO_TsioMode_En(MS_BOOL bEnable)1753 void HAL_TSO_TsioMode_En(MS_BOOL bEnable)
1754 {
1755 //dummy function for make
1756 return;
1757 }
1758
HAL_TSO_SerialMode_En(MS_BOOL bEnable)1759 void HAL_TSO_SerialMode_En(MS_BOOL bEnable)
1760 {
1761 if(bEnable)
1762 {
1763 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1764 }
1765 else
1766 {
1767 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1768 }
1769 }
1770
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1771 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1772 {
1773 REG32_TSO *Base = NULL;
1774 REG16_TSO *Size = NULL, *TX_Config = NULL;
1775
1776
1777 switch(u8ChIf)
1778 {
1779 case HAL_TSO_TSIF_LIVE1:
1780 Base = &(_TSOCtrl1->SVQ1_BASE);
1781 Size = &(_TSOCtrl1->SVQ1_SIZE_200BYTE);
1782 TX_Config = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1783 break;
1784 case HAL_TSO_TSIF_LIVE2:
1785 Base = &(_TSOCtrl1->SVQ2_BASE);
1786 Size = &(_TSOCtrl1->SVQ2_SIZE_200BYTE);
1787 TX_Config = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1788 break;
1789 case HAL_TSO_TSIF_LIVE3:
1790 Base = &(_TSOCtrl1->SVQ3_BASE);
1791 Size = &(_TSOCtrl1->SVQ3_SIZE_200BYTE);
1792 TX_Config = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1793 break;
1794 case HAL_TSO_TSIF_LIVE4:
1795 Base = &(_TSOCtrl1->SVQ4_BASE);
1796 Size = &(_TSOCtrl1->SVQ4_SIZE_200BYTE);
1797 TX_Config = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1798 break;
1799 case HAL_TSO_TSIF_LIVE5:
1800 Base = &(_TSOCtrl1->SVQ5_BASE);
1801 Size = &(_TSOCtrl1->SVQ5_SIZE_200BYTE);
1802 TX_Config = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1803 break;
1804 case HAL_TSO_TSIF_LIVE6:
1805 Base = &(_TSOCtrl1->SVQ6_BASE);
1806 Size = &(_TSOCtrl1->SVQ6_SIZE_200BYTE);
1807 TX_Config = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1808 break;
1809 default:
1810 printf("Not support !!\n");
1811 return FALSE;
1812 }
1813
1814 _HAL_REG32_W(Base, ((phyBufAddr >> TSO_MIU_BUS) & TSO1_SVQ1_BASE_MASK));
1815 _HAL_REG16_W(Size, ((u32BufSize / TSO_SVQ_UNIT_SIZE) & TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK));
1816 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1817 _REG16_CLR(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1818 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);
1819
1820 return TRUE;
1821 }
1822
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1823 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1824 {
1825 REG16_TSO* p16Reg = NULL;
1826
1827 if(u8Eng > 0)
1828 {
1829 return FALSE;
1830 }
1831
1832 switch(u8ChIf)
1833 {
1834 case HAL_TSO_TSIF_LIVE1:
1835 p16Reg = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1836 break;
1837 case HAL_TSO_TSIF_LIVE2:
1838 p16Reg = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1839 break;
1840 case HAL_TSO_TSIF_LIVE3:
1841 p16Reg = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1842 break;
1843 case HAL_TSO_TSIF_LIVE4:
1844 p16Reg = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1845 break;
1846 case HAL_TSO_TSIF_LIVE5:
1847 p16Reg = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1848 break;
1849 case HAL_TSO_TSIF_LIVE6:
1850 p16Reg = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1851 break;
1852 default:
1853 printf("Not support !!\n");
1854 return FALSE;
1855 }
1856
1857 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1858 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1859 return TRUE;
1860 }
1861
HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem,MS_BOOL benable)1862 void HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem, MS_BOOL benable)
1863 {
1864 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG));
1865
1866 if(benable)
1867 {
1868 u16data |= u16CfgItem;
1869 }
1870 else
1871 {
1872 u16data &= ~u16CfgItem;
1873 }
1874
1875 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), u16data);
1876 }
1877
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1878 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1879 {
1880 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), (_HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG)) & ~TSO1_SVQ_RX_CONFIG_MODE_MASK) | u16mode);
1881
1882 return TRUE;
1883 }
1884
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1885 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1886 {
1887 MS_U32 u32data = 0;
1888 MS_U32 u32Shift = 0;
1889
1890 *pu16Status = 0;
1891 u32data = _HAL_REG32_R(&(_TSOCtrl1->SVQ_STATUS));
1892
1893 switch(u8ChIf)
1894 {
1895 case HAL_TSO_TSIF_LIVE1:
1896 u32Shift = TSO_SVQ1_STS_SHIFT;
1897 break;
1898 case HAL_TSO_TSIF_LIVE2:
1899 u32Shift = TSO_SVQ2_STS_SHIFT;
1900 break;
1901 case HAL_TSO_TSIF_LIVE3:
1902 u32Shift = TSO_SVQ3_STS_SHIFT;
1903 break;
1904 case HAL_TSO_TSIF_LIVE4:
1905 u32Shift = TSO_SVQ4_STS_SHIFT;
1906 break;
1907 case HAL_TSO_TSIF_LIVE5:
1908 u32Shift = TSO_SVQ5_STS_SHIFT;
1909 break;
1910 case HAL_TSO_TSIF_LIVE6:
1911 u32Shift = TSO_SVQ6_STS_SHIFT;
1912 break;
1913 default:
1914 return FALSE;
1915 }
1916
1917 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1918
1919 return TRUE;
1920 }
1921
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1922 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1923 {
1924 //@TODO not implement
1925 return TRUE;
1926 }
1927
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1928 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1929 {
1930 //@TODO not implement
1931 return TRUE;
1932 }
1933
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1934 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1935 {
1936 REG16_TSO* p16Reg = NULL;
1937
1938 switch(u8ChIf)
1939 {
1940 case HAL_TSO_TSIF_LIVE1:
1941 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_1_CONFIG_0);
1942 break;
1943 case HAL_TSO_TSIF_LIVE2:
1944 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_2_CONFIG_0);
1945 break;
1946 case HAL_TSO_TSIF_LIVE3:
1947 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_3_CONFIG_0);
1948 break;
1949 case HAL_TSO_TSIF_LIVE4:
1950 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_4_CONFIG_0);
1951 break;
1952 case HAL_TSO_TSIF_LIVE5:
1953 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_5_CONFIG_0);
1954 break;
1955 case HAL_TSO_TSIF_LIVE6:
1956 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_6_CONFIG_0);
1957 break;
1958 default:
1959 return FALSE;
1960 }
1961
1962 if(beSet == TRUE)
1963 {
1964 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
1965 }
1966 else
1967 {
1968 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
1969 }
1970
1971 return TRUE;
1972
1973 }
1974
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)1975 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
1976 {
1977 MS_U16 u16Temp = 0;
1978
1979 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
1980 u16Temp = (u16Temp & TSO_PIDFLT_PID_MASK) | ((u16InputSrc & TSO_PIDFLT_IN_MASK) << TSO_PIDFLT_IN_SHIFT);
1981 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
1982 }
1983
HAL_TSO_Flt_SetSid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8Sid)1984 void HAL_TSO_Flt_SetSid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8Sid)
1985 {
1986 //dummy function for make
1987 return;
1988 }
1989
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)1990 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
1991 {
1992 //@TODO not implement
1993 return TRUE;
1994 }
1995
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)1996 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
1997 {
1998 //@TODO not implement
1999 return TRUE;
2000 }
2001
HAL_TSO_SaveRegs(void)2002 void HAL_TSO_SaveRegs(void)
2003 {
2004 //@TODO not implement
2005 }
2006
HAL_TSO_RestoreRegs(void)2007 void HAL_TSO_RestoreRegs(void)
2008 {
2009 //@TODO not implement
2010 }
2011
2012 #ifdef CONFIG_MSTAR_CLKM
HAL_TSO_PowerCtrl(MS_BOOL bOn)2013 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2014 {
2015 MS_S32 s32ClkHandle;
2016
2017 if (bOn)
2018 {
2019 // Enable TSO out Clock
2020 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2021 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOOUT_DIV");
2022
2023 // Enable TSO in Clock
2024 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2025 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOIN0_PAD0");
2026
2027 // Enable TSO1 in Clock
2028 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2029 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN1_PAD0");
2030
2031 // Enable TSO2 in Clock
2032 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2033 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN2_PAD0");
2034
2035 // Enable TSO3 in Clock
2036 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2037 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN3_PAD0");
2038
2039 // Enable TSO4 in Clock
2040 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2041 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN4_PAD0");
2042
2043 // Enable TSO5 in Clock
2044 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2045 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN5_PAD0");
2046
2047 // Disable MCM
2048 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2049 }
2050 else
2051 {
2052 // Enable MCM
2053 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2054
2055 // Disabel TSO out Clock
2056 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2057 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2058
2059 // Disabel TSO in Clock
2060 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2061 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2062
2063 // Disabel TSO1 in Clock
2064 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2065 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2066
2067 // Disabel TSO2 in Clock
2068 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2069 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2070
2071 // Disabel TSO3 in Clock
2072 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2073 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2074
2075 // Disabel TSO4 in Clock
2076 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2077 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2078
2079 // Disabel TSO5 in Clock
2080 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2081 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2082 }
2083 }
2084 #else
HAL_TSO_PowerCtrl(MS_BOOL bOn)2085 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2086 {
2087 if (bOn)
2088 {
2089 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
2090 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2091 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2092 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2093 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2094 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2095 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2096
2097 // Disable MCM
2098 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2099 }
2100 else
2101 {
2102 // Enable MCM
2103 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2104
2105 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
2106 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2107 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2108 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2109 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2110 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2111 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2112 }
2113 }
2114 #endif
2115