Lines Matching refs:_TSOCtrl
44 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
227 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
247 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
253 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
254 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
256 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
257 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
271 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
272 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
277 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
292 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Clear()
299 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Status()
426 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
430 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
434 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
438 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
442 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
446 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
908 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
935 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
954 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW_withSid()
955 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW_withSid()
958 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW_withSid()
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F)); in _HAL_TSO_PageTableIndW_withSid()
962 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW_withSid()
968 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW()
969 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW()
972 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW()
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000); in _HAL_TSO_PageTableIndW()
976 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW()
982 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndR()
983 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndR()
986 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN); in _HAL_TSO_PageTableIndR()
989 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA)); in _HAL_TSO_PageTableIndR()
1011 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]); in HAL_TSO_Set_Filein_ReadAddr()
1016 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]); in HAL_TSO_Set_Filein_ReadAddr()
1025 …REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_6… in HAL_TSO_Set_Filein_ReadLen()
1033 …REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1); in HAL_TSO_Get_Filein_ReadAddr()
1034 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Get_Filein_ReadAddr()
1046 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Set_Filein_Ctrl()
1053 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Get_Filein_Ctrl()
1070 … REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_FileinTimer_Enable()
1084 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer); in HAL_TSO_Filein_Rate()
1089 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192Mode_Enable()
1103 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192BlockMode_Enable()
1120 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRCnt()
1142 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRLevel()
1149 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1150 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1176 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)); in HAL_TSO_Cfg1_Enable()
1187 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1188 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1196 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1197 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1200 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1201 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1204 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1205 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1208 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1209 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1212 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1213 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1216 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1217 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1263 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1266 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_ChIf_Cfg()
1269 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1272 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1275 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1278 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1310 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1313 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1319 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1322 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1325 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1357 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data); in HAL_TSO_Get_ChIf_Cfg()
1364 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_File_Cfg1_Enable()
1402 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_ValidBlock_Count()
1408 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_ValidBlock_Count()
1410 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1411 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1421 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_InvalidBlock_Count()
1427 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_InvalidBlock_Count()
1429 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1430 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1502 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Set()
1503 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Set()
1514 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Get()
1515 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Get()
1527 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1); in HAL_TSO_TimeStamp_Get()
1537 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_PktChkSize_Set()
1538 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1542 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_PktChkSize_Set()
1543 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1547 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_PktChkSize_Set()
1548 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1552 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_PktChkSize_Set()
1553 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1557 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_PktChkSize_Set()
1558 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1562 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_PktChkSize_Set()
1563 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1576 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize); in HAL_TSO_RW_OutputPktSize()
1580 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3)); in HAL_TSO_RW_OutputPktSize()
1583 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PK… in HAL_TSO_RW_OutputPktSize()
1584 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_… in HAL_TSO_RW_OutputPktSize()
1592 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1593 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1597 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1598 … (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1612 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1613 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1617 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1618 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1622 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1623 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1627 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1628 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1632 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1633 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1637 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1638 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1653 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1654 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1657 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1658 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1661 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1662 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1666 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1667 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1670 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1671 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1674 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1675 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1679 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1680 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1683 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1684 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1687 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1688 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1692 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1693 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1696 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1697 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1700 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1701 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1705 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1706 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1709 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1710 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1713 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1714 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1718 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1719 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1722 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1723 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1726 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1727 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1753 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1756 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1759 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1780 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1783 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1786 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1800 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1804 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1812 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1816 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1824 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
1828 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
2111 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2116 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2161 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2166 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2311 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()
2315 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()