1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halTSO.c
20 // @brief TS I/O HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "regTSO.h"
25 #include "halTSO.h"
26 #include "halCHIP.h"
27 #include "drvSYS.h"
28
29 #ifdef CONFIG_MSTAR_CLKM
30 #include "drvCLKM.h"
31 #endif
32
33 //--------------------------------------------------------------------------------------------------
34 // Driver Compiler Option
35 //--------------------------------------------------------------------------------------------------
36 #define TSP_HAL_REG_SAFE_MODE 1 // Register protection access between 1 task and 1+ ISR
37
38 #define MIU_BUS 4
39
40
41 //--------------------------------------------------------------------------------------------------
42 // TSP Hardware Abstraction Layer
43 //--------------------------------------------------------------------------------------------------
44 static REG_Ctrl_TSO* _TSOCtrl = NULL;
45 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
46 static REG_Ctrl_TSO2* _TSOCtrl2 = NULL;
47 static REG_Ctrl_TSO4* _TSOCtrl4 = NULL;
48
49 static MS_VIRT _u32TSORegBase = 0;
50
51 //-------------------------------------------------------------------------------------------------
52 // Debug Message
53 //-------------------------------------------------------------------------------------------------
54 typedef enum
55 {
56 E_HAL_TSO_DBG_LEVEL_NONE, // no debug message shown
57 E_HAL_TSO_DBG_LEVEL_ERR, // only shows error message that can't be recover
58 E_HAL_TSO_DBG_LEVEL_WARN, // error case can be recover, like retry
59 E_HAL_TSO_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
60 E_HAL_TSO_DBG_LEVEL_INFO, // information for internal parameter
61 E_HAL_TSO_DBG_LEVEL_FUNC, // Function trace and input parameter trace
62 E_HAL_TSO_DBG_LEVEL_TRACE, // debug trace
63 } EN_HAL_TSO_DBGMSG_LEVEL;
64
65 typedef enum
66 {
67 E_HAL_TSO_DBG_MODEL_NONE, // @temporarily , need to refine
68 E_HAL_TSO_DBG_MODEL_ALL,
69 } EN_HAL_TSO_DBGMSG_MODEL;
70
71 #define HAL_TSO_DBGMSG(_level,_model,_f) do {if(_u32TSODbgLevel >= (_level)&&((_u32TSODbgModel&_model)!=0)) (_f);} while(0)
72 static MS_U32 _u32TSODbgLevel = E_HAL_TSO_DBG_LEVEL_ERR;
73 static MS_U32 _u32TSODbgModel = E_HAL_TSO_DBG_MODEL_ALL;
74
75
76 //[NOTE] Jerry
77 // Some register has write order, for example, writing PCR_L will disable PCR counter
78 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
79 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
80 (reg)->H = ((value) >> 16); } while(0)
81
82 #define _HAL_REG16_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
83
84 //--------------------------------------------------------------------------------------------------
85 // Macro of bit operations
86 //--------------------------------------------------------------------------------------------------
87 #define HAS_FLAG(flag, bit) ((flag) & (bit))
88 #define SET_FLAG(flag, bit) ((flag) |= (bit))
89 #define RESET_FLAG(flag, bit) ((flag) &= (~(bit)))
90 #define SET_FLAG1(flag, bit) ((flag) | (bit))
91 #define RESET_FLAG1(flag, bit) ((flag) & (~(bit)))
92
93
94 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));
95 #define _REG32_SET(reg, value); _HAL_REG32_W(reg, SET_FLAG1(_HAL_REG32_R(reg), value));
96 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
97 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
98
99
100
101
102 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
103 #define REG_CLKGEN0_TSO_IN 0x27
104 #define REG_CLKGEN0_TSO_IN_MASK 0x001F
105 #define REG_CLKGEN0_TSO_IN_SHIFT 2
106 #define REG_CLKGEN0_TSO_IN_DISABLE 0x0001
107 #define REG_CLKGEN0_TSO_IN_INVERT 0x0002
108 // bit[4:0] -> 0: disable clock
109 // 1: invert clock
110 // bit [3:2] -> 000: select TS0_CLK
111 // 001: select TS1_CLK
112 // 010: from demod 0
113 #define REG_CLKGEN0_TSO_TRACE_MASK 0x0F00
114 #define REG_CLKGEN0_TSO_TRACE_DISABLE 0x0100
115 #define REG_CLKGEN0_TSO_TRACE_INVERT 0x0200
116 #define REG_CLKGEN0_TSO_TRACE_216M 0x0000
117
118 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D
119 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK 0x001F
120 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT 0
121 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_EN_MASK 0x0020
122 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE 0x0020
123 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040
124 #define HAL_TSO_OUT_DIV_SEL_172M_2N 0x0000
125 #define HAL_TSO_OUT_DIV_SEL_288M_2N 0x0040
126
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM 0x2E
128 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0
129 #define REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT 6
130 #define REG_CLKGEN_TSO_P_TSO_OUT_MASK 0xF800
131 #define REG_CLKGEN_TSO_P_TSO_OUT_SHIFT 13
132
133 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F
134 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x001F
135 #define REG_CLKGEN0_TSO_OUT_CLK_DISABLE 0x0001
136 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002
137 #define REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT 2
138 // bit[4:0] -> 0: disable clock
139 // 1: invert clock
140 // bit [4:2] -> 000: from demod 0, clk_dvbtc_ts_p
141 // 001: 62MHz
142 // 010: 54MHz
143 // 011: clk_p_tso_out (live in)
144 // 100: clk_p_tso_out_div8 (live in)
145 // 101: tso_out_div (clock/(N+1))
146 // 110: 86MHz
147
148 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))))
149 #define REG_CLKGEN1_DEMOD0_OUT_CLK 0x00
150 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_MASK 0x001F //demod0 div num of output clk
151 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_SHIFT 0
152 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_MASK 0x0100 //demod0 div src of output clk
153 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_SHIFT 8
154 // bit[8] -> 0: CLK_DMPLLDIV2
155 // 1: CLK_DMPLLDIV3
156
157 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
158 #define REG_CLKGEN2_TSO1_IN 0x06
159 #define REG_CLKGEN2_TSO2_IN 0x07
160 #define REG_CLKGEN2_TSO3_IN 0x08
161 #define REG_CLKGEN2_TSO4_IN 0x09
162 #define REG_CLKGEN2_TSO5_IN 0x0a
163
164 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
165 #define REG_TOP_TSO_MUX 0x3A
166 #define REG_TOP_TSO_MUX_MASK 0x0007
167 #define REG_TOP_TSO1_MUX_SHIFT 0
168 #define REG_TOP_TSO2_MUX_SHIFT 4
169 #define REG_TOP_TSO3_MUX_SHIFT 8
170 #define REG_TOP_TSO4_MUX_SHIFT 12
171
172 #define REG_TOP_TSO1_MUX 0x3B
173 #define REG_TOP_TSO5_MUX_SHIFT 0
174 #define REG_TOP_TSO6_MUX_SHIFT 4
175 // bit[2:0] -> 000: PAD_TS0
176 // 001: PAD_TS1
177 // 0111: DEMOD
178
179 #if 0 // Not used
180 #define REG_TOP_MIU_GP1_i64 0x21
181 #define REG_TOP_MIU_GP1_i64_TSO_MASK 0x0080
182 #define REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT 0x0000
183 #define REG_TOP_MIU_GP1_i64_TSO_64BIT_CLIENT 0x0080
184 #define REG_TOP_TS_CONFIG 0x57
185 #define REG_TOP_TS0_CONFIG_MASK 0x0700
186 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0100
187 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0200
188 #define REG_TOP_TS1_CONFIG_MASK 0x3800
189 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800
190 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000
191 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800
192 #define REG_TOP_TS2_CONFIG_MASK 0x4000
193 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x4000
194 #define REG_TOP_TSCB_CONFIG_MASK 0x8000
195 #define REG_TOP_TSCB_CONFIG_SERIAL_IN 0x8000
196 #define REG_TOP_TS_OUT_MODE 0x6E
197 #define REG_TOP_TS_OUT_MODE_MASK 0x0300
198 #define REG_TOP_TS_OUT_MODE_TSO 0x0200
199 #endif
200
201 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
202 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
203 #define REG_MIUDIG_MIU_SEL1 0x79
204 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080
205
206 //--------------------------------------------------------------------------------------------------
207 // Implementation
208 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_TSO * reg)209 static MS_U32 _HAL_REG32_R(REG32_TSO *reg)
210 {
211 MS_U32 value = 0;
212 value = (reg)->L;
213 value |= (reg)->H << 16;
214 return value;
215 }
216
_HAL_REG16_R(REG16_TSO * reg)217 static MS_U16 _HAL_REG16_R(REG16_TSO *reg)
218 {
219 MS_U16 value = 0;
220 value = (reg)->data;
221 return value;
222 }
223
HAL_TSO_SetBank(MS_VIRT u32BankAddr)224 void HAL_TSO_SetBank(MS_VIRT u32BankAddr)
225 {
226 _u32TSORegBase = u32BankAddr;
227 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706
228 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612
229 _TSOCtrl2 = (REG_Ctrl_TSO2*)(_u32TSORegBase+ REG_CTRL_BASE_TSO2); // 0x1539
230 //_TSOCtrl3 = (REG_Ctrl_TSO3*)(_u32TSORegBase+ REG_CTRL_BASE_TSO3); // 0x171D
231 _TSOCtrl4 = (REG_Ctrl_TSO4*)(_u32TSORegBase+ REG_CTRL_BASE_TSO4); // 0x1215
232 }
233
234 //
235 // General API
236 //
HAL_TSO_Init(void)237 void HAL_TSO_Init(void)
238 {
239 //select MIU0, and 128bit MIU bus
240 /*
241 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
242 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
243 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
244 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
245 */
246
247 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);
248
249 }
250
HAL_TSO_Reset_All(MS_U8 u8Eng)251 void HAL_TSO_Reset_All(MS_U8 u8Eng)
252 {
253 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active
254 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);
255
256 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
257 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
258 }
259
HAL_TSO_Reset(MS_U8 u8Eng)260 void HAL_TSO_Reset(MS_U8 u8Eng)
261 {
262 //@TODO not find in register table
263 /*
264 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
265 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
266 */
267 }
268
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)269 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
270 {
271 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem));
272 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem));
273 }
274
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL bEnable,MS_U16 u16init)275 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL bEnable, MS_U16 u16init)
276 {
277 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
278 MS_U16 u16data = _HAL_REG16_R(reg);
279
280 if(bEnable)
281 {
282 _HAL_REG16_W(reg, (u16data | u16init));
283 }
284 else
285 {
286 _HAL_REG16_W(reg, (u16data & ~u16init));
287 }
288 }
289
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)290 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
291 {
292 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
293
294 _HAL_REG16_W(reg, (_HAL_REG16_R(reg) & ~u16Int));
295 }
296
HAL_TSO_HWInt_Status(MS_U8 u8Eng)297 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
298 {
299 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
300
301 return (_HAL_REG16_R(reg) & TSO_INT_STS_MASK);
302 }
303
HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId,MS_U16 * u16Pad,MS_U16 * u16Clk)304 MS_BOOL HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId, MS_U16 *u16Pad, MS_U16 *u16Clk)
305 {
306 switch(u8Pad3WireId)
307 {
308 case 3:
309 *u16Pad = HAL_TSOIN_MUX_TS3;
310 *u16Clk = TSO_CLKIN_TS3;
311 break;
312 case 4:
313 *u16Pad = HAL_TSOIN_MUX_TS4;
314 *u16Clk = TSO_CLKIN_TS4;
315 break;
316 case 5:
317 *u16Pad = HAL_TSOIN_MUX_TS5;
318 *u16Clk = TSO_CLKIN_TS5;
319 break;
320 case 6:
321 *u16Pad = HAL_TSOIN_MUX_TS6;
322 *u16Clk = TSO_CLKIN_TS6;
323 break;
324 default:
325 printf("[%s][%d]: Not support !!\n", __FUNCTION__, __LINE__);
326 return FALSE;
327 }
328
329 return TRUE;
330 }
331
332
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)333 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
334 {
335 MS_U16 u16Reg, u16RegShift;
336
337 switch(u8TsIf)
338 {
339 case HAL_TSO_TSIF_LIVE1:
340 u16Reg = REG_TOP_TSO_MUX;
341 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
342 break;
343 case HAL_TSO_TSIF_LIVE2:
344 u16Reg = REG_TOP_TSO_MUX;
345 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
346 break;
347 case HAL_TSO_TSIF_LIVE3:
348 u16Reg = REG_TOP_TSO_MUX;
349 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
350 break;
351 case HAL_TSO_TSIF_LIVE4:
352 u16Reg = REG_TOP_TSO_MUX;
353 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
354 break;
355 case HAL_TSO_TSIF_LIVE5:
356 u16Reg = REG_TOP_TSO1_MUX;
357 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
358 break;
359 case HAL_TSO_TSIF_LIVE6:
360 u16Reg = REG_TOP_TSO1_MUX;
361 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
362 break;
363 default:
364 printf("Not support !!\n");
365 return FALSE;
366 }
367
368 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~(REG_TOP_TSO_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
369
370 //@NOTE: no need to change input pad mode dynamically (Mboot handle it...)
371
372 return TRUE;
373 }
374
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)375 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
376 {
377 //@TODO not implement
378 return TRUE;
379 }
380
381
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)382 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
383 {
384 MS_U16 u16Reg, u16RegShift;
385 MS_U16 u16data = 0;
386 REG16_TSO* reg16 = 0;
387
388 // Set pad mux
389 switch(u8TsIf)
390 {
391 case HAL_TSO_TSIF_LIVE1:
392 u16Reg = REG_TOP_TSO_MUX;
393 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
394 break;
395 case HAL_TSO_TSIF_LIVE2:
396 u16Reg = REG_TOP_TSO_MUX;
397 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
398 break;
399 case HAL_TSO_TSIF_LIVE3:
400 u16Reg = REG_TOP_TSO_MUX;
401 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
402 break;
403 case HAL_TSO_TSIF_LIVE4:
404 u16Reg = REG_TOP_TSO_MUX;
405 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
406 break;
407 case HAL_TSO_TSIF_LIVE5:
408 u16Reg = REG_TOP_TSO1_MUX;
409 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
410 break;
411 case HAL_TSO_TSIF_LIVE6:
412 u16Reg = REG_TOP_TSO1_MUX;
413 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
414 break;
415 default:
416 printf("Not support !!\n");
417 return FALSE;
418 }
419
420 *pu16Pad = (TSP_TOP_REG(u16Reg) >> u16RegShift) & REG_TOP_TSO_MUX_MASK;
421
422 switch(u8TsIf)
423 {
424 case HAL_TSO_TSIF_LIVE1:
425 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK;
426 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
427 break;
428 case HAL_TSO_TSIF_LIVE2:
429 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;
430 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
431 break;
432 case HAL_TSO_TSIF_LIVE3:
433 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;
434 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
435 break;
436 case HAL_TSO_TSIF_LIVE4:
437 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;
438 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
439 break;
440 case HAL_TSO_TSIF_LIVE5:
441 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;
442 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
443 break;
444 case HAL_TSO_TSIF_LIVE6:
445 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;
446 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
447 break;
448 default:
449 printf("Not support !!\n");
450 return FALSE;
451 }
452
453 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
454 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
455 *pbClkInvert = ((u16data & REG_CLKGEN0_TSO_IN_INVERT) == REG_CLKGEN0_TSO_IN_INVERT);
456
457 return TRUE;
458 }
459
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)460 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
461 {
462 MS_BOOL isCLKGEN0 = FALSE;
463 MS_U16 u16Reg;
464 MS_U16 u16value = 0;
465
466 switch(u8TsIf)
467 {
468 case HAL_TSO_TSIF_LIVE1:
469 isCLKGEN0 = TRUE;
470 u16Reg = REG_CLKGEN0_TSO_IN;
471 break;
472 case HAL_TSO_TSIF_LIVE2:
473 u16Reg = REG_CLKGEN2_TSO1_IN;
474 break;
475 case HAL_TSO_TSIF_LIVE3:
476 u16Reg = REG_CLKGEN2_TSO2_IN;
477 break;
478 case HAL_TSO_TSIF_LIVE4:
479 u16Reg = REG_CLKGEN2_TSO3_IN;
480 break;
481 case HAL_TSO_TSIF_LIVE5:
482 u16Reg = REG_CLKGEN2_TSO4_IN;
483 break;
484 case HAL_TSO_TSIF_LIVE6:
485 u16Reg = REG_CLKGEN2_TSO5_IN;
486 break;
487 default:
488 printf("Not support !!\n");
489 return FALSE;
490 }
491
492 if(u16ClkSel == 0xFFFF)
493 {
494 return FALSE;
495 }
496
497 if(isCLKGEN0)
498 {
499 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
500 }
501 else
502 {
503 u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
504 }
505
506 if(!bEnable)
507 {
508 u16value |= REG_CLKGEN0_TSO_IN_DISABLE;
509 }
510 else
511 {
512 #ifndef CONFIG_MSTAR_CLKM
513 u16value |= (u16ClkSel << REG_CLKGEN0_TSO_IN_SHIFT);
514 #endif
515
516 if(bClkInvert)
517 {
518 u16value |= REG_CLKGEN0_TSO_IN_INVERT;
519 }
520 }
521
522 if(isCLKGEN0)
523 {
524 TSO_CLKGEN0_REG(u16Reg) = u16value;
525 }
526 else
527 {
528 TSO_CLKGEN2_REG(u16Reg) = u16value;
529 }
530
531 #ifdef CONFIG_MSTAR_CLKM
532
533 MS_S32 s32Handle;
534 char u8ClkSrcName[20] = "";
535 MS_U8 u8Idx = u8TsIf - 1;
536
537 switch(u16ClkSel)
538 {
539 case TSO_CLKIN_TS0:
540 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD0", u8Idx);
541 break;
542 case TSO_CLKIN_TS1:
543 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD1", u8Idx);
544 break;
545 case TSO_CLKIN_TS2:
546 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD2", u8Idx);
547 break;
548 case TSO_CLKIN_TS3:
549 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD3", u8Idx);
550 break;
551 case TSO_CLKIN_TS4:
552 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD4", u8Idx);
553 break;
554 case TSO_CLKIN_TS5:
555 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD5", u8Idx);
556 break;
557 default:
558 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
559 return FALSE;
560 }
561
562 switch(u8TsIf)
563 {
564 case HAL_TSO_TSIF_LIVE1:
565 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
566 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
567 break;
568 case HAL_TSO_TSIF_LIVE2:
569 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
570 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
571 break;
572 case HAL_TSO_TSIF_LIVE3:
573 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
574 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
575 break;
576 case HAL_TSO_TSIF_LIVE4:
577 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
578 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
579 break;
580 case HAL_TSO_TSIF_LIVE5:
581 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
582 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
583 break;
584 case HAL_TSO_TSIF_LIVE6:
585 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
586 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
587 break;
588 default:
589 printf("Not support !!\n");
590 return FALSE;
591 }
592
593 #endif
594
595 return TRUE;
596 }
597
598 #if 0
599 #define NPM_REG_ANAMISC 0x10C00 //0x110c00 //ana misc
600 #define NPM_REG_MIPS_PLLCLK (NPM_REG_ANAMISC+0x0002)
601 static MS_U32 _HAL_TSO_CPU_QueryClock(void)
602 {
603 MS_U32 u32Count = 0;
604 MS_U32 u32Speed = 0;
605 //here we assum that _u32TSORegBase is the same as non-PM bank
606 u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];
607 u32Count = ((u32Speed & 0xFF00) >> 8) * 12000000;
608
609 return u32Count;
610 }
611
612 static void _HAL_TSO_Delay(MS_U32 u32Us)
613 {
614 MS_U32 u32CPUClk = _HAL_TSO_CPU_QueryClock();
615 register MS_U32 u32Loop = (((u32CPUClk/1000000)/3)*(u32Us));// 3 cycles / loop
616 while(u32Loop--);
617 }
618 #endif
619
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)620 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
621 {
622 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
623 {
624 return FALSE; //not support yet
625 }
626
627 switch(u16PadSel)
628 {
629 case HAL_TSOIN_MUX_TS0:
630 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
631 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
632 break;
633 case HAL_TSOIN_MUX_TS1:
634 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
635 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
636 break;
637 case HAL_TSOIN_MUX_TS2:
638 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
639 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
640 break;
641 case HAL_TSOIN_MUX_TS3:
642 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
643 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS3IN;
644 break;
645 case HAL_TSOIN_MUX_TS4:
646 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
647 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS4IN;
648 break;
649 case HAL_TSOIN_MUX_TS5:
650 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
651 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS5IN;
652 break;
653 /*
654 case HAL_TSOIN_MUX_TSDEMOD0:
655 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
656 break;
657 */
658 case HAL_TSOIN_MUX_MEM:
659 case HAL_TSOIN_MUX_MEM1:
660 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV;
661 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
662 pstOutClkSet->u16OutDivNum = 0x1F; //default: 172.8/(31+1) = 5.4M
663 break;
664 default:
665 return FALSE;
666 }
667
668 return TRUE;
669 }
670
671
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)672 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16 *pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
673 {
674 //clock source for clock divide
675 if(bSet == TRUE)
676 {
677 /*
678 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
679 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
680 */
681
682 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
683 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
684
685 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
686 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum << REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT);
687 }
688 else
689 {
690 *pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
691 *pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT;
692 }
693
694 return TRUE;
695 }
696
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)697 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
698 {
699 if(bSet == TRUE)
700 {
701 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS6IN)
702 {
703 return FALSE;
704 }
705
706 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
707 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | ((*pu16PreTsoOutSel) << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
708 }
709 else
710 {
711 *pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN_TSO_P_TSO_OUT_MASK) >> REG_CLKGEN_TSO_P_TSO_OUT_SHIFT;
712 }
713
714 return TRUE;
715 }
716
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)717 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
718 {
719 if(bSet == TRUE)
720 {
721 if(pstOutClkSet->bEnable == FALSE)
722 {
723 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
724 return;
725 }
726
727 switch(pstOutClkSet->u16OutClk)
728 {
729 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
730 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
731 break;
732 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
733 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
734 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
735 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
736 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
737 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
738 break;
739 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
740 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
741 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
742 break;
743 default:
744 return;
745 }
746
747 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
748 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //always need TSO out clock
749 }
750 else
751 {
752 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
753 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV)
754 {
755 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
756 }
757 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
758 {
759 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
760 }
761 }
762 }
763
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)764 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
765 {
766 MS_U16 u16value = 0;
767 if(u8Eng == 0)
768 {
769 if(!bPhaseEnable)
770 {
771 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
772 }
773 else
774 {
775 u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)
776 | (u16ClkOutPhase << REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT);
777
778 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;
779 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
780 }
781 }
782 else
783 {
784 return FALSE;
785 }
786
787 return TRUE;
788 }
789
HAL_TSO_Set_PreTsoOutClk(MS_U8 u8Eng,MS_U16 u16PreTsoOutSel)790 MS_BOOL HAL_TSO_Set_PreTsoOutClk(MS_U8 u8Eng, MS_U16 u16PreTsoOutSel)
791 {
792 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
793 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | (u16PreTsoOutSel << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
794
795 return TRUE;
796 }
797
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)798 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
799 {
800 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
801
802 if(bSet == TRUE)
803 {
804 if(*pbEnable == FALSE)
805 {
806 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
807 }
808 else
809 {
810 /*
811 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
812 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
813 */
814 #ifndef CONFIG_MSTAR_CLKM
815 u16Clk |= (*pu16ClkOutSel << REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT);
816 #endif
817
818 if(*pbClkInvert)
819 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT;
820 }
821
822 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;
823
824 #ifdef CONFIG_MSTAR_CLKM
825
826 MS_S32 s32Handle;
827 MS_U8 u8NameIdx = 0;
828 char* u8ClkSrcNames[] =
829 {
830 "CLK_TSOOUT_27M",
831 "CLK_TSOOUT_62M",
832 "CLK_TSOOUT_108M",
833 "CLK_TSOOUT_FROMPAD",
834 "CLK_TSOOUT_DIV8",
835 "CLK_TSOOUT_DIV",
836 "CLK_TSOOUT_86M",
837 "CLK_TSOOUT_123M"
838 };
839
840 switch(*pu16ClkOutSel)
841 {
842 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
843 u8NameIdx = 0;
844 break;
845 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
846 u8NameIdx = 1;
847 break;
848 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
849 u8NameIdx = 2;
850 break;
851 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
852 u8NameIdx = 3;
853 break;
854 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
855 u8NameIdx = 4;
856 break;
857 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
858 u8NameIdx = 5;
859 break;
860 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
861 u8NameIdx = 6;
862 break;
863 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
864 u8NameIdx = 7;
865 break;
866 default:
867 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
868 return FALSE;
869 }
870
871 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_out");
872 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
873
874 #endif
875 }
876 else
877 {
878 *pbEnable = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_DISABLE) == 0);
879 *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT);
880 *pu16ClkOutSel = u16Clk >> REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT;
881 }
882
883 return TRUE;
884 }
885
HAL_TSO_Set_PidBypass(MS_U8 u8Eng,MS_BOOL bEnable)886 MS_BOOL HAL_TSO_Set_PidBypass(MS_U8 u8Eng, MS_BOOL bEnable)
887 {
888 if(bEnable)
889 {
890 switch(u8Eng)
891 {
892 case HAL_TSO_TSIF_LIVE1:
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
894 break;
895 case HAL_TSO_TSIF_LIVE2:
896 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
897 break;
898 case HAL_TSO_TSIF_LIVE3:
899 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
900 break;
901 case HAL_TSO_TSIF_LIVE4:
902 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
903 break;
904 case HAL_TSO_TSIF_LIVE5:
905 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
906 break;
907 case HAL_TSO_TSIF_LIVE6:
908 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
909 break;
910 default:
911 printf("Not support !!\n");
912 break;
913 }
914 }
915 else
916 {
917 switch(u8Eng)
918 {
919 case HAL_TSO_TSIF_LIVE1:
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
921 break;
922 case HAL_TSO_TSIF_LIVE2:
923 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
924 break;
925 case HAL_TSO_TSIF_LIVE3:
926 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
927 break;
928 case HAL_TSO_TSIF_LIVE4:
929 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
930 break;
931 case HAL_TSO_TSIF_LIVE5:
932 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
933 break;
934 case HAL_TSO_TSIF_LIVE6:
935 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
936 break;
937 default:
938 printf("Not support !!\n");
939 break;
940 }
941 }
942
943 return TRUE;
944 }
945
946 // ------------------------------------------------------
947 // APIS
948 //-------------------------------------------------------
949 #define TSO_PIDFLT_ADDR(FltId) (REG_PIDFLT_BASE + ((FltId) << 2))
950
_HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr,MS_U16 u16Wdata,MS_U8 u8Sid)951 static void _HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr, MS_U16 u16Wdata, MS_U8 u8Sid)
952 {
953 // addr
954 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
955 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
956
957 // Wdata
958 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F));
960
961 // Wen
962 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
963 }
964
_HAL_TSO_PageTableIndW(MS_U32 u32Addr,MS_U16 u16Wdata)965 static void _HAL_TSO_PageTableIndW(MS_U32 u32Addr, MS_U16 u16Wdata)
966 {
967 // addr
968 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
969 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
970
971 // Wdata
972 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000);
974
975 // Wen
976 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
977 }
978
_HAL_TSO_PageTableIndR(MS_U32 u32Addr)979 static MS_U16 _HAL_TSO_PageTableIndR(MS_U32 u32Addr)
980 {
981 // addr
982 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
983 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
984
985 // Ren
986 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN);
987
988 // Rdata
989 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA));
990 }
991
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)992 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
993 {
994 MS_U16 u16Temp = 0;
995
996 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
997 u16Temp = (u16Temp & (TSO_PIDFLT_IN_MASK << TSO_PIDFLT_IN_SHIFT)) | (u16PID & TSO_PIDFLT_PID_MASK);
998 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
999 }
1000
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32Addr)1001 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32Addr)
1002 {
1003 REG32_TSO *FileInRaddr;
1004 MS_U8 u8MiuSel;
1005 MS_PHY phyMiuOffsetFileinBuf;
1006
1007 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinBuf, u32Addr);
1008
1009 if(u8FileEng == 0)
1010 {
1011 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]);
1012 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_CH5FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH5FILEIN_SHIFT) & REG_MIU_SEL_CH5FILEIN_MASK));
1013 }
1014 else
1015 {
1016 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]);
1017 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_2, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_2) & (~REG_MIU_SEL_CH6FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH6FILEIN_SHIFT) & REG_MIU_SEL_CH6FILEIN_MASK));
1018 }
1019
1020 _HAL_REG32_W(FileInRaddr, phyMiuOffsetFileinBuf);
1021 }
1022
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)1023 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
1024 {
1025 REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_68[1]);
1026
1027 _HAL_REG32_W(FileInRlen, u32len);
1028 }
1029
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)1030 MS_U32 HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
1031 {
1032 MS_U32 u32temp = 0;
1033 REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1);
1034 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1035
1036
1037 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1038 u32temp = (_HAL_REG32_R(TSO2MI_RADDR) << TSO_MIU_BUS);
1039 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1040
1041 return u32temp;
1042 }
1043
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)1044 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
1045 {
1046 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1047
1048 _HAL_REG16_W(FileinCtrl, (_HAL_REG16_R(FileinCtrl) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1049 }
1050
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)1051 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
1052 {
1053 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1054
1055 return (_HAL_REG16_R(FileinCtrl) & TSO_FILEIN_CTRL_MASK);
1056 }
1057
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1058 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1059 {
1060 MS_U16 u16ChIf = (u8FileEng == 0)? TSO_CFG1_TSO_TSIF5_EN : TSO_CFG1_TSO_TSIF6_EN;
1061
1062 HAL_TSO_Cfg1_Enable(0, u16ChIf, bEnable);
1063 HAL_TSO_File_Cfg1_Enable(u8FileEng, (TSO_FILE_CONFIG_TSO_FILE_IN|TSO_FILE_CONFIG_TSP_FILE_SEGMENT|TSO_FILE_CONFIG_TS_DATA_PORT_SEL), bEnable);
1064
1065 return TRUE;
1066 }
1067
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1068 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1069 {
1070 REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1071
1072 if(bEnable)
1073 {
1074 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) | TSO_FILE_CONFIG_TIMER_EN);
1075 }
1076 else
1077 {
1078 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) & ~TSO_FILE_CONFIG_TIMER_EN);
1079 }
1080 }
1081
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1082 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1083 {
1084 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer);
1085 }
1086
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1087 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1088 {
1089 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1090
1091 if(bEnable)
1092 {
1093 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_EN));
1094 }
1095 else
1096 {
1097 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_EN));
1098 }
1099 }
1100
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1101 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1102 {
1103 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1104
1105 if(bEnable)
1106 {
1107 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1108 }
1109 else
1110 {
1111 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1112 }
1113 }
1114
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1115 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1116 {
1117 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK;
1118 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT;
1119
1120 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1121 }
1122
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)1123 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)
1124 {
1125 //@TODO not implement
1126 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_FULL);
1127 return FALSE;
1128 }
1129
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)1130 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)
1131 {
1132 //@TODO not implement
1133 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_EMPTY);
1134 return FALSE;
1135 }
1136
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1137 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1138 {
1139 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK;
1140 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT;
1141
1142 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1143 }
1144
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1145 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1146 {
1147 MS_U16 u16data = ((u8FileEng == 0)? TSO_SW_RST_CMDQ : TSO_SW_RST_CMDQ1);
1148
1149 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1150 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1151
1152 return TRUE;
1153 }
1154
HAL_TSO_Cfg0_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1155 void HAL_TSO_Cfg0_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1156 {
1157 //@TODO not implement
1158 /*
1159 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG0));
1160
1161 if(benable)
1162 {
1163 u16data |= u16CfgItem;
1164 }
1165 else
1166 {
1167 u16data &= ~u16CfgItem;
1168 }
1169
1170 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG0), u16data);
1171 */
1172 }
1173
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1174 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1175 {
1176 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1));
1177
1178 if(benable)
1179 {
1180 u16data |= u16CfgItem;
1181 }
1182 else
1183 {
1184 u16data &= ~u16CfgItem;
1185 }
1186
1187 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD));
1188 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1189 }
1190
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1191 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1192 {
1193 switch(u8ChIf)
1194 {
1195 case HAL_TSO_TSIF_LIVE1:
1196 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1197 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1198 break;
1199 case HAL_TSO_TSIF_LIVE2:
1200 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1201 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1202 break;
1203 case HAL_TSO_TSIF_LIVE3:
1204 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1205 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1206 break;
1207 case HAL_TSO_TSIF_LIVE4:
1208 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1209 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1210 break;
1211 case HAL_TSO_TSIF_LIVE5:
1212 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1213 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1214 break;
1215 case HAL_TSO_TSIF_LIVE6:
1216 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1217 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1218 break;
1219 default:
1220 return FALSE;
1221 }
1222
1223 return TRUE;
1224 }
1225
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1226 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1227 {
1228 switch(u8ChIf)
1229 {
1230 case HAL_TSO_TSIF_LIVE1:
1231 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF1_EN, bEnable);
1232 break;
1233 case HAL_TSO_TSIF_LIVE2:
1234 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF2_EN, bEnable);
1235 break;
1236 case HAL_TSO_TSIF_LIVE3:
1237 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF3_EN, bEnable);
1238 break;
1239 case HAL_TSO_TSIF_LIVE4:
1240 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF4_EN, bEnable);
1241 break;
1242 case HAL_TSO_TSIF_LIVE5:
1243 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF5_EN, bEnable);
1244 break;
1245 case HAL_TSO_TSIF_LIVE6:
1246 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF6_EN, bEnable);
1247 break;
1248 default:
1249 return FALSE;
1250 }
1251
1252 return TRUE;
1253 }
1254
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1255 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1256 {
1257 REG16_TSO *reg = NULL;
1258 MS_U16 u16data = 0;
1259
1260 switch(u8ChIf)
1261 {
1262 case HAL_TSO_TSIF_LIVE1:
1263 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1264 break;
1265 case HAL_TSO_TSIF_LIVE2:
1266 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1267 break;
1268 case HAL_TSO_TSIF_LIVE3:
1269 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1270 break;
1271 case HAL_TSO_TSIF_LIVE4:
1272 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1273 break;
1274 case HAL_TSO_TSIF_LIVE5:
1275 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1276 break;
1277 case HAL_TSO_TSIF_LIVE6:
1278 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1279 break;
1280 default:
1281 return FALSE;
1282 }
1283
1284 u16data = _HAL_REG16_R(reg);
1285
1286 if(bEnable)
1287 {
1288 u16data |= u16Cfg;
1289 }
1290 else
1291 {
1292 u16data &= ~u16Cfg;
1293 }
1294
1295 _HAL_REG16_W(reg, u16data);
1296 return TRUE;
1297 }
1298
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1299 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1300 {
1301 REG16_TSO* pReg = NULL;
1302 MS_U16 u16data = 0;
1303
1304 *pu16Cfg = 0;
1305 *pbEnable = FALSE;
1306
1307 switch(u8ChIf)
1308 {
1309 case HAL_TSO_TSIF_LIVE1:
1310 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1311 break;
1312 case HAL_TSO_TSIF_LIVE2:
1313 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1314 break;
1315 case HAL_TSO_TSIF_LIVE3:
1316 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1317 break;
1318 case HAL_TSO_TSIF_LIVE4:
1319 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1320 break;
1321 case HAL_TSO_TSIF_LIVE5:
1322 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1323 break;
1324 case HAL_TSO_TSIF_LIVE6:
1325 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1326 break;
1327 default:
1328 return FALSE;
1329 }
1330
1331 *pu16Cfg = _HAL_REG16_R(pReg);
1332
1333 switch(u8ChIf)
1334 {
1335 case HAL_TSO_TSIF_LIVE1:
1336 u16data = TSO_CFG1_TSO_TSIF1_EN;
1337 break;
1338 case HAL_TSO_TSIF_LIVE2:
1339 u16data = TSO_CFG1_TSO_TSIF2_EN;
1340 break;
1341 case HAL_TSO_TSIF_LIVE3:
1342 u16data = TSO_CFG1_TSO_TSIF3_EN;
1343 break;
1344 case HAL_TSO_TSIF_LIVE4:
1345 u16data = TSO_CFG1_TSO_TSIF4_EN;
1346 break;
1347 case HAL_TSO_TSIF_LIVE5:
1348 u16data = TSO_CFG1_TSO_TSIF5_EN;
1349 break;
1350 case HAL_TSO_TSIF_LIVE6:
1351 u16data = TSO_CFG1_TSO_TSIF6_EN;
1352 break;
1353 default:
1354 return FALSE;
1355 }
1356
1357 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data);
1358
1359 return TRUE;
1360 }
1361
HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1362 void HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1363 {
1364 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1365 MS_U16 u16data = _HAL_REG16_R(reg);
1366
1367 if(benable)
1368 {
1369 u16data |= u16CfgItem;
1370 }
1371 else
1372 {
1373 u16data &= ~u16CfgItem;
1374 }
1375
1376 _HAL_REG16_W(reg, u16data);
1377 }
1378
1379
1380
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U32 u32CfgItem,MS_BOOL benable)1381 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U32 u32CfgItem, MS_BOOL benable)
1382 {
1383 //@TODO not implement
1384 /*
1385 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG4));
1386
1387 if(benable)
1388 {
1389 u16data |= u32CfgItem;
1390 }
1391 else
1392 {
1393 u16data &= ~u32CfgItem;
1394 }
1395
1396 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG4), u16data);
1397 */
1398 }
1399
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1400 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1401 {
1402 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1403
1404 if(bWrite)
1405 {
1406 u16data &= ~TSO_CONFIG2_VALID_BYTE_CNT_MASK;
1407 u16data |= (*pu16ValidBlockCnt << TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1408 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1409
1410 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1411 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1412 }
1413 else
1414 {
1415 *pu16ValidBlockCnt = ((u16data & TSO_CONFIG2_VALID_BYTE_CNT_MASK) >> TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1416 }
1417 }
1418
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1419 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1420 {
1421 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1422
1423 if(bWrite)
1424 {
1425 u16data &= ~TSO_CONFIG2_INVALID_BYTE_CNT_MASK;
1426 u16data |= (*pu16InvalidBlockCnt << TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT);
1427 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1428
1429 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1430 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1431 }
1432 else
1433 {
1434 *pu16InvalidBlockCnt = (u16data & TSO_CONFIG2_INVALID_BYTE_CNT_MASK) >> TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT;
1435 }
1436 }
1437
HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)1438 MS_U32 HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)
1439 {
1440 //@TODO not implement
1441 //return (_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK);
1442 return 0;
1443 }
1444
HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)1445 MS_U32 HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)
1446 {
1447 //@TODO not implement
1448 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK) >> TSO_HD_ADP_FIELD_SHIFT);
1449 return 0;
1450 }
1451
HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)1452 MS_U32 HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)
1453 {
1454 //@TODO not implement
1455 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PID_MASK) >> TSO_HD_PID_SHIFT);
1456 return 0;
1457 }
1458
HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)1459 MS_U32 HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)
1460 {
1461 //@TODO not implement
1462 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_SCRM_FIELD_MASK) >> TSO_HD_SCRM_FIELD_SHIFT);
1463 return 0;
1464 }
1465
HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)1466 MS_U32 HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)
1467 {
1468 //@TODO not implement
1469 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_TS_PRIORITY_MASK) >> TSO_HD_TS_PRIORITY_SHIFT);
1470 return 0;
1471 }
1472
HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)1473 MS_U32 HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)
1474 {
1475 //@TODO not implement
1476 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_START_IND_MASK) >> TSO_HD_PAYLOAD_START_IND_SHIFT);
1477 return 0;
1478 }
1479
HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)1480 MS_U32 HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)
1481 {
1482 //@TODO not implement
1483 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_ERR_IND_MASK) >> TSO_HD_PAYLOAD_ERR_IND_SHIFT);
1484 return 0;
1485 }
1486
HAL_TSO_Get_Pid_Info(MS_U8 u8Eng,MS_U16 * pu16matchpid,MS_BOOL * pbchanged)1487 void HAL_TSO_Get_Pid_Info(MS_U8 u8Eng, MS_U16 *pu16matchpid, MS_BOOL *pbchanged)
1488 {
1489 //@TODO not implement
1490 /*
1491 MS_U16 u16temp;
1492
1493 u16temp = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_PID_Info));
1494
1495 *pu16matchpid = u16temp & TSO_PID_INFO_MATCH_PID_MASK;
1496 *pbchanged = (((u16temp & TSO_PID_INFO_MATCH_PID_CHANGE_MASK) > 0) ? TRUE: FALSE);
1497 */
1498 }
1499
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1500 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1501 {
1502 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1503 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1504
1505
1506 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1507 _HAL_REG32_W(LPCR2, u32lpcr2);
1508 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1509 }
1510
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1511 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1512 {
1513 MS_U32 u32temp = 0;
1514 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1515 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1516
1517
1518 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1519 u32temp = _HAL_REG32_R(LPCR2);
1520 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1521
1522 return u32temp;
1523 }
1524
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1525 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1526 {
1527 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1);
1528
1529 return _HAL_REG32_R(TIMESTAMP);
1530 }
1531
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1532 void HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1533 {
1534 switch(u8If)
1535 {
1536 case HAL_TSO_TSIF_LIVE1:
1537 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1538 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1539 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1540 break;
1541 case HAL_TSO_TSIF_LIVE2:
1542 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1543 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1544 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1545 break;
1546 case HAL_TSO_TSIF_LIVE3:
1547 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1548 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1549 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1550 break;
1551 case HAL_TSO_TSIF_LIVE4:
1552 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1553 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1554 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1555 break;
1556 case HAL_TSO_TSIF_LIVE5:
1557 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1558 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1559 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1560 break;
1561 case HAL_TSO_TSIF_LIVE6:
1562 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1563 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1564 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1565 break;
1566 default:
1567 printf("Not support !!\n");
1568 break;
1569 }
1570 }
1571
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1572 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1573 {
1574 if(bWrite)
1575 {
1576 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize);
1577 }
1578 else
1579 {
1580 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3));
1581 }
1582
1583 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1584 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1585 }
1586
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1587 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1588 {
1589 switch(u8FileEng)
1590 {
1591 case 0:
1592 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1593 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK)
1594 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN_SHIFT)) & TSO_PKT_CHK_SIZE_FIN_MASK));
1595 break;
1596 case 1:
1597 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1598 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK)
1599 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN1_SHIFT)) & TSO_PKT_CHK_SIZE_FIN1_MASK));
1600 break;
1601 default:
1602 printf("Not support !!\n");
1603 break;
1604 }
1605 }
1606
HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1607 void HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1608 {
1609 switch(u8If)
1610 {
1611 case HAL_TSO_TSIF_LIVE1:
1612 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1613 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1614 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1615 break;
1616 case HAL_TSO_TSIF_LIVE2:
1617 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1618 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1619 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1620 break;
1621 case HAL_TSO_TSIF_LIVE3:
1622 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1623 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1624 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1625 break;
1626 case HAL_TSO_TSIF_LIVE4:
1627 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1628 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1629 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1630 break;
1631 case HAL_TSO_TSIF_LIVE5:
1632 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1633 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1634 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1635 break;
1636 case HAL_TSO_TSIF_LIVE6:
1637 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1638 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1639 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1640 break;
1641 default:
1642 printf("Not support !!\n");
1643 break;
1644 }
1645 }
1646
1647
HAL_TSO_Livein_Input_Config(MS_U8 u8Eng,MS_U8 u8PktInputMode,MS_U8 u8PktSyncByte,MS_U8 u8PktHeaderLength)1648 void HAL_TSO_Livein_Input_Config(MS_U8 u8Eng, MS_U8 u8PktInputMode, MS_U8 u8PktSyncByte, MS_U8 u8PktHeaderLength)
1649 {
1650 switch(u8Eng)
1651 {
1652 case HAL_TSO_TSIF_LIVE1:
1653 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1654 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK)
1655 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK));
1656
1657 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1658 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK)
1659 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK));
1660
1661 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1662 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK)
1663 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK));
1664 break;
1665 case HAL_TSO_TSIF_LIVE2:
1666 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1667 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK)
1668 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK));
1669
1670 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1671 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK)
1672 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK));
1673
1674 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1675 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK)
1676 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK));
1677 break;
1678 case HAL_TSO_TSIF_LIVE3:
1679 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1680 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK)
1681 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK));
1682
1683 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1684 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK)
1685 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK));
1686
1687 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1688 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK)
1689 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK));
1690 break;
1691 case HAL_TSO_TSIF_LIVE4:
1692 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1693 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK)
1694 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK));
1695
1696 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1697 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK)
1698 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK));
1699
1700 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1701 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK)
1702 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK));
1703 break;
1704 case HAL_TSO_TSIF_LIVE5:
1705 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1706 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK)
1707 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK));
1708
1709 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1710 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK)
1711 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK));
1712
1713 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1714 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK)
1715 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK));
1716 break;
1717 case HAL_TSO_TSIF_LIVE6:
1718 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1719 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK)
1720 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK));
1721
1722 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1723 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK)
1724 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK));
1725
1726 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1727 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK)
1728 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK));
1729 break;
1730 default:
1731 printf("Not support !!\n");
1732 break;
1733 }
1734 }
1735
1736
HAL_TSO_Livein_3Wire(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1737 void HAL_TSO_Livein_3Wire(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1738 {
1739 if(bEnable)
1740 {
1741 switch(u8ChIf)
1742 {
1743 case HAL_TSO_TSIF_LIVE1:
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1745 break;
1746 case HAL_TSO_TSIF_LIVE2:
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1748 break;
1749 case HAL_TSO_TSIF_LIVE3:
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1751 break;
1752 case HAL_TSO_TSIF_LIVE4:
1753 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1754 break;
1755 case HAL_TSO_TSIF_LIVE5:
1756 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1757 break;
1758 case HAL_TSO_TSIF_LIVE6:
1759 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1760 break;
1761 default:
1762 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1763 break;
1764 }
1765 }
1766 else
1767 {
1768 switch(u8ChIf)
1769 {
1770 case HAL_TSO_TSIF_LIVE1:
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1772 break;
1773 case HAL_TSO_TSIF_LIVE2:
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1775 break;
1776 case HAL_TSO_TSIF_LIVE3:
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1778 break;
1779 case HAL_TSO_TSIF_LIVE4:
1780 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1781 break;
1782 case HAL_TSO_TSIF_LIVE5:
1783 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1784 break;
1785 case HAL_TSO_TSIF_LIVE6:
1786 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1787 break;
1788 default:
1789 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1790 break;
1791 }
1792
1793 }
1794 }
1795
HAL_TSO_TsioMode_En(MS_BOOL bEnable)1796 void HAL_TSO_TsioMode_En(MS_BOOL bEnable)
1797 {
1798 if(bEnable)
1799 {
1800 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE);
1801 }
1802 else
1803 {
1804 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE);
1805 }
1806 }
1807
HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)1808 void HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)
1809 {
1810 if(bEnable)
1811 {
1812 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF);
1813 }
1814 else
1815 {
1816 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF);
1817 }
1818 }
1819
HAL_TSO_SerialMode_En(MS_BOOL bEnable)1820 void HAL_TSO_SerialMode_En(MS_BOOL bEnable)
1821 {
1822 if(bEnable)
1823 {
1824 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1825 }
1826 else
1827 {
1828 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1829 }
1830 }
1831
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1832 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1833 {
1834 REG32_TSO *Base = NULL;
1835 REG16_TSO *Size = NULL, *TX_Config = NULL;
1836
1837
1838 switch(u8ChIf)
1839 {
1840 case HAL_TSO_TSIF_LIVE1:
1841 Base = &(_TSOCtrl1->SVQ1_BASE);
1842 Size = &(_TSOCtrl1->SVQ1_SIZE_200BYTE);
1843 TX_Config = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1844 break;
1845 case HAL_TSO_TSIF_LIVE2:
1846 Base = &(_TSOCtrl1->SVQ2_BASE);
1847 Size = &(_TSOCtrl1->SVQ2_SIZE_200BYTE);
1848 TX_Config = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1849 break;
1850 case HAL_TSO_TSIF_LIVE3:
1851 Base = &(_TSOCtrl1->SVQ3_BASE);
1852 Size = &(_TSOCtrl1->SVQ3_SIZE_200BYTE);
1853 TX_Config = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1854 break;
1855 case HAL_TSO_TSIF_LIVE4:
1856 Base = &(_TSOCtrl1->SVQ4_BASE);
1857 Size = &(_TSOCtrl1->SVQ4_SIZE_200BYTE);
1858 TX_Config = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1859 break;
1860 case HAL_TSO_TSIF_LIVE5:
1861 Base = &(_TSOCtrl1->SVQ5_BASE);
1862 Size = &(_TSOCtrl1->SVQ5_SIZE_200BYTE);
1863 TX_Config = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1864 break;
1865 case HAL_TSO_TSIF_LIVE6:
1866 Base = &(_TSOCtrl1->SVQ6_BASE);
1867 Size = &(_TSOCtrl1->SVQ6_SIZE_200BYTE);
1868 TX_Config = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1869 break;
1870 default:
1871 printf("Not support !!\n");
1872 return FALSE;
1873 }
1874
1875 _HAL_REG32_W(Base, ((phyBufAddr >> TSO_MIU_BUS) & TSO1_SVQ1_BASE_MASK));
1876 _HAL_REG16_W(Size, ((u32BufSize / TSO_SVQ_UNIT_SIZE) & TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK));
1877 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1878 _REG16_CLR(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1879 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);
1880
1881 return TRUE;
1882 }
1883
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1884 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1885 {
1886 REG16_TSO* p16Reg = NULL;
1887
1888 if(u8Eng > 0)
1889 {
1890 return FALSE;
1891 }
1892
1893 switch(u8ChIf)
1894 {
1895 case HAL_TSO_TSIF_LIVE1:
1896 p16Reg = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1897 break;
1898 case HAL_TSO_TSIF_LIVE2:
1899 p16Reg = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1900 break;
1901 case HAL_TSO_TSIF_LIVE3:
1902 p16Reg = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1903 break;
1904 case HAL_TSO_TSIF_LIVE4:
1905 p16Reg = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1906 break;
1907 case HAL_TSO_TSIF_LIVE5:
1908 p16Reg = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1909 break;
1910 case HAL_TSO_TSIF_LIVE6:
1911 p16Reg = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1912 break;
1913 default:
1914 printf("Not support !!\n");
1915 return FALSE;
1916 }
1917
1918 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1919 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1920 return TRUE;
1921 }
1922
HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem,MS_BOOL benable)1923 void HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem, MS_BOOL benable)
1924 {
1925 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG));
1926
1927 if(benable)
1928 {
1929 u16data |= u16CfgItem;
1930 }
1931 else
1932 {
1933 u16data &= ~u16CfgItem;
1934 }
1935
1936 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), u16data);
1937 }
1938
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1939 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1940 {
1941 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), (_HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG)) & ~TSO1_SVQ_RX_CONFIG_MODE_MASK) | u16mode);
1942
1943 return TRUE;
1944 }
1945
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1946 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1947 {
1948 MS_U32 u32data = 0;
1949 MS_U32 u32Shift = 0;
1950
1951 *pu16Status = 0;
1952 u32data = _HAL_REG32_R(&(_TSOCtrl1->SVQ_STATUS));
1953
1954 switch(u8ChIf)
1955 {
1956 case HAL_TSO_TSIF_LIVE1:
1957 u32Shift = TSO_SVQ1_STS_SHIFT;
1958 break;
1959 case HAL_TSO_TSIF_LIVE2:
1960 u32Shift = TSO_SVQ2_STS_SHIFT;
1961 break;
1962 case HAL_TSO_TSIF_LIVE3:
1963 u32Shift = TSO_SVQ3_STS_SHIFT;
1964 break;
1965 case HAL_TSO_TSIF_LIVE4:
1966 u32Shift = TSO_SVQ4_STS_SHIFT;
1967 break;
1968 case HAL_TSO_TSIF_LIVE5:
1969 u32Shift = TSO_SVQ5_STS_SHIFT;
1970 break;
1971 case HAL_TSO_TSIF_LIVE6:
1972 u32Shift = TSO_SVQ6_STS_SHIFT;
1973 break;
1974 default:
1975 return FALSE;
1976 }
1977
1978 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1979
1980 return TRUE;
1981 }
1982
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1983 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1984 {
1985 //@TODO not implement
1986 return TRUE;
1987 }
1988
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1989 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1990 {
1991 //@TODO not implement
1992 return TRUE;
1993 }
1994
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1995 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1996 {
1997 REG16_TSO* p16Reg = NULL;
1998
1999 switch(u8ChIf)
2000 {
2001 case HAL_TSO_TSIF_LIVE1:
2002 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_1_CONFIG_0);
2003 break;
2004 case HAL_TSO_TSIF_LIVE2:
2005 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_2_CONFIG_0);
2006 break;
2007 case HAL_TSO_TSIF_LIVE3:
2008 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_3_CONFIG_0);
2009 break;
2010 case HAL_TSO_TSIF_LIVE4:
2011 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_4_CONFIG_0);
2012 break;
2013 case HAL_TSO_TSIF_LIVE5:
2014 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_5_CONFIG_0);
2015 break;
2016 case HAL_TSO_TSIF_LIVE6:
2017 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_6_CONFIG_0);
2018 break;
2019 default:
2020 return FALSE;
2021 }
2022
2023 if(beSet == TRUE)
2024 {
2025 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2026 }
2027 else
2028 {
2029 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2030 }
2031
2032 return TRUE;
2033
2034 }
2035
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)2036 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
2037 {
2038 MS_U16 u16Temp = 0;
2039
2040 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2041 u16Temp = (u16Temp & TSO_PIDFLT_PID_MASK) | ((u16InputSrc & TSO_PIDFLT_IN_MASK) << TSO_PIDFLT_IN_SHIFT);
2042 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
2043 }
2044
HAL_TSO_Flt_SetSid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8Sid)2045 void HAL_TSO_Flt_SetSid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8Sid)
2046 {
2047 MS_U16 u16Temp = 0;
2048
2049 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2050 _HAL_TSO_PageTableIndW_withSid(TSO_PIDFLT_ADDR(u16FltId), u16Temp, u8Sid);
2051 }
2052
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)2053 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
2054 {
2055 //@TODO not implement
2056 return TRUE;
2057 }
2058
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)2059 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
2060 {
2061 //@TODO not implement
2062 return TRUE;
2063 }
2064
HAL_TSO_SaveRegs(void)2065 void HAL_TSO_SaveRegs(void)
2066 {
2067 //@TODO not implement
2068 }
2069
HAL_TSO_RestoreRegs(void)2070 void HAL_TSO_RestoreRegs(void)
2071 {
2072 //@TODO not implement
2073 }
2074
2075 #ifdef CONFIG_MSTAR_CLKM
HAL_TSO_PowerCtrl(MS_BOOL bOn)2076 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2077 {
2078 MS_S32 s32ClkHandle;
2079
2080 if (bOn)
2081 {
2082 // Enable TSO out Clock
2083 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2084 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOOUT_DIV");
2085
2086 // Enable TSO in Clock
2087 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2088 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOIN0_PAD0");
2089
2090 // Enable TSO1 in Clock
2091 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2092 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN1_PAD0");
2093
2094 // Enable TSO2 in Clock
2095 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2096 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN2_PAD0");
2097
2098 // Enable TSO3 in Clock
2099 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2100 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN3_PAD0");
2101
2102 // Enable TSO4 in Clock
2103 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2104 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN4_PAD0");
2105
2106 // Enable TSO5 in Clock
2107 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2108 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN5_PAD0");
2109
2110 // Disable MCM
2111 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2112 }
2113 else
2114 {
2115 // Enable MCM
2116 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2117
2118 // Disabel TSO out Clock
2119 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2120 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2121
2122 // Disabel TSO in Clock
2123 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2124 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2125
2126 // Disabel TSO1 in Clock
2127 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2128 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2129
2130 // Disabel TSO2 in Clock
2131 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2132 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2133
2134 // Disabel TSO3 in Clock
2135 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2136 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2137
2138 // Disabel TSO4 in Clock
2139 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2140 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2141
2142 // Disabel TSO5 in Clock
2143 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2144 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2145 }
2146 }
2147 #else
HAL_TSO_PowerCtrl(MS_BOOL bOn)2148 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2149 {
2150 if (bOn)
2151 {
2152 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
2153 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2154 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2155 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2156 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2157 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2158 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2159
2160 // Disable MCM
2161 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2162 }
2163 else
2164 {
2165 // Enable MCM
2166 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2167
2168 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
2169 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2170 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2171 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2172 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2173 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2174 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2175 }
2176 }
2177 #endif
2178
HAL_TSO_PcrFlt_Enable(MS_U8 u8ChIf,MS_U16 u16PID,MS_BOOL bEnable)2179 MS_BOOL HAL_TSO_PcrFlt_Enable(MS_U8 u8ChIf, MS_U16 u16PID, MS_BOOL bEnable)
2180 {
2181 if(bEnable)
2182 {
2183 _HAL_REG16_W(&(_TSOCtrl2->REG_TSO2_PIDFLT_PCR_CFG32_37[u8ChIf]), (TSO2_REG_PIDFLT_PCR_ENPCR | (TSO2_REG_PIDFLT_PCR_PID_MASK & u16PID)));
2184 }
2185 else
2186 {
2187 _HAL_REG16_W(&(_TSOCtrl2->REG_TSO2_PIDFLT_PCR_CFG32_37[u8ChIf]), (~TSO2_REG_PIDFLT_PCR_ENPCR | TSO2_REG_PIDFLT_PCR_PID_MASK));
2188 }
2189 return TRUE;
2190 }
2191
HAL_TSO_Pcr_Get(MS_U8 u8ChIf,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)2192 MS_BOOL HAL_TSO_Pcr_Get(MS_U8 u8ChIf, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
2193 {
2194
2195 switch(u8ChIf)
2196 {
2197 case HAL_TSO_TSIF_LIVE1:
2198 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_READ);
2199 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR1_LOW32_CFG38_39));
2200 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR1_VAILD_CFG3A)) & 0x1;
2201 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_READ);
2202 break;
2203
2204 case HAL_TSO_TSIF_LIVE2:
2205 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_READ);
2206 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR2_LOW32_CFG3B_3C));
2207 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR2_VAILD_CFG3D)) & 0x1;
2208 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_READ);
2209 break;
2210
2211 case HAL_TSO_TSIF_LIVE3:
2212 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_READ);
2213 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR3_LOW32_CFG3E_3F));
2214 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR3_VAILD_CFG40)) & 0x1;
2215 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_READ);
2216 break;
2217
2218 case HAL_TSO_TSIF_LIVE4:
2219 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_READ);
2220 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR4_LOW32_CFG41_42));
2221 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR4_VAILD_CFG43)) & 0x1;
2222 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_READ);
2223 break;
2224
2225 case HAL_TSO_TSIF_LIVE5:
2226 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR5_READ);
2227 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR5_LOW32_CFG44_45));
2228 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR5_VAILD_CFG46)) & 0x1;
2229 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR5_READ);
2230 break;
2231
2232 case HAL_TSO_TSIF_LIVE6:
2233 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR6_READ);
2234 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR6_LOW32_CFG47_48));
2235 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR6_VAILD_CFG49)) & 0x1;
2236 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR6_READ);
2237 break;
2238
2239 default:
2240 return FALSE;
2241 }
2242 return TRUE;
2243 }
2244
2245
HAL_TSO_PcrClr(MS_U8 u8ChIf,MS_BOOL bEnable)2246 MS_BOOL HAL_TSO_PcrClr(MS_U8 u8ChIf, MS_BOOL bEnable)
2247 {
2248 if(bEnable == TRUE)
2249 {
2250 switch(u8ChIf)
2251 {
2252 case HAL_TSO_TSIF_LIVE1:
2253 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_RESET);
2254 break;
2255 case HAL_TSO_TSIF_LIVE2:
2256 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_RESET);
2257 break;
2258 case HAL_TSO_TSIF_LIVE3:
2259 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_RESET);
2260 break;
2261 case HAL_TSO_TSIF_LIVE4:
2262 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_RESET);
2263 break;
2264 case HAL_TSO_TSIF_LIVE5:
2265 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR5_RESET);
2266 break;
2267 case HAL_TSO_TSIF_LIVE6:
2268 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR6_RESET);
2269 break;
2270 default:
2271 return FALSE;
2272 }
2273 return TRUE;
2274 }
2275 else
2276 {
2277 switch(u8ChIf)
2278 {
2279 case HAL_TSO_TSIF_LIVE1:
2280 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_RESET);
2281 break;
2282 case HAL_TSO_TSIF_LIVE2:
2283 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_RESET);
2284 break;
2285 case HAL_TSO_TSIF_LIVE3:
2286 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_RESET);
2287 break;
2288 case HAL_TSO_TSIF_LIVE4:
2289 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_RESET);
2290 break;
2291 case HAL_TSO_TSIF_LIVE5:
2292 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR5_RESET);
2293 break;
2294 case HAL_TSO_TSIF_LIVE6:
2295 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR6_RESET);
2296 break;
2297 default:
2298 return FALSE;
2299 }
2300 return TRUE;
2301
2302 }
2303
2304 }
2305
2306
HAL_TSO_Set_SvqBypass(MS_BOOL bEnable)2307 MS_BOOL HAL_TSO_Set_SvqBypass(MS_BOOL bEnable)
2308 {
2309 if(bEnable)
2310 {
2311 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1);
2312 }
2313 else
2314 {
2315 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1);
2316 }
2317
2318 return TRUE;
2319 }
2320