1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSO.c
97 // @brief TS I/O HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSO.h"
101 #include "halCHIP.h"
102
103 #ifdef CONFIG_MSTAR_CLKM
104 #include "drvCLKM.h"
105 #endif //CONFIG_MSTAR_CLKM
106
107
108 //--------------------------------------------------------------------------------------------------
109 // Driver Compiler Option
110 //--------------------------------------------------------------------------------------------------
111 #define TSP_HAL_REG_SAFE_MODE 1UL // Register protection access between 1 task and 1+ ISR
112
113 //-------------------------------------------------------------------------------------------------
114 // Local Structures
115 //-------------------------------------------------------------------------------------------------
116 typedef struct _HalTSO_OutPad
117 {
118 MS_U16 u16OutPad[TSO_ENGINE_NUM];
119 MS_U16 u16TSCfgOld[TSO_ENGINE_NUM];
120 MS_U16 u16TSOutModeOld[TSO_ENGINE_NUM];
121 } HalTSO_OutPad;
122
123 //--------------------------------------------------------------------------------------------------
124 // TSP Hardware Abstraction Layer
125 //--------------------------------------------------------------------------------------------------
126 static REG_Ctrl_TSO* _TSOCtrl = NULL;
127 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
128
129
130 static MS_VIRT _virtTSORegBase = 0;
131 static MS_PHY _phyTSOFiMiuOffset[TSO_FILE_IF_NUM] = {[0 ... (TSO_FILE_IF_NUM-1)] = 0UL};
132 static MS_PHY _phyTSOVQiMiuOffset = 0UL;
133
134 static HalTSO_OutPad _stOutPadCtrl;
135
136 #ifdef MSOS_TYPE_LINUX_KERNEL
137 static MS_U16 _u16TSORegArray[2][128];
138 static MS_U16 _u16TSOTopReg[3][8];
139 #endif
140
141
142 //[NOTE] Jerry
143 // Some register has write order, for example, writing PCR_L will disable PCR counter
144 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
145 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFFUL); \
146 (reg)->H = ((value) >> 16UL); } while(0)
147
148 #define _HAL_REG16_W(reg, value) (reg)->data = (value);
149
150 #define TSO0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO + ((addr)<<2UL))))
151 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((addr)<<2UL))))
152
153 //--------------------------------------------------------------------------------------------------
154 // Macro of bit operations
155 //--------------------------------------------------------------------------------------------------
156 #define HAS_FLAG(flag, bit) ((flag) & (bit))
157 #define SET_FLAG(flag, bit) ((flag)|= (bit))
158 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
159 #define SET_FLAG1(flag, bit) ((flag)| (bit))
160 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
161
162 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x6600UL + ((addr)<<2UL))))
163 #define REG_CLKGEN1_TSO_IN 0x22UL
164 #define REG_CLKGEN1_TSO_TRACE_MASK 0x000FUL
165 #define REG_CLKGEN1_TSO_TRACE_DISABLE 0x0001UL
166 #define REG_CLKGEN1_TSO_TRACE_INVERT 0x0002UL
167 #define REG_CLKGEN1_TSO_TRACE_216M 0x0000UL
168 #define REG_CLKGEN1_TSO_IN_MASK 0x1F00UL
169 #define REG_CLKGEN1_TSO_IN_SHIFT 8UL
170 #define REG_CLKGEN1_TSO_IN_DISABLE 0x0100UL
171 #define REG_CLKGEN1_TSO_IN_INVERT 0x0200UL
172 // bit[12:8] -> 0: disable clock
173 // 1: invert clock
174 // bit [4:2] -> 000: Sel TS0 Clk
175 // 001: Sel TS1 Clk
176 // 010: Sel TS2 Clk
177 // 011: Sel TS3 Clk
178 // 100: Sel TS4 Clk
179 // 101: Sel TS5 Clk
180 // 110: Sel Dmd Clk
181 #define REG_CLKGEN1_TSO_OUT_PHASE 0x24UL
182 #define REG_CLKGEN1_TSO_OUT_DIVNUM_MASK 0x001FUL
183 #define REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_MASK 0x1F00UL
184 #define REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_SHIFT 8UL
185
186 #define REG_CLKGEN1_TSO_OUT_CLK 0x25UL
187 #define REG_CLKGEN1_TSO_OUT_DIV_SEL_MASK 0x0001UL
188 // bit[0] -> 0: CLK_DMPLLDIV2
189 // 1: CLK_DMPLLDIV3
190 #define REG_CLKGEN1_TSO_OUT_INV 0x0002UL
191 #define REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE 0x0004UL
192 #define REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK 0x0070UL
193 #define REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT 4UL
194 // bit[6:4] -> 000:CLK_TS0_IN
195 // 001:CLK_TS1_IN
196 // 010:CLK_TS2_IN
197 // 011:CLK_TS3_IN
198 // 100:CLK_TS4_IN
199 // 101:CLK_TS5_IN
200 #define REG_CLKGEN1_TSO_OUT_CLK_MASK 0x1F00UL
201 #define REG_CLKGEN1_TSO_OUT_CLK_DISABLE 0x0100UL
202 #define REG_CLKGEN1_TSO_OUT_CLK_INVERT 0x0200UL
203 // bit[12:8] -> 0: disable clock
204 // 1: invert clock
205 // bit [4:2] -> 000: TSO_OUT_DIV2 (clock/2N+1)
206 // 001: 62MHz
207 // 010: 54MHz
208 // 011: clk_p_tso_out (live in)
209 // 100: clk_p_tso_out_div8 (live in)
210 // 101: 27MHz
211 // 111: clk_demod_ts_p
212 //#define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1400UL + ((addr)<<2UL))))
213 #define REG_CLKGEN1_TSO1_IN 0x23UL
214 #define REG_CLKGEN1_TSO1_IN_MASK 0x001FUL
215 #define REG_CLKGEN1_TSO1_IN_SHIFT 8UL
216 #define REG_CLKGEN1_TSO1_IN_DISABLE 0x0001UL
217 #define REG_CLKGEN1_TSO1_IN_INVERT 0x0002UL
218 // bit[4:0] -> 0: disable clock
219 // 1: invert clock
220 // bit [4:2] -> 000: Sel TS0 Clk
221 // 001: Sel TS1 Clk
222 // 010: Sel TS2 Clk
223 // 011: Sel TS3 Clk
224 // 100: Sel TS4 Clk
225 // 101: Sel TS5 Clk
226 // 111: Sel Dmd Clk
227
228
229 #define TSO_TOP_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x3c00UL + ((addr)<<2UL))))
230 #define REG_TOP_TS_OUT_CFG 0x51UL
231 #define REG_TOP_TS_OUT_MODE_MASK 0x0100UL
232
233 #define REG_TOP_TS_CONFIG 0x51UL
234 #define REG_TOP_TS0_CONFIG_MASK 0x0600UL
235 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0200UL
236 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0400UL
237 #define REG_TOP_TS0_CONFIG_3WIRE_MODE 0x0400UL
238
239 #define REG_TOP_TS1_CONFIG_MASK 0x3800UL
240 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800UL
241 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000UL //out from demod
242 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800UL
243 #define REG_TOP_TS1_CONFIG_3WIRE_MODE 0x1800UL
244
245 #define REG_TOP_TS2_CONFIG 0x54UL
246 #define REG_TOP_TS2_CONFIG_MASK 0x7000UL
247 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x1000UL
248 #define REG_TOP_TS2_CONFIG_SERIAL_IN 0x2000UL
249
250
251 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0xc7600 + ((addr)<<2))))
252 #define REG_TSP5_TSOIN_MUX 0x13UL
253 #define REG_TSP5_TSOIN_MUX_MASK 0x000FUL
254 #define REG_TSP5_TSOIN0_MUX_SHIFT 0UL
255 #define REG_TSP5_TSOIN1_MUX_SHIFT 4UL
256 #define REG_TSP5_TSOIN2_MUX_SHIFT 8UL
257 // bit[14:12] -> 000: PAD_TS0
258 // 001: PAD_TS1
259 // 010: PAD_TS2
260 // 011: PAD_TS3
261 // 100: PAD_TS4
262 // 101: PAD_TS5
263 // 111: DEMOD
264 #define REG_TSP5_TSOOUT_MUX 0x15UL
265 #define REG_TSP5_TSOOUT_MUX_MASK 0x000FUL
266 #define REG_TSP5_TSOOUT_MUX_TSO 0x0000UL
267 #define REG_TSP5_TSOOUT_MUX_S2P0 0x0001UL
268
269 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x21600 + ((addr)<<2))))
270 #define REG_TSO_OUT_CLK_SEL 0x30UL
271 #define REG_TSO_OUT_CLK_SEL_MASK 1UL
272 #define REG_TSO_OUT_TSO 0x0000UL
273 #define REG_TSO_OUT_S2P 0x0001UL
274
275 //--------------------------------------------------------------------------------------------------
276 // Implementation
277 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32 * reg)278 static MS_U32 _HAL_REG32_R(REG32 *reg)
279 {
280 MS_U32 value = 0UL;
281 value = (reg)->H << 16UL;
282 value |= (reg)->L;
283 return value;
284 }
285
_HAL_REG16_R(REG16 * reg)286 static MS_U16 _HAL_REG16_R(REG16 *reg)
287 {
288 MS_U16 value = 0;
289 value = (reg)->data;
290 return value;
291 }
292
_HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)293 static MS_PHY _HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)
294 {
295 #ifdef HAL_MIU2_BASE
296 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
297 return ((MS_PHY)HAL_MIU2_BASE & 0xFFFFFFFFUL);
298 else
299 #endif //HAL_MIU2_BASE
300 #ifdef HAL_MIU1_BASE
301 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
302 return ((MS_PHY)HAL_MIU1_BASE & 0xFFFFFFFFUL);
303 else
304 #endif //HAL_MIU1_BASE
305 return ((MS_PHY)HAL_MIU0_BASE & 0xFFFFFFFFUL);
306 }
307
HAL_TSO_SetBank(MS_VIRT virtBankAddr)308 void HAL_TSO_SetBank(MS_VIRT virtBankAddr)
309 {
310 _virtTSORegBase = virtBankAddr;
311 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO);
312 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1);
313
314 }
315
HAL_TSO_REG32_IndR(REG32 * reg)316 static MS_U32 HAL_TSO_REG32_IndR(REG32 *reg)
317 {
318 MS_U32 u32tmp;
319 MS_VIRT virtReg = (MS_VIRT)reg;
320
321 u32tmp = ((MS_U32)virtReg)>> 1UL;
322
323 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
324 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_R_ENABLE)); // set command
325
326 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value
327
328 return u32tmp;
329 }
330
HAL_TSO_REG32_IndW(REG32 * reg,MS_U32 value)331 static void HAL_TSO_REG32_IndW(REG32 *reg, MS_U32 value)
332 {
333 MS_VIRT virtReg = (MS_VIRT)reg;
334 MS_U32 u32tmp = 0;
335
336 u32tmp = ((MS_U32)virtReg)>> 1;
337
338 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
339 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value
340 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_W_ENABLE)); // set command
341 }
342
343 //
344 // General API
345 //
HAL_TSO_Init(void)346 void HAL_TSO_Init(void)
347 {
348 MS_U8 u8ii = 0;
349
350 //select MIU0, and 128bit MIU bus
351 #if 0
352 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
353 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
354 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
355 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
356 #endif
357
358 for(u8ii = 0; u8ii < (MS_U8)TSO_ENGINE_NUM; u8ii++)
359 {
360 _stOutPadCtrl.u16OutPad[u8ii] = 0;
361 _stOutPadCtrl.u16TSCfgOld[u8ii] = 0;
362 _stOutPadCtrl.u16TSOutModeOld[u8ii] = 0;
363 }
364
365 //reset
366 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
367 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
368 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
369 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
370
371 //default local stream id
372 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER1_CFG0), 0x47);
373 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER5_CFG0), 0x47);
374
375 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | TSO_SVQ_RX_CFG_MODE_CIPL);
376
377 // Set SVQ FIFO timeout value
378 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ1_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ1_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
379 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ5_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ5_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
380
381 //enable eco bit
382 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_TIMESTAMP_RING_BACK | TSO_LPCR_RING_BACK | TSO_INIT_STAMP_RSTART));
383
384 }
385
HAL_TSO_Reset_All(MS_U8 u8Eng)386 void HAL_TSO_Reset_All(MS_U8 u8Eng)
387 {
388 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
389 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
390
391 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
392 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
393 }
394
HAL_TSO_Reset(MS_U8 u8Eng)395 void HAL_TSO_Reset(MS_U8 u8Eng)
396 {
397 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
398 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
399 }
400
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)401 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
402 {
403 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | u16RstItem));
404 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~u16RstItem));
405 }
406
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL bEnable,MS_U16 u16init)407 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL bEnable, MS_U16 u16init)
408 {
409 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt));
410
411 if(bEnable)
412 {
413 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data | u16init));
414 }
415 else
416 {
417 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data & ~u16init));
418 }
419 }
420
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)421 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
422 {
423 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & ~u16Int));
424 }
425
HAL_TSO_HWInt_Status(MS_U8 u8Eng)426 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
427 {
428 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & TSO_INT_STATUS_MASK);
429 }
430
431 #ifdef CONFIG_MSTAR_CLKM
HAL_TSO_PowerCtrl(MS_BOOL bOn)432 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
433 {
434 MS_S32 s32ClkHandle;
435
436 if (bOn)
437 {
438 // Enable TSO Trace Clock
439 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_trace");
440 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSO_TRACE_NORMAL");
441
442 // Enable TSO out Clock
443 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
444 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOOUT_DIV");
445
446 // Enable TSO in Clock
447 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
448 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOIN0_PAD0");
449
450 // Enable TSO1 in Clock
451 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
452 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN1_PAD0");
453
454 // Enable TSO2 in Clock
455 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
456 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN2_PAD0");
457 }
458 else
459 {
460 // Disabel TSO Trace Clock
461 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_trace");
462 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
463
464 // Disabel TSO out Clock
465 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
466 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
467
468 // Disabel TSO in Clock
469 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
470 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
471
472 // Disabel TSO1 in Clock
473 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
474 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
475
476 // Disabel TSO2 in Clock
477 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
478 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
479 }
480 }
481 #else
HAL_TSO_PowerCtrl(MS_BOOL bOn)482 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
483 {
484 if (bOn)
485 {
486 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) &= ~REG_CLKGEN1_TSO_TRACE_MASK;
487 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) &= ~REG_CLKGEN1_TSO_OUT_CLK_MASK;
488 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) &= ~REG_CLKGEN1_TSO_IN_MASK;
489 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN) &= ~REG_CLKGEN1_TSO1_IN_MASK;
490 }
491 else
492 {
493 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) |= REG_CLKGEN1_TSO_OUT_CLK_DISABLE;
494 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) |= REG_CLKGEN1_TSO_TRACE_DISABLE;
495 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) |= REG_CLKGEN1_TSO_IN_DISABLE;
496 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN) |= REG_CLKGEN1_TSO1_IN_DISABLE;
497 }
498 }
499 #endif
500
HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)501 void HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)
502 {
503 if(_stOutPadCtrl.u16OutPad[u8Eng] != HAL_TSOOUT_MUX_TS1)
504 return;
505
506 TSO_TOP_REG(REG_TOP_TS_CONFIG) = (TSO_TOP_REG(REG_TOP_TS_CONFIG) & ~REG_TOP_TS1_CONFIG_MASK) | _stOutPadCtrl.u16TSCfgOld[u8Eng];
507 TSO_TOP_REG(REG_TOP_TS_OUT_CFG) = (TSO_TOP_REG(REG_TOP_TS_OUT_CFG) & ~REG_TOP_TS_OUT_MODE_MASK) | _stOutPadCtrl.u16TSOutModeOld[u8Eng];
508 }
509
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)510 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
511 {
512 if(bSet)
513 {
514 if(*pu16OutPad != HAL_TSOOUT_MUX_TS1)
515 return FALSE;
516
517 _stOutPadCtrl.u16OutPad[u8Eng] = *pu16OutPad;
518 _stOutPadCtrl.u16TSCfgOld[u8Eng] = TSO_TOP_REG(REG_TOP_TS_CONFIG) & REG_TOP_TS1_CONFIG_MASK;
519 _stOutPadCtrl.u16TSOutModeOld[u8Eng] = TSO_TOP_REG(REG_TOP_TS_OUT_CFG) & REG_TOP_TS_OUT_MODE_MASK;
520 TSO_TOP_REG(REG_TOP_TS_CONFIG) = TSO_TOP_REG(REG_TOP_TS_CONFIG) & ~REG_TOP_TS1_CONFIG_MASK;
521 TSO_TOP_REG(REG_TOP_TS_OUT_CFG) = (TSO_TOP_REG(REG_TOP_TS_OUT_CFG) & ~REG_TOP_TS_OUT_MODE_MASK);
522 }
523 else
524 {
525 *pu16OutPad = HAL_TSOOUT_MUX_TS1;
526 }
527 return TRUE;
528 }
529
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)530 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
531 {
532 MS_U16 u16Reg, u16RegMask, u16RegShift;
533 MS_U16 u16MuxReg, u16MuxRegMask;
534 MS_U16 u16data = 0;
535
536 //printf("[%s][%d] u8Eng %d, u8TsIf %d, u16InPadSel %d, bParallel %d\n", __FUNCTION__, __LINE__, (int)u8Eng, (int)u8TsIf, (int)u16InPadSel, (int)bParallel);
537
538 // Set pad mux
539 switch(u8TsIf)
540 {
541 case HAL_TSO_TSIF_LIVE1:
542 u16MuxReg = REG_TSP5_TSOIN_MUX;
543 u16MuxRegMask = REG_TSP5_TSOIN_MUX_MASK;
544 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT;
545 break;
546 case HAL_TSO_TSIF_LIVE2:
547 u16MuxReg = REG_TSP5_TSOIN_MUX;
548 u16MuxRegMask = REG_TSP5_TSOIN_MUX_MASK;
549 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT;
550 break;
551 default:
552 return FALSE;
553 }
554
555 //set pad configure
556 switch(u16InPadSel)
557 {
558 case HAL_TSOIN_MUX_TS0:
559 u16Reg = REG_TOP_TS_CONFIG;
560 u16RegMask = REG_TOP_TS0_CONFIG_MASK;
561 if(bParallel)
562 {
563 u16data = REG_TOP_TS0_CONFIG_PARALLEL_IN;
564 }
565 else
566 {
567 u16data = REG_TOP_TS0_CONFIG_SERIAL_IN;
568 }
569 break;
570 case HAL_TSOIN_MUX_TS1:
571 u16Reg = REG_TOP_TS_CONFIG;
572 u16RegMask = REG_TOP_TS1_CONFIG_MASK;
573 if(bParallel)
574 {
575 u16data = REG_TOP_TS1_CONFIG_PARALLEL_IN;
576 }
577 else
578 {
579 u16data = REG_TOP_TS1_CONFIG_SERIAL_IN;
580 }
581 break;
582 case HAL_TSOIN_MUX_TS2:
583 u16Reg = REG_TOP_TS2_CONFIG;
584 u16RegMask = REG_TOP_TS2_CONFIG_MASK;
585 if(bParallel)
586 {
587 u16data = REG_TOP_TS2_CONFIG_PARALLEL_IN;
588 }
589 else
590 {
591 u16data = REG_TOP_TS2_CONFIG_SERIAL_IN;
592 }
593 break;
594 case HAL_TSOIN_MUX_TSDEMOD0:
595 TSP_TSP5_REG(u16MuxReg) = (TSP_TSP5_REG(u16MuxReg) & ~(u16MuxRegMask << u16RegShift)) | (u16InPadSel << u16RegShift);
596 return TRUE;
597
598 default:
599 return FALSE;
600 }
601
602 TSO_TOP_REG(u16Reg) = (TSO_TOP_REG(u16Reg) & ~u16RegMask) | u16data;
603
604 TSP_TSP5_REG(u16MuxReg) = (TSP_TSP5_REG(u16MuxReg) & ~(u16MuxRegMask << u16RegShift)) | (u16InPadSel << u16RegShift);
605
606 return TRUE;
607 }
608
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)609 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
610 {
611 MS_U16 u16Reg, u16RegMask, u16RegShift;
612 MS_U16 u16value = 0;
613
614 //printf("[%s] u8TsIf %x, u16ClkSel %d\n", __FUNCTION__, (int)u8TsIf, u16ClkSel);
615
616 //set clock
617 switch(u8TsIf)
618 {
619 case HAL_TSO_TSIF_LIVE1:
620 u16Reg = REG_CLKGEN1_TSO_IN;
621 u16RegMask = REG_CLKGEN1_TSO_IN_MASK;
622 u16RegShift = REG_CLKGEN1_TSO_IN_SHIFT;
623 u16value = TSO_CLKGEN1_REG(u16Reg) & ~u16RegMask;
624 break;
625 case HAL_TSO_TSIF_LIVE2:
626 u16Reg = REG_CLKGEN1_TSO1_IN;
627 u16RegMask = REG_CLKGEN1_TSO1_IN_MASK;
628 u16RegShift = REG_CLKGEN1_TSO1_IN_SHIFT;
629 u16value = TSO_CLKGEN1_REG(u16Reg) & ~u16RegMask;
630 break;
631 default:
632 return FALSE;
633 }
634
635 //printf("[%s] u16RegMask %x, u16RegShift %d\n", __FUNCTION__, u16RegMask, u16RegShift);
636
637 if(!bEnable)
638 {
639 u16value |= ((REG_CLKGEN1_TSO1_IN_DISABLE << u16RegShift) & 0xFFFFUL);
640 }
641 else
642 {
643 u16value |= (u16ClkSel << u16RegShift);
644 if(bClkInvert)
645 {
646 u16value |= ((REG_CLKGEN1_TSO1_IN_INVERT << u16RegShift) & 0xFFFFUL);
647 }
648 }
649
650 switch(u8TsIf)
651 {
652 case HAL_TSO_TSIF_LIVE1:
653 TSO_CLKGEN1_REG(u16Reg) = u16value;
654 break;
655 case HAL_TSO_TSIF_LIVE2:
656 TSO_CLKGEN1_REG(u16Reg) = u16value;
657 break;
658 default:
659 return FALSE;
660 }
661
662 return TRUE;
663 }
664
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)665 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
666 {
667 MS_U16 u16Reg, u16RegMask, u16RegShift;
668 MS_U16 u16data = 0;
669 REG16* reg16 = 0;
670
671 // Set pad mux
672 switch(u8TsIf)
673 {
674 case HAL_TSO_TSIF_LIVE1:
675 u16Reg = REG_TSP5_TSOIN_MUX;
676 u16RegMask = REG_TSP5_TSOIN_MUX_MASK;
677 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT;
678 break;
679 case HAL_TSO_TSIF_LIVE2:
680 u16Reg = REG_TSP5_TSOIN_MUX;
681 u16RegMask = REG_TSP5_TSOIN_MUX_MASK;
682 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT;
683 break;
684 default:
685 return FALSE;
686 }
687 *pu16Pad = (TSP_TSP5_REG(u16Reg) & (u16RegMask << u16RegShift)) >> u16RegShift;
688
689 switch(u8TsIf)
690 {
691 case HAL_TSO_TSIF_LIVE1:
692 u16data = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & REG_CLKGEN1_TSO_IN_MASK) >> REG_CLKGEN1_TSO_IN_SHIFT;
693 reg16 = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
694 break;
695 case HAL_TSO_TSIF_LIVE2:
696 u16data = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN) & REG_CLKGEN1_TSO1_IN_MASK) >> REG_CLKGEN1_TSO1_IN_SHIFT;
697 reg16 = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
698 break;
699 default:
700 return FALSE;
701 }
702
703 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
704 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
705 *pbClkInvert = ((u16data & REG_CLKGEN1_TSO1_IN_INVERT) == REG_CLKGEN1_TSO1_IN_INVERT);
706
707 return TRUE;
708
709 }
710
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)711 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
712 {
713 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
714 {
715 return FALSE; //not support yet
716 }
717
718 switch(u16PadSel)
719 {
720 case HAL_TSOIN_MUX_TS0:
721 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
722 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
723 break;
724 case HAL_TSOIN_MUX_TS1:
725 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
726 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
727 break;
728 case HAL_TSOIN_MUX_TS2:
729 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
730 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
731 break;
732 case HAL_TSOIN_MUX_TSDEMOD0:
733 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
734 break;
735 case HAL_TSOIN_MUX_MEM:
736 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV2N;
737 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
738 pstOutClkSet->u16OutDivNum = 0x0F; //default: 172.8/2(15+1) = 5.4M
739 break;
740 default:
741 return FALSE;
742 }
743
744 return TRUE;
745 }
746
747 // default: dmplldiv5 / 2 (11+1) = 7.2 MHz
748 // default: dmplldiv_3 / 2 (17+1) = 8 MHz
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)749 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
750 {
751 if(bSet == TRUE)
752 {
753 if(pstOutClkSet->bEnable == FALSE)
754 {
755 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
756 return;
757 }
758
759 switch(pstOutClkSet->u16OutClk)
760 {
761 case HAL_TSO_OUT_SEL_TSO_OUT_DIV2N:
762 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
763 break;
764 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
765 case HAL_TSO_OUT_SEL_TSO_OUT_54MHz:
766 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
767 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
768 break;
769 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
770 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
771 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
772 break;
773 default:
774 return;
775 }
776
777 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
778 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //alyays need TSO out clock
779 }
780 else
781 {
782 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
783 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV2N)
784 {
785 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
786 }
787 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
788 {
789 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
790 }
791 }
792 }
793
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)794 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
795 {
796 MS_U16 u16value = 0;
797
798 if(!bPhaseEnable)
799 {
800 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) &= ~REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE;
801 }
802 else
803 {
804 u16value = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & ~REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_MASK)
805 | (u16ClkOutPhase << REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_SHIFT);
806
807 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) = u16value;
808 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) |= REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE;
809 }
810
811 return TRUE;
812 }
813
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)814 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
815 {
816 if(bSet == TRUE)
817 {
818 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS2IN)
819 {
820 return FALSE;
821 }
822
823 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) =
824 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSel << REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT);
825 }
826 else
827 {
828 *pu16PreTsoOutSel = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) >> REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT;
829 }
830
831 return TRUE;
832 }
833
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)834 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16* pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
835 {
836 //clock source for clock divide
837 if(bSet == TRUE)
838 {
839 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) =
840 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & ~REG_CLKGEN1_TSO_TRACE_MASK) | REG_CLKGEN1_TSO_TRACE_216M;
841
842 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) =
843 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
844
845 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) =
846 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & ~REG_CLKGEN1_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum);
847 }
848 else
849 {
850 *pu16ClkOutDivSrcSel = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_DIV_SEL_MASK;
851 *pu16ClkOutDivNum = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & REG_CLKGEN1_TSO_OUT_DIVNUM_MASK;
852 }
853
854 return TRUE;
855 }
856
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)857 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
858 {
859 MS_U16 u16Clk = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_CLK_MASK;
860
861 if(bSet == TRUE)
862 {
863 if(*pbEnable == FALSE)
864 {
865 u16Clk |= REG_CLKGEN1_TSO_OUT_CLK_DISABLE;
866 }
867 else
868 {
869 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) =
870 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & ~REG_CLKGEN1_TSO_TRACE_MASK) | REG_CLKGEN1_TSO_TRACE_216M;
871
872 u16Clk |= (*pu16ClkOutSel);
873
874 if(*pbClkInvert)
875 u16Clk |= REG_CLKGEN1_TSO_OUT_CLK_INVERT;
876
877 }
878 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) = u16Clk;
879 }
880 else
881 {
882 *pbEnable = ((u16Clk & REG_CLKGEN1_TSO_OUT_CLK_DISABLE) == 0);
883 *pbClkInvert = ((u16Clk & REG_CLKGEN1_TSO_OUT_CLK_INVERT) == REG_CLKGEN1_TSO_OUT_CLK_INVERT);
884 *pu16ClkOutSel = u16Clk;
885 }
886
887 return TRUE;
888 }
889
890 // ------------------------------------------------------
891 // APIS
892 //-------------------------------------------------------
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)893 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
894 {
895 MS_U32 u32value;
896 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
897
898 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_PID_MASK) | (((MS_U32)u16PID << TSO_PIDFLT_PID_SHFT) & TSO_PIDFLT_PID_MASK);
899 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
900 }
901
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)902 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
903 {
904 MS_U32 u32value;
905 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
906
907 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_IN_MASK) | (u16InputSrc << TSO_PIDFLT_IN_SHIFT);
908 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
909 }
910
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)911 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
912 {
913 MS_U16 u32data = (((MS_U32)u16OldPid) & REP_PIDFLT_ORG_PID_MASK) | (((MS_U32)u8TsIf) << REP_PIDFLT_SRC_SHIFT) |
914 ((((MS_U32)u16NewPid) << REP_PIDFLT_NEW_PID_SHIFT) & REP_PIDFLT_NEW_PID_MASK);
915
916 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), u32data);
917
918 return TRUE;
919 }
920
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)921 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
922 {
923 if(bEnable)
924 {
925 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), SET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
926 }
927 else
928 {
929 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
930 }
931
932 return TRUE;
933 }
934
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_PHY phyAddr)935 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_PHY phyAddr)
936 {
937 _phyTSOFiMiuOffset[u8FileEng] = _HAL_TSO_MIU_OFFSET(phyAddr);
938
939 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_raddr), (MS_U32)(phyAddr-_phyTSOFiMiuOffset[u8FileEng]));
940 }
941
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)942 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
943 {
944 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_rNum), u32len);
945 }
946
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)947 MS_PHY HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
948 {
949 MS_PHY phyvalue = 0;
950
951 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_RADDR_READ);
952 phyvalue = ((MS_PHY)_HAL_REG32_R(&(_TSOCtrl->TSO_TSO2MI_RADDR[u8FileEng])) & 0xFFFFFFFFUL) << TSO_MIU_BUS;
953 phyvalue += _phyTSOFiMiuOffset[u8FileEng];
954 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_RADDR_READ);
955 return phyvalue;
956 }
957
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)958 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
959 {
960 _HAL_REG16_W(&(_TSOCtrl->TSO_Filein_Ctrl), (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
961 }
962
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)963 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
964 {
965 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & TSO_FILEIN_CTRL_MASK);
966 return 0;
967 }
968
HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng,MS_U32 u32Key,MS_BOOL bSecured)969 MS_BOOL HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng, MS_U32 u32Key, MS_BOOL bSecured)
970 {
971 MS_U16 u16data = (bSecured ? TSO_FILEIN_RIU_TSO_NS : 0);
972 REG16* pReg = &(_TSOCtrl->TSO_Filein_Ctrl);
973
974 if((_HAL_REG16_R(pReg) & (TSO_FILEIN_RSTART|TSO_FILEIN_ABORT)) != 0)
975 {
976 return FALSE;
977 }
978
979 u16data |= ((MS_U16)(u32Key << TSO_FILEIN_MOBF_IDX_SHIFT) & TSO_FILEIN_MOBF_IDX_MASK);
980 _HAL_REG16_W(pReg, u16data)
981
982 return TRUE;
983 }
984
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)985 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
986 {
987 if(bEnable)
988 {
989 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), TSO_CFG1_TSO_TSIF5_EN));
990 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
991 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
992 }
993 else
994 {
995 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), TSO_CFG1_TSO_TSIF5_EN));
996 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
997 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
998 }
999
1000 return TRUE;
1001 }
1002
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1003 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1004 {
1005 if(bEnable)
1006 {
1007 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_TIMER_ENABLE);
1008 }
1009 else
1010 {
1011 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_TIMER_ENABLE);
1012 }
1013 }
1014
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1015 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1016 {
1017 _HAL_REG16_W(&(_TSOCtrl->TSO_FI_TIMER[u8FileEng]), u16timer);
1018 }
1019
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1020 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1021 {
1022 if(bEnable)
1023 {
1024 //init timestamp
1025 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_INIT_TIMESTAMP));
1026 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_INIT_TIMESTAMP));
1027
1028 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
1029 }
1030 else
1031 {
1032 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1033 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
1034 }
1035 }
1036
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1037 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1038 {
1039 if(bEnable)
1040 {
1041 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1042 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
1043 }
1044 else
1045 {
1046 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1047 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
1048 }
1049 }
1050
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1051 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1052 {
1053 return (_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) & TSO_CMDQ_STS_WCNT_MASK);
1054 }
1055
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng,MS_U8 u8FileEng)1056 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng, MS_U8 u8FileEng)
1057 {
1058 return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) & TSO_CMDQ_STS_FIFO_FULL);
1059 }
1060
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng,MS_U8 u8FileEng)1061 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng, MS_U8 u8FileEng)
1062 {
1063 return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) & TSO_CMDQ_STS_FIFO_EMPTY);
1064 }
1065
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1066 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1067 {
1068 return (MS_U8)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CMDQ_STATUS)) & TSO_CMDQ_STS_WLEVEL_MASK);
1069 }
1070
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1071 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1072 {
1073 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), TSO_SW_RSTZ_CMDQ));
1074 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), TSO_SW_RSTZ_CMDQ));
1075
1076 return TRUE;
1077 }
1078
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1079 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1080 {
1081 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1082
1083 if(bWrite)
1084 {
1085 u16data &= ~TSO_CFG2_VALID_BYTECNT_MASK;
1086 u16data |= (*pu16ValidBlockCnt << TSO_CFG2_VALID_BYTECNT_SHIFT);
1087 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1088
1089 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1090 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1091 }
1092 else
1093 {
1094 *pu16ValidBlockCnt = (u16data & TSO_CFG2_VALID_BYTECNT_MASK) >> TSO_CFG2_VALID_BYTECNT_SHIFT;
1095 }
1096 }
1097
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1098 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1099 {
1100 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1101
1102 if(bWrite)
1103 {
1104 u16data &= ~TSO_CFG2_INVALID_BYTECNT_MASK;
1105 u16data |= (*pu16InvalidBlockCnt << TSO_CFG2_INVALID_BYTECNT_SHIFT);
1106 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1107
1108 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1109 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1110 }
1111 else
1112 {
1113 *pu16InvalidBlockCnt = u16data & TSO_CFG2_INVALID_BYTECNT_MASK;
1114 }
1115 }
1116
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1117 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1118 {
1119 if(bWrite)
1120 {
1121 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG3), *pu16PktSize);
1122 }
1123 else
1124 {
1125 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG3));
1126 }
1127
1128 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1129 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1130 }
1131
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1132 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1133 {
1134 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1135
1136 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp | TSO_FICFG_LPCR2_WLD);
1137 _HAL_REG32_W(&(_TSOCtrl->TSO_LPCR2[u8FileEng]), u32lpcr2);
1138 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1139 }
1140
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1141 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1142 {
1143 MS_U32 u32temp = 0;
1144 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1145
1146 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), ((u16temp & ~TSO_FICFG_LPCR2_WLD)|TSO_FICFG_LPCR2_LD));
1147 u32temp = _HAL_REG32_R(&_TSOCtrl->TSO_LPCR2[u8FileEng]);
1148 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1149
1150 return u32temp;
1151 }
1152
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1153 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1154 {
1155 return _HAL_REG32_R(&(_TSOCtrl->TSO_TIMESTAMP[u8FileEng]));
1156 }
1157
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1158 MS_BOOL HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1159 {
1160 MS_U16 u16data = 0;
1161
1162 if(u8If == HAL_TSO_TSIF_LIVE1)
1163 {
1164 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF1_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1165 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF1_CFG0), u16data | (MS_U16)u8size);
1166 }
1167 else if((u8If == HAL_TSO_TSIF_LIVE2) || (u8If == HAL_TSO_TSIF_FILE1))
1168 {
1169 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF5_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1170 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF5_CFG0), u16data | (MS_U16)u8size);
1171 }
1172 else
1173 {
1174 return FALSE;
1175 }
1176
1177 return TRUE;
1178 }
1179
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1180 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1181 {
1182 MS_U16 u16temp = 0;
1183
1184 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI)) & ~(TSO_PKT_CHKSIZE_FI_MASK);
1185 u16temp |= ((MS_U16)(u8size & 0xFF));
1186
1187 _HAL_REG16_W(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI), u16temp);
1188 }
1189
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1190 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1191 {
1192 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG1));
1193
1194 if(bEnable)
1195 {
1196 u16data |= u16CfgItem;
1197 }
1198 else
1199 {
1200 u16data &= ~u16CfgItem;
1201 }
1202
1203 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), u16data);
1204 }
1205
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1206 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1207 {
1208 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG4));
1209
1210 if(bEnable)
1211 {
1212 u16data |= u16CfgItem;
1213 }
1214 else
1215 {
1216 u16data &= ~u16CfgItem;
1217 }
1218
1219 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4), u16data);
1220 }
1221
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1222 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1223 {
1224 MS_U16 u16data = 0;
1225 REG16* pReg = &(_TSOCtrl->TSO_CFG1);
1226
1227 if(u8Eng > 0)
1228 {
1229 return FALSE;
1230 }
1231
1232 switch(u8ChIf)
1233 {
1234 case HAL_TSO_TSIF_LIVE1:
1235 u16data = TSO_CFG1_TSO_TSIF1_EN;
1236 break;
1237 case HAL_TSO_TSIF_LIVE2:
1238 u16data = TSO_CFG1_TSO_TSIF5_EN;
1239 break;
1240 default:
1241 return FALSE;
1242 }
1243
1244 if(bEnable)
1245 {
1246 _HAL_REG16_W(pReg, SET_FLAG1(_HAL_REG16_R(pReg), u16data));
1247 }
1248 else
1249 {
1250 _HAL_REG16_W(pReg, RESET_FLAG1(_HAL_REG16_R(pReg), u16data));
1251 }
1252
1253 return TRUE;
1254
1255 }
1256
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1257 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1258 {
1259 REG16* pReg = NULL;
1260
1261 if(u8Eng > 0)
1262 {
1263 return FALSE;
1264 }
1265
1266 switch(u8ChIf)
1267 {
1268 case HAL_TSO_TSIF_LIVE1:
1269 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1270 break;
1271 case HAL_TSO_TSIF_LIVE2:
1272 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1273 break;
1274 default:
1275 return FALSE;
1276 }
1277
1278 if(bEnable)
1279 {
1280 _HAL_REG16_W(pReg, SET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1281 }
1282 else
1283 {
1284 _HAL_REG16_W(pReg, RESET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1285 }
1286
1287 return TRUE;
1288 }
1289
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1290 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1291 {
1292 REG16* pReg = NULL;
1293 MS_U16 u16data = 0;
1294
1295 *pu16Cfg = 0;
1296 *pbEnable = FALSE;
1297
1298 if(u8Eng > 0)
1299 {
1300 return FALSE;
1301 }
1302
1303 switch(u8ChIf)
1304 {
1305 case HAL_TSO_TSIF_LIVE1:
1306 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1307 break;
1308 case HAL_TSO_TSIF_LIVE2:
1309 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1310 break;
1311 default:
1312 return FALSE;
1313 }
1314
1315 *pu16Cfg = _HAL_REG16_R(pReg);
1316
1317 switch(u8ChIf)
1318 {
1319 case HAL_TSO_TSIF_LIVE1:
1320 u16data = TSO_CFG1_TSO_TSIF1_EN;
1321 break;
1322 case HAL_TSO_TSIF_LIVE2:
1323 u16data = TSO_CFG1_TSO_TSIF5_EN;
1324 break;
1325 default:
1326 return FALSE;
1327 }
1328
1329 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)) & u16data) == u16data);
1330
1331 return TRUE;
1332
1333 }
1334
1335
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1336 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1337 {
1338 REG32* p32Reg = NULL;
1339 REG16* p16Reg = NULL;
1340 REG16* p16RegCfg = NULL;
1341 MS_U32 u32addr = 0;
1342
1343 _phyTSOVQiMiuOffset = _HAL_TSO_MIU_OFFSET(phyBufAddr);
1344 u32addr = (MS_U32)(phyBufAddr - _phyTSOVQiMiuOffset);
1345
1346 if(u8Eng > 0)
1347 {
1348 return FALSE;
1349 }
1350
1351 switch(u8ChIf)
1352 {
1353 case HAL_TSO_TSIF_LIVE1:
1354 p32Reg = &(_TSOCtrl1->TSO_SVQ1_BASE);
1355 p16Reg = &(_TSOCtrl1->TSO_SVQ1_SIZE);
1356 p16RegCfg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1357 break;
1358 case HAL_TSO_TSIF_LIVE2:
1359 p32Reg = &(_TSOCtrl1->TSO_SVQ5_BASE);
1360 p16Reg = &(_TSOCtrl1->TSO_SVQ5_SIZE);
1361 p16RegCfg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1362 break;
1363 default:
1364 return FALSE;
1365 }
1366
1367 _HAL_REG32_W(p32Reg, u32addr >> TSO_MIU_BUS);
1368 _HAL_REG16_W(p16Reg , u32BufSize/TSO_SVQ_UNIT_SIZE);
1369
1370 // Reset SVQ
1371 _HAL_REG16_W(p16RegCfg , SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1372 _HAL_REG16_W(p16RegCfg , RESET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1373
1374 _HAL_REG16_W(p16RegCfg, SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_SVQ_EN));
1375
1376 return TRUE;
1377 }
1378
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1379 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1380 {
1381 MS_U16 u16data = 0;
1382
1383 switch(u8ChIf)
1384 {
1385 case HAL_TSO_TSIF_LIVE1:
1386 u16data = TSO_CLR_BYTE_CNT_1;
1387 break;
1388 case HAL_TSO_TSIF_LIVE2:
1389 u16data = TSO_CLR_BYTE_CNT_5;
1390 break;
1391 default:
1392 return FALSE;
1393 }
1394
1395
1396 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1397 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1398
1399 return TRUE;
1400 }
1401
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1402 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1403 {
1404 REG16* p16Reg = NULL;
1405
1406 if(beSet == FALSE)
1407 {
1408 *pu8StrID = 0xFF;
1409 }
1410
1411 if(u8Eng > 0)
1412 {
1413 return FALSE;
1414 }
1415
1416 switch(u8ChIf)
1417 {
1418 case HAL_TSO_TSIF_LIVE1:
1419 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER1_CFG0);
1420 break;
1421 case HAL_TSO_TSIF_LIVE2:
1422 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER5_CFG0);
1423 break;
1424 default:
1425 return FALSE;
1426 }
1427
1428 if(beSet == TRUE)
1429 {
1430 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & 0xFF);
1431 }
1432 else
1433 {
1434 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & 0xFF);
1435 }
1436
1437 return TRUE;
1438
1439 }
1440
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1441 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1442 {
1443 REG16* p16Reg = NULL;
1444
1445 if(u8Eng > 0)
1446 {
1447 return FALSE;
1448 }
1449
1450 switch(u8ChIf)
1451 {
1452 case HAL_TSO_TSIF_LIVE1:
1453 p16Reg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1454 break;
1455 case HAL_TSO_TSIF_LIVE2:
1456 p16Reg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1457 break;
1458 default:
1459 return FALSE;
1460 }
1461
1462 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1463 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1464
1465 return TRUE;
1466
1467 }
1468
HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng,MS_U32 u32Key,MS_BOOL bSecured)1469 MS_BOOL HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng, MS_U32 u32Key, MS_BOOL bSecured)
1470 {
1471 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK;
1472
1473 u16data |= ((MS_U16)(u32Key << TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT) & TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK);
1474
1475 if(bSecured)
1476 {
1477 u16data |= TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1478 }
1479 else
1480 {
1481 u16data &= ~TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1482 }
1483
1484 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), u16data);
1485
1486 return TRUE;
1487 }
1488
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1489 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1490 {
1491 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | u16mode);
1492
1493 return TRUE;
1494 }
1495
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1496 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1497 {
1498 MS_U8 u8ii = 0, u8jj = 0;
1499 MS_U16 u16shift = 0;
1500
1501 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_ARBMODE_MASK) | u16mode);
1502
1503 if(u16mode != TSO_SVQ_RX_CFG_ARBMODE_FIXPRI)
1504 {
1505 return TRUE;
1506 }
1507
1508 for(u8ii = 0; u8ii < TSO_SVQ_RX_NUM; u8ii++)
1509 {
1510 u8jj = u8ii >> 1;
1511 u16shift = ((u8ii % 2) ? TSO_SVQ_RX_PRI_SHIFT: 0);
1512
1513 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj]),
1514 (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj])) & ~(TSO_SVQ_RX_PRI_MASK << u16shift)) | (pu16SvqRxPri[u8ii] << u16shift));
1515 }
1516
1517 return TRUE;
1518 }
1519
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1520 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1521 {
1522 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1523 _HAL_REG32_W(&(_TSOCtrl->TSO_SYSTIMESTAMP), u32systime);
1524 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1525
1526 return FALSE;
1527 }
1528
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1529 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1530 {
1531 MS_U32 u32data = 0;
1532 MS_U32 u32Shift = 0;
1533
1534 *pu16Status = 0;
1535
1536 if(u8Eng > 0)
1537 {
1538 return FALSE;
1539 }
1540
1541 u32data = _HAL_REG32_R(&(_TSOCtrl1->TSO_SVQ_STATUS));
1542
1543 switch(u8ChIf)
1544 {
1545 case HAL_TSO_TSIF_LIVE1:
1546 u32Shift = 0;
1547 break;
1548 case HAL_TSO_TSIF_LIVE2:
1549 u32Shift = 16;
1550 break;
1551 default:
1552 return FALSE;
1553 }
1554
1555 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1556
1557 return TRUE;
1558
1559 }
1560
HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U32 * pu32time)1561 MS_BOOL HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U32 *pu32time)
1562 {
1563 *pu32time = 0;
1564
1565 if(u8Eng > 0)
1566 {
1567 return FALSE;
1568 }
1569
1570 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1571 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1572
1573 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) ,
1574 (_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & ~TSO_DELTA_CFG_SEL_CH_MASK) | u8ChIf);
1575
1576 *pu32time = _HAL_REG32_R(&(_TSOCtrl1->TSO_DELTA));
1577
1578 return TRUE;
1579 }
1580
HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng,MS_U8 * pu8ChIf)1581 MS_BOOL HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng, MS_U8 *pu8ChIf)
1582 {
1583 *pu8ChIf = 0xFF;
1584
1585 *pu8ChIf = (MS_U8)((_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & TSO_DELTA_CFG_MAX_ID_MASK) >> TSO_DELTA_CFG_MAX_ID_SHIFT);
1586
1587 return TRUE;
1588 }
1589
HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng,MS_U16 u16ClkBase)1590 MS_BOOL HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng, MS_U16 u16ClkBase)
1591 {
1592 if(u16ClkBase == HAL_TSO_TIMESTAMP_27M)
1593 {
1594 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_27M));
1595 }
1596 else
1597 {
1598 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_BASE_MASK));
1599 }
1600
1601 return TRUE;
1602 }
1603
1604
HAL_TSO_ChIf_Ng_Protocol_ID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16ID)1605 MS_BOOL HAL_TSO_ChIf_Ng_Protocol_ID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16ID)
1606 {
1607 REG32* p32Reg = NULL;
1608
1609 switch(u8ChIf)
1610 {
1611 case HAL_TSO_TSIF_LIVE1:
1612 p32Reg = &(_TSOCtrl1->TSO_DONGLE_TSIF1);
1613 break;
1614 case HAL_TSO_TSIF_LIVE2:
1615 p32Reg = &(_TSOCtrl1->TSO_DONGLE_TSIF5);
1616 break;
1617 default:
1618 return FALSE;
1619 }
1620 _HAL_REG32_W(p32Reg, (_HAL_REG32_R(p32Reg) & ~TSO_DONGLE_PROTOCAL_ID_MASK) | (u16ID<<TSO_DONGLE_PROTOCAL_ID_SHIFT));
1621
1622 return TRUE;
1623 }
1624
HAL_TSO_ChIf_Ng_Stream_ID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16ID)1625 MS_BOOL HAL_TSO_ChIf_Ng_Stream_ID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16ID)
1626 {
1627 REG32* p32Reg = NULL;
1628
1629 switch(u8ChIf)
1630 {
1631 case HAL_TSO_TSIF_LIVE1:
1632 p32Reg = &(_TSOCtrl1->TSO_DONGLE_TSIF1);
1633 break;
1634 case HAL_TSO_TSIF_LIVE2:
1635 p32Reg = &(_TSOCtrl1->TSO_DONGLE_TSIF5);
1636 break;
1637 default:
1638 return FALSE;
1639 }
1640 _HAL_REG32_W(p32Reg, (_HAL_REG32_R(p32Reg) & ~TSO_DONGLE_STREAM_ID_MASK) | (u16ID<<TSO_DONGLE_STREAM_ID_SHIFT));
1641 return TRUE;
1642 }
1643
1644
1645 #ifdef MSOS_TYPE_LINUX_KERNEL
1646
HAL_TSO_SaveRegs(void)1647 MS_BOOL HAL_TSO_SaveRegs(void)
1648 {
1649 MS_U32 u32ii = 0;
1650
1651 _u16TSORegArray[0][0x04] = TSO0_REG(0x04);
1652 _u16TSORegArray[0][0x05] = TSO0_REG(0x05);
1653 _u16TSORegArray[0][0x06] = TSO0_REG(0x06);
1654
1655 _u16TSORegArray[0][0x14] = TSO0_REG(0x14);
1656 _u16TSORegArray[0][0x15] = TSO0_REG(0x15);
1657 _u16TSORegArray[0][0x16] = TSO0_REG(0x16);
1658
1659 _u16TSORegArray[0][0x18] = TSO0_REG(0x18);
1660 _u16TSORegArray[0][0x19] = TSO0_REG(0x19);
1661 _u16TSORegArray[0][0x1a] = TSO0_REG(0x1a);
1662
1663 for(u32ii = 0x1c; u32ii <= 0x44; u32ii++)
1664 {
1665 _u16TSORegArray[0][u32ii] = TSO0_REG(u32ii);
1666 }
1667
1668 _u16TSORegArray[0][0x4c] = TSO0_REG(0x4c);
1669 _u16TSORegArray[0][0x4d] = TSO0_REG(0x4d);
1670
1671 for(u32ii = 0x60; u32ii <= 0x6f; u32ii++)
1672 {
1673 _u16TSORegArray[0][u32ii] = TSO0_REG(u32ii);
1674 }
1675
1676 _u16TSORegArray[0][0x79] = TSO0_REG(0x79);
1677 _u16TSORegArray[0][0x7a] = TSO0_REG(0x7a);
1678 _u16TSORegArray[0][0x7b] = TSO0_REG(0x7b);
1679 _u16TSORegArray[0][0x7c] = TSO0_REG(0x7c);
1680
1681 //TSO1
1682 _u16TSORegArray[1][0x00] = TSO1_REG(0x00);
1683 _u16TSORegArray[1][0x10] = TSO1_REG(0x10);
1684 _u16TSORegArray[1][0x14] = TSO1_REG(0x14);
1685
1686 for(u32ii = 0x18; u32ii <= 0x1b; u32ii++)
1687 {
1688 _u16TSORegArray[1][u32ii] = TSO1_REG(u32ii);
1689 }
1690
1691 for(u32ii = 0x28; u32ii <= 0x33; u32ii++)
1692 {
1693 _u16TSORegArray[1][u32ii] = TSO1_REG(u32ii);
1694 }
1695
1696 _u16TSOTopReg[0][0] = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN);
1697 _u16TSOTopReg[0][1] = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE);
1698 _u16TSOTopReg[0][2] = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK);
1699 _u16TSOTopReg[0][3] = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN);
1700 _u16TSOTopReg[0][4] = TSP_TS_SAMPLE_REG(REG_TSO_OUT_CLK_SEL);
1701
1702 _u16TSOTopReg[1][1] = TSO_TOP_REG(REG_TOP_TS_OUT_CFG);
1703 _u16TSOTopReg[1][2] = TSO_TOP_REG(REG_TOP_TS_CONFIG);
1704 _u16TSOTopReg[1][3] = TSO_TOP_REG(REG_TOP_TS2_CONFIG);
1705
1706 _u16TSOTopReg[2][0] = TSP_TSP5_REG(REG_TSP5_TSOIN_MUX);
1707 _u16TSOTopReg[2][1] = TSP_TSP5_REG(REG_TSP5_TSOOUT_MUX);
1708
1709 return TRUE;
1710 }
1711
HAL_TSO_RestoreRegs(void)1712 MS_BOOL HAL_TSO_RestoreRegs(void)
1713 {
1714 MS_U32 u32ii = 0, u32jj, u32temp = 0;
1715
1716
1717 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) = _u16TSOTopReg[0][0];
1718 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) = _u16TSOTopReg[0][1];
1719 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) = _u16TSOTopReg[0][2];
1720 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN) = _u16TSOTopReg[0][3];
1721 TSP_TS_SAMPLE_REG(REG_TSO_OUT_CLK_SEL) = _u16TSOTopReg[0][4];
1722
1723 TSO_TOP_REG(REG_TOP_TS_OUT_CFG) = _u16TSOTopReg[1][1];
1724 TSO_TOP_REG(REG_TOP_TS_CONFIG) = _u16TSOTopReg[1][2] ;
1725 TSO_TOP_REG(REG_TOP_TS2_CONFIG) = _u16TSOTopReg[1][3];
1726
1727 TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) = _u16TSOTopReg[2][0];
1728 TSP_TSP5_REG(REG_TSP5_TSOOUT_MUX) = _u16TSOTopReg[2][1];
1729
1730 TSO0_REG(0x04) = _u16TSORegArray[0][0x04];
1731 TSO0_REG(0x05) = _u16TSORegArray[0][0x05];
1732 TSO0_REG(0x06) = _u16TSORegArray[0][0x06];
1733
1734 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1735 {
1736 TSO0_REG(u32temp+0x14) = _u16TSORegArray[0][u32temp+0x14];
1737 TSO0_REG(u32temp+0x15) = _u16TSORegArray[0][u32temp+0x15];
1738 TSO0_REG(u32temp+0x16) = _u16TSORegArray[0][u32temp+0x16];
1739 u32temp += 4;
1740 }
1741
1742 for(u32ii = 0x1c; u32ii <= 0x3f; u32ii++)
1743 {
1744 TSO0_REG(u32ii) = _u16TSORegArray[0][u32ii];
1745 }
1746
1747 TSO0_REG(0x43) = _u16TSORegArray[0][0x43] & ~0x0004;
1748 TSO0_REG(0x44) = _u16TSORegArray[0][0x44];
1749
1750 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1751 {
1752 TSO0_REG(u32ii+0x4c) = _u16TSORegArray[0][u32ii+0x4c];
1753 }
1754
1755 u32temp = 0;
1756 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1757 {
1758 TSO0_REG(u32temp+0x60) = _u16TSORegArray[0][u32temp+0x60];
1759 TSO0_REG(u32temp+0x61) = _u16TSORegArray[0][u32temp+0x61];
1760 TSO0_REG(u32temp+0x62) = _u16TSORegArray[0][u32temp+0x62];
1761 TSO0_REG(u32temp+0x63) = _u16TSORegArray[0][u32temp+0x63];
1762 u32temp += 5;
1763 }
1764
1765 TSO0_REG(0x6a) = _u16TSORegArray[0][0x6a];
1766 TSO0_REG(0x6b) = _u16TSORegArray[0][0x6b];
1767
1768 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1769 {
1770 TSO0_REG(u32ii+0x79) = _u16TSORegArray[0][u32ii+0x79];
1771 }
1772 TSO0_REG(0x7b) = _u16TSORegArray[0][0x7b];
1773 TSO0_REG(0x7c) = _u16TSORegArray[0][0x7c];
1774
1775 //TSO1
1776 TSO1_REG(0x00) = _u16TSORegArray[1][0x00];
1777
1778 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1779 {
1780 TSO1_REG(u32temp+0x10) = _u16TSORegArray[1][u32temp+0x10];
1781 u32temp += 4;
1782 }
1783
1784 TSO1_REG(0x18) = _u16TSORegArray[1][0x18];
1785 TSO1_REG(0x19) = _u16TSORegArray[1][0x19];
1786 TSO1_REG(0x1a) = _u16TSORegArray[1][0x1a];
1787 TSO1_REG(0x1b) = _u16TSORegArray[1][0x1b] & ~TSO_SVQ_TX_CFG_SVQ_EN; //disable SVQ fisr
1788
1789 u32temp =0;
1790 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1791 {
1792 TSO1_REG(u32temp+0x28) = _u16TSORegArray[1][u32temp+0x28];
1793 TSO1_REG(u32temp+0x29) = _u16TSORegArray[1][u32temp+0x29];
1794 TSO1_REG(u32temp+0x2a) = _u16TSORegArray[1][u32temp+0x2a];
1795 TSO1_REG(u32temp+0x2b) = _u16TSORegArray[1][u32temp+0x2b] & ~TSO_SVQ_TX_CFG_SVQ_EN; //disable SVQ first
1796 u32temp += 4;
1797 }
1798 for(u32ii = 0x30; u32ii <= 0x33; u32ii++)
1799 {
1800 TSO1_REG(u32ii) = _u16TSORegArray[1][u32ii];
1801 }
1802
1803 //enable SVQ
1804 if(_u16TSORegArray[1][0x1b] & TSO_SVQ_TX_CFG_SVQ_EN)
1805 {
1806 TSO1_REG(0x1b) |= TSO_SVQ_TX_CFG_TX_RESET;
1807 TSO1_REG(0x1b) &= ~TSO_SVQ_TX_CFG_TX_RESET;
1808 TSO1_REG(0x2b) |= TSO_SVQ_TX_CFG_TX_RESET;
1809 TSO1_REG(0x2b) &= ~TSO_SVQ_TX_CFG_TX_RESET;
1810 TSO1_REG(0x2f) |= TSO_SVQ_TX_CFG_TX_RESET;
1811 TSO1_REG(0x2f) &= ~TSO_SVQ_TX_CFG_TX_RESET;
1812
1813 TSO1_REG(0x1b) |= TSO_SVQ_TX_CFG_SVQ_EN;
1814 }
1815
1816 if(_u16TSORegArray[0][0x43] & 0x0004)
1817 {
1818 TSO0_REG(0x43) |= 0x0004;
1819 TSO0_REG(0x43) &= ~0x0004;
1820 }
1821
1822 //enable TSO setting
1823 TSO0_REG(0x1d) |= TSO_CFG1_PKT_PARAM_LD;
1824 TSO0_REG(0x1d) &= ~TSO_CFG1_PKT_PARAM_LD;
1825
1826 //set lpcr2, TSO file in start
1827 u32temp = 0;
1828 u32jj = 0;
1829 for(u32ii = 0; u32ii < TSO_FILE_IF_NUM; u32ii++)
1830 {
1831 if(_u16TSORegArray[0][u32temp+0x64] & 0x0003)
1832 {
1833 TSO0_REG(u32ii+0x79) = _u16TSORegArray[0][u32ii+0x79] | TSO_FICFG_LPCR2_WLD;
1834 TSO0_REG(u32jj+0x6c) = _u16TSORegArray[0][u32jj+0x6c];
1835 TSO0_REG(u32jj+0x6d) = _u16TSORegArray[0][u32jj+0x6d];
1836 TSO0_REG(u32ii+0x79) = _u16TSORegArray[0][u32ii+0x79] & ~TSO_FICFG_LPCR2_WLD;
1837 TSO0_REG(u32temp+0x64) = _u16TSORegArray[0][u32temp+0x64];
1838 }
1839 u32temp += 5;
1840 u32jj += 2;
1841 }
1842
1843 return TRUE;
1844 }
1845
1846 #endif //MSOS_TYPE_LINUX_KERNEL
1847
1848
1849