Lines Matching refs:_TSOCtrl
44 static REG_Ctrl_TSO* _TSOCtrl = NULL; variable
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706 in HAL_TSO_SetBank()
244 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH); in HAL_TSO_Init()
250 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
251 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ); in HAL_TSO_Reset_All()
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
254 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
268 … _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem)); in HAL_TSO_Reset_SubItem()
269 …_HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem)); in HAL_TSO_Reset_SubItem()
274 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Enable()
289 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Clear()
296 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1); in HAL_TSO_HWInt_Status()
423 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
427 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
431 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
435 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
439 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
443 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
893 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
902 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
951 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW_withSid()
952 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW_withSid()
955 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW_withSid()
956 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F)); in _HAL_TSO_PageTableIndW_withSid()
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW_withSid()
965 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndW()
966 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndW()
969 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata); in _HAL_TSO_PageTableIndW()
970 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000); in _HAL_TSO_PageTableIndW()
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN); in _HAL_TSO_PageTableIndW()
979 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF)); in _HAL_TSO_PageTableIndR()
980 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16)); in _HAL_TSO_PageTableIndR()
983 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN); in _HAL_TSO_PageTableIndR()
986 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA)); in _HAL_TSO_PageTableIndR()
1008 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]); in HAL_TSO_Set_Filein_ReadAddr()
1013 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]); in HAL_TSO_Set_Filein_ReadAddr()
1022 …REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_6… in HAL_TSO_Set_Filein_ReadLen()
1030 …REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1); in HAL_TSO_Get_Filein_ReadAddr()
1031 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Get_Filein_ReadAddr()
1043 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Set_Filein_Ctrl()
1050 …REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ct… in HAL_TSO_Get_Filein_Ctrl()
1067 … REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_FileinTimer_Enable()
1081 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer); in HAL_TSO_Filein_Rate()
1086 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192Mode_Enable()
1100 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_Filein_192BlockMode_Enable()
1117 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRCnt()
1139 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift); in HAL_TSO_CmdQ_FIFO_Get_WRLevel()
1146 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1147 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1173 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)); in HAL_TSO_Cfg1_Enable()
1184 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD)); in HAL_TSO_Cfg1_Enable()
1185 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_Cfg1_Enable()
1193 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1194 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1); in HAL_TSO_ChIf_ClrByteCnt()
1197 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1198 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2); in HAL_TSO_ChIf_ClrByteCnt()
1201 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1202 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3); in HAL_TSO_ChIf_ClrByteCnt()
1205 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1206 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4); in HAL_TSO_ChIf_ClrByteCnt()
1209 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1210 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5); in HAL_TSO_ChIf_ClrByteCnt()
1213 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1214 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6); in HAL_TSO_ChIf_ClrByteCnt()
1260 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_ChIf_Cfg()
1263 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_ChIf_Cfg()
1266 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_ChIf_Cfg()
1269 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_ChIf_Cfg()
1272 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_ChIf_Cfg()
1275 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1307 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1310 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1313 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1319 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1322 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
1354 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data); in HAL_TSO_Get_ChIf_Cfg()
1361 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1); in HAL_TSO_File_Cfg1_Enable()
1399 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_ValidBlock_Count()
1405 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_ValidBlock_Count()
1407 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1408 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_ValidBlock_Count()
1418 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2)); in HAL_TSO_RW_InvalidBlock_Count()
1424 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data); in HAL_TSO_RW_InvalidBlock_Count()
1426 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1427 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD); in HAL_TSO_RW_InvalidBlock_Count()
1499 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Set()
1500 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Set()
1511 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1); in HAL_TSO_LPcr2_Get()
1512 …REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CON… in HAL_TSO_LPcr2_Get()
1524 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1); in HAL_TSO_TimeStamp_Get()
1534 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_PktChkSize_Set()
1535 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1539 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_PktChkSize_Set()
1540 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1544 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_PktChkSize_Set()
1545 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1549 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_PktChkSize_Set()
1550 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1554 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_PktChkSize_Set()
1555 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1559 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_PktChkSize_Set()
1560 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK) in HAL_TSO_PktChkSize_Set()
1573 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize); in HAL_TSO_RW_OutputPktSize()
1577 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3)); in HAL_TSO_RW_OutputPktSize()
1580 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PK… in HAL_TSO_RW_OutputPktSize()
1581 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_… in HAL_TSO_RW_OutputPktSize()
1589 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1590 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1594 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN), in HAL_TSO_Filein_PktChkSize_Set()
1595 … (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK) in HAL_TSO_Filein_PktChkSize_Set()
1609 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1610 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1614 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1615 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1619 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1620 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1624 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1625 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1629 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1630 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1634 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0), in HAL_TSO_Livein_PktChkSize_Set()
1635 …(_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MAS… in HAL_TSO_Livein_PktChkSize_Set()
1650 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1651 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1654 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1655 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1658 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1), in HAL_TSO_Livein_Input_Config()
1659 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1663 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1664 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1667 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1668 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1671 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1), in HAL_TSO_Livein_Input_Config()
1672 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1676 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1677 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1680 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1681 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1684 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1), in HAL_TSO_Livein_Input_Config()
1685 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1689 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1690 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1693 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1694 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1697 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1), in HAL_TSO_Livein_Input_Config()
1698 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1702 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1703 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1706 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1707 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1710 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1), in HAL_TSO_Livein_Input_Config()
1711 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1715 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1716 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK) in HAL_TSO_Livein_Input_Config()
1719 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1720 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK) in HAL_TSO_Livein_Input_Config()
1723 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1), in HAL_TSO_Livein_Input_Config()
1724 … (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK) in HAL_TSO_Livein_Input_Config()
1741 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1753 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1756 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1768 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1); in HAL_TSO_Livein_3Wire()
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2); in HAL_TSO_Livein_3Wire()
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3); in HAL_TSO_Livein_3Wire()
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4); in HAL_TSO_Livein_3Wire()
1780 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5); in HAL_TSO_Livein_3Wire()
1783 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6); in HAL_TSO_Livein_3Wire()
1797 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1801 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE); in HAL_TSO_TsioMode_En()
1809 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1813 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF); in HAL_TSO_Tsio2Opif_En()
1821 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
1825 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN); in HAL_TSO_SerialMode_En()
2119 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2124 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2169 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2174 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM); in HAL_TSO_PowerCtrl()
2319 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()
2323 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1); in HAL_TSO_Set_SvqBypass()