1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halTSO.c
20 // @brief TS I/O HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "regTSO.h"
25 #include "halTSO.h"
26 #include "drvSYS.h"
27 #include "halCHIP.h"
28
29 #ifdef CONFIG_MSTAR_CLKM
30 #include "drvCLKM.h"
31 #endif
32
33 //--------------------------------------------------------------------------------------------------
34 // Driver Compiler Option
35 //--------------------------------------------------------------------------------------------------
36 #define TSP_HAL_REG_SAFE_MODE 1 // Register protection access between 1 task and 1+ ISR
37
38 #define MIU_BUS 4
39
40
41 //--------------------------------------------------------------------------------------------------
42 // TSP Hardware Abstraction Layer
43 //--------------------------------------------------------------------------------------------------
44 static REG_Ctrl_TSO* _TSOCtrl = NULL;
45 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
46 static REG_Ctrl_TSO2* _TSOCtrl2 = NULL;
47
48 static MS_VIRT _u32TSORegBase = 0;
49
50 //-------------------------------------------------------------------------------------------------
51 // Debug Message
52 //-------------------------------------------------------------------------------------------------
53 typedef enum
54 {
55 E_HAL_TSO_DBG_LEVEL_NONE, // no debug message shown
56 E_HAL_TSO_DBG_LEVEL_ERR, // only shows error message that can't be recover
57 E_HAL_TSO_DBG_LEVEL_WARN, // error case can be recover, like retry
58 E_HAL_TSO_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
59 E_HAL_TSO_DBG_LEVEL_INFO, // information for internal parameter
60 E_HAL_TSO_DBG_LEVEL_FUNC, // Function trace and input parameter trace
61 E_HAL_TSO_DBG_LEVEL_TRACE, // debug trace
62 } EN_HAL_TSO_DBGMSG_LEVEL;
63
64 typedef enum
65 {
66 E_HAL_TSO_DBG_MODEL_NONE, // @temporarily , need to refine
67 E_HAL_TSO_DBG_MODEL_ALL,
68 } EN_HAL_TSO_DBGMSG_MODEL;
69
70 #define HAL_TSO_DBGMSG(_level,_model,_f) do {if(_u32TSODbgLevel >= (_level)&&((_u32TSODbgModel&_model)!=0)) (_f);} while(0)
71 static MS_U32 _u32TSODbgLevel = E_HAL_TSO_DBG_LEVEL_ERR;
72 static MS_U32 _u32TSODbgModel = E_HAL_TSO_DBG_MODEL_ALL;
73
74
75 //[NOTE] Jerry
76 // Some register has write order, for example, writing PCR_L will disable PCR counter
77 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
78 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
79 (reg)->H = ((value) >> 16); } while(0)
80
81 #define _HAL_REG16_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
82
83 //--------------------------------------------------------------------------------------------------
84 // Macro of bit operations
85 //--------------------------------------------------------------------------------------------------
86 #define HAS_FLAG(flag, bit) ((flag) & (bit))
87 #define SET_FLAG(flag, bit) ((flag) |= (bit))
88 #define RESET_FLAG(flag, bit) ((flag) &= (~(bit)))
89 #define SET_FLAG1(flag, bit) ((flag) | (bit))
90 #define RESET_FLAG1(flag, bit) ((flag) & (~(bit)))
91
92
93 #define _REG16_SET(reg, value); _HAL_REG16_W(reg, SET_FLAG1(_HAL_REG16_R(reg), value));
94 #define _REG32_SET(reg, value); _HAL_REG32_W(reg, SET_FLAG1(_HAL_REG32_R(reg), value));
95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
96 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
97
98
99
100
101 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1600UL + ((addr)<<2))))
102 #define REG_CLKGEN0_TSO_IN 0x27
103 #define REG_CLKGEN0_TSO_IN_MASK 0x003F
104 #define REG_CLKGEN0_TSO_IN_SHIFT 2
105 #define REG_CLKGEN0_TSO_IN_DISABLE 0x0001
106 #define REG_CLKGEN0_TSO_IN_INVERT 0x0002
107 // bit[4:0] -> 0: disable clock
108 // 1: invert clock
109 // bit [3:2] -> 000: select TS0_CLK
110 // 001: select TS1_CLK
111 // 010: from demod 0
112 #define REG_CLKGEN0_TSO_TRACE_MASK 0x0F00
113 #define REG_CLKGEN0_TSO_TRACE_DISABLE 0x0100
114 #define REG_CLKGEN0_TSO_TRACE_INVERT 0x0200
115 #define REG_CLKGEN0_TSO_TRACE_216M 0x0000
116
117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D
118 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK 0x001F
119 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT 0
120 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_EN_MASK 0x0020
121 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE 0x0020
122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040
123 #define HAL_TSO_OUT_DIV_SEL_172M_2N 0x0000
124 #define HAL_TSO_OUT_DIV_SEL_288M_2N 0x0040
125
126 #define REG_CLKGEN0_TSO_OUT_DIVNUM 0x2E
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0
128 #define REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT 6
129 #define REG_CLKGEN_TSO_P_TSO_OUT_MASK 0xF800
130 #define REG_CLKGEN_TSO_P_TSO_OUT_SHIFT 13
131
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F
133 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x003F
134 #define REG_CLKGEN0_TSO_OUT_CLK_DISABLE 0x0001
135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002
136 #define REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT 2
137 // bit[4:0] -> 0: disable clock
138 // 1: invert clock
139 // bit [4:2] -> 000: from demod 0, clk_dvbtc_ts_p
140 // 001: 62MHz
141 // 010: 54MHz
142 // 011: clk_p_tso_out (live in)
143 // 100: clk_p_tso_out_div8 (live in)
144 // 101: tso_out_div (clock/(N+1))
145 // 110: 86MHz
146
147 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x6600UL + ((addr)<<2))))
148 #define REG_CLKGEN1_DEMOD0_OUT_CLK 0x00
149 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_MASK 0x001F //demod0 div num of output clk
150 #define REG_CLKGEN1_DVBTM0_TS_DIVNUM_SHIFT 0
151 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_MASK 0x0100 //demod0 div src of output clk
152 #define REG_CLKGEN1_ATSC_DVB0_DIV_SEL_SHIFT 8
153 // bit[8] -> 0: CLK_DMPLLDIV2
154 // 1: CLK_DMPLLDIV3
155
156 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x1400UL + ((addr)<<2))))
157 #define REG_CLKGEN2_TSO1_IN 0x06
158 #define REG_CLKGEN2_TSO2_IN 0x07
159 #define REG_CLKGEN2_TSO3_IN 0x08
160 #define REG_CLKGEN2_TSO4_IN 0x09
161 #define REG_CLKGEN2_TSO5_IN 0x0a
162
163 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x3c00UL + ((addr)<<2))))
164 #define REG_TOP_TSO_MUX 0x3A
165 #define REG_TOP_TSO_MUX_MASK 0x000F
166 #define REG_TOP_TSO1_MUX_SHIFT 0
167 #define REG_TOP_TSO2_MUX_SHIFT 4
168 #define REG_TOP_TSO3_MUX_SHIFT 8
169 #define REG_TOP_TSO4_MUX_SHIFT 12
170
171 #define REG_TOP_TSO1_MUX 0x3B
172 #define REG_TOP_TSO5_MUX_SHIFT 0
173 #define REG_TOP_TSO6_MUX_SHIFT 4
174 // bit[2:0] -> 000: PAD_TS0
175 // 001: PAD_TS1
176 // 0111: DEMOD
177
178 #if 0 // Not used
179 #define REG_TOP_MIU_GP1_i64 0x21
180 #define REG_TOP_MIU_GP1_i64_TSO_MASK 0x0080
181 #define REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT 0x0000
182 #define REG_TOP_MIU_GP1_i64_TSO_64BIT_CLIENT 0x0080
183 #define REG_TOP_TS_CONFIG 0x57
184 #define REG_TOP_TS0_CONFIG_MASK 0x0700
185 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0100
186 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0200
187 #define REG_TOP_TS1_CONFIG_MASK 0x3800
188 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800
189 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000
190 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800
191 #define REG_TOP_TS2_CONFIG_MASK 0x4000
192 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x4000
193 #define REG_TOP_TSCB_CONFIG_MASK 0x8000
194 #define REG_TOP_TSCB_CONFIG_SERIAL_IN 0x8000
195 #define REG_TOP_TS_OUT_MODE 0x6E
196 #define REG_TOP_TS_OUT_MODE_MASK 0x0300
197 #define REG_TOP_TS_OUT_MODE_TSO 0x0200
198 #endif
199
200 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00UL + ((addr)<<2))))
201 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400UL + ((addr)<<2))))
202 #define REG_MIUDIG_MIU_SEL1 0x79
203 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080
204
205 //--------------------------------------------------------------------------------------------------
206 // Implementation
207 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_TSO * reg)208 static MS_U32 _HAL_REG32_R(REG32_TSO *reg)
209 {
210 MS_U32 value = 0;
211 value = (reg)->L;
212 value |= (reg)->H << 16;
213 return value;
214 }
215
_HAL_REG16_R(REG16_TSO * reg)216 static MS_U16 _HAL_REG16_R(REG16_TSO *reg)
217 {
218 MS_U16 value = 0;
219 value = (reg)->data;
220 return value;
221 }
222
HAL_TSO_SetBank(MS_VIRT u32BankAddr)223 void HAL_TSO_SetBank(MS_VIRT u32BankAddr)
224 {
225 _u32TSORegBase = u32BankAddr;
226 _TSOCtrl = (REG_Ctrl_TSO*)(_u32TSORegBase+ REG_CTRL_BASE_TSO); // 0x1706
227 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_u32TSORegBase+ REG_CTRL_BASE_TSO1); // 0x1612
228 _TSOCtrl2 = (REG_Ctrl_TSO2*)(_u32TSORegBase+ REG_CTRL_BASE_TSO2); // 0x1539
229 }
230
231 //
232 // General API
233 //
HAL_TSO_Init(void)234 void HAL_TSO_Init(void)
235 {
236 //select MIU0, and 128bit MIU bus
237 /*
238 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
239 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
240 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
241 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
242 */
243
244 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5), TSO_CONFIG5_FIXED_MIU_REG_FLUSH);
245
246 }
247
HAL_TSO_Reset_All(MS_U8 u8Eng)248 void HAL_TSO_Reset_All(MS_U8 u8Eng)
249 {
250 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active
251 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);
252
253 _REG16_SET(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
254 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1);
255 }
256
HAL_TSO_Reset(MS_U8 u8Eng)257 void HAL_TSO_Reset(MS_U8 u8Eng)
258 {
259 //@TODO not find in register table
260 /*
261 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
262 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
263 */
264 }
265
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)266 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
267 {
268 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) | u16RstItem));
269 _HAL_REG16_W(&(_TSOCtrl[u8Eng].SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl[u8Eng].SW_RSTZ)) & ~u16RstItem));
270 }
271
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL bEnable,MS_U16 u16init)272 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL bEnable, MS_U16 u16init)
273 {
274 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
275 MS_U16 u16data = _HAL_REG16_R(reg);
276
277 if(bEnable)
278 {
279 _HAL_REG16_W(reg, (u16data | u16init));
280 }
281 else
282 {
283 _HAL_REG16_W(reg, (u16data & ~u16init));
284 }
285 }
286
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)287 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
288 {
289 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
290
291 _HAL_REG16_W(reg, (_HAL_REG16_R(reg) & ~u16Int));
292 }
293
HAL_TSO_HWInt_Status(MS_U8 u8Eng)294 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
295 {
296 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->INTERRUPT) : &(_TSOCtrl->INTERRUPT1);
297
298 return (_HAL_REG16_R(reg) & TSO_INT_STS_MASK);
299 }
300
HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId,MS_U16 * u16Pad,MS_U16 * u16Clk)301 MS_BOOL HAL_TSO_3WirePadMapping(MS_U8 u8Pad3WireId, MS_U16 *u16Pad, MS_U16 *u16Clk)
302 {
303 switch(u8Pad3WireId)
304 {
305 case 3:
306 *u16Pad = HAL_TSOIN_MUX_TS3;
307 *u16Clk = TSO_CLKIN_TS3;
308 break;
309 case 4:
310 *u16Pad = HAL_TSOIN_MUX_TS4;
311 *u16Clk = TSO_CLKIN_TS4;
312 break;
313 case 5:
314 *u16Pad = HAL_TSOIN_MUX_TS5;
315 *u16Clk = TSO_CLKIN_TS5;
316 break;
317 case 6:
318 *u16Pad = HAL_TSOIN_MUX_TS6;
319 *u16Clk = TSO_CLKIN_TS6;
320 break;
321 default:
322 printf("[%s][%d]: Not support !!\n", __FUNCTION__, __LINE__);
323 return FALSE;
324 }
325
326 return TRUE;
327 }
328
329
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)330 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
331 {
332 MS_U16 u16Reg, u16RegShift;
333
334 switch(u8TsIf)
335 {
336 case HAL_TSO_TSIF_LIVE1:
337 u16Reg = REG_TOP_TSO_MUX;
338 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
339 break;
340 case HAL_TSO_TSIF_LIVE2:
341 u16Reg = REG_TOP_TSO_MUX;
342 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
343 break;
344 case HAL_TSO_TSIF_LIVE3:
345 u16Reg = REG_TOP_TSO_MUX;
346 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
347 break;
348 case HAL_TSO_TSIF_LIVE4:
349 u16Reg = REG_TOP_TSO_MUX;
350 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
351 break;
352 case HAL_TSO_TSIF_LIVE5:
353 u16Reg = REG_TOP_TSO1_MUX;
354 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
355 break;
356 case HAL_TSO_TSIF_LIVE6:
357 u16Reg = REG_TOP_TSO1_MUX;
358 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
359 break;
360 default:
361 printf("Not support !!\n");
362 return FALSE;
363 }
364
365 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~(REG_TOP_TSO_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
366
367 //@NOTE: no need to change input pad mode dynamically (Mboot handle it...)
368
369 return TRUE;
370 }
371
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)372 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
373 {
374 //@TODO not implement
375 return TRUE;
376 }
377
378
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)379 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
380 {
381 MS_U16 u16Reg, u16RegShift;
382 MS_U16 u16data = 0;
383 REG16_TSO* reg16 = 0;
384
385 // Set pad mux
386 switch(u8TsIf)
387 {
388 case HAL_TSO_TSIF_LIVE1:
389 u16Reg = REG_TOP_TSO_MUX;
390 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
391 break;
392 case HAL_TSO_TSIF_LIVE2:
393 u16Reg = REG_TOP_TSO_MUX;
394 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
395 break;
396 case HAL_TSO_TSIF_LIVE3:
397 u16Reg = REG_TOP_TSO_MUX;
398 u16RegShift = REG_TOP_TSO3_MUX_SHIFT;
399 break;
400 case HAL_TSO_TSIF_LIVE4:
401 u16Reg = REG_TOP_TSO_MUX;
402 u16RegShift = REG_TOP_TSO4_MUX_SHIFT;
403 break;
404 case HAL_TSO_TSIF_LIVE5:
405 u16Reg = REG_TOP_TSO1_MUX;
406 u16RegShift = REG_TOP_TSO5_MUX_SHIFT;
407 break;
408 case HAL_TSO_TSIF_LIVE6:
409 u16Reg = REG_TOP_TSO1_MUX;
410 u16RegShift = REG_TOP_TSO6_MUX_SHIFT;
411 break;
412 default:
413 printf("Not support !!\n");
414 return FALSE;
415 }
416
417 *pu16Pad = (TSP_TOP_REG(u16Reg) >> u16RegShift) & REG_TOP_TSO_MUX_MASK;
418
419 switch(u8TsIf)
420 {
421 case HAL_TSO_TSIF_LIVE1:
422 u16data = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK;
423 reg16 = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
424 break;
425 case HAL_TSO_TSIF_LIVE2:
426 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN0_TSO_IN_MASK;
427 reg16 = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
428 break;
429 case HAL_TSO_TSIF_LIVE3:
430 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) & REG_CLKGEN0_TSO_IN_MASK;
431 reg16 = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
432 break;
433 case HAL_TSO_TSIF_LIVE4:
434 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) & REG_CLKGEN0_TSO_IN_MASK;
435 reg16 = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
436 break;
437 case HAL_TSO_TSIF_LIVE5:
438 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) & REG_CLKGEN0_TSO_IN_MASK;
439 reg16 = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
440 break;
441 case HAL_TSO_TSIF_LIVE6:
442 u16data = TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) & REG_CLKGEN0_TSO_IN_MASK;
443 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
444 break;
445 default:
446 printf("Not support !!\n");
447 return FALSE;
448 }
449
450 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
451 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
452 *pbClkInvert = ((u16data & REG_CLKGEN0_TSO_IN_INVERT) == REG_CLKGEN0_TSO_IN_INVERT);
453
454 return TRUE;
455 }
456
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)457 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
458 {
459 MS_BOOL isCLKGEN0 = FALSE;
460 MS_U16 u16Reg;
461 MS_U16 u16value = 0;
462
463 switch(u8TsIf)
464 {
465 case HAL_TSO_TSIF_LIVE1:
466 isCLKGEN0 = TRUE;
467 u16Reg = REG_CLKGEN0_TSO_IN;
468 break;
469 case HAL_TSO_TSIF_LIVE2:
470 u16Reg = REG_CLKGEN2_TSO1_IN;
471 break;
472 case HAL_TSO_TSIF_LIVE3:
473 u16Reg = REG_CLKGEN2_TSO2_IN;
474 break;
475 case HAL_TSO_TSIF_LIVE4:
476 u16Reg = REG_CLKGEN2_TSO3_IN;
477 break;
478 case HAL_TSO_TSIF_LIVE5:
479 u16Reg = REG_CLKGEN2_TSO4_IN;
480 break;
481 case HAL_TSO_TSIF_LIVE6:
482 u16Reg = REG_CLKGEN2_TSO5_IN;
483 break;
484 default:
485 printf("Not support !!\n");
486 return FALSE;
487 }
488
489 if(u16ClkSel == 0xFFFF)
490 {
491 return FALSE;
492 }
493
494 if(isCLKGEN0)
495 {
496 u16value = TSO_CLKGEN0_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
497 }
498 else
499 {
500 u16value = TSO_CLKGEN2_REG(u16Reg) & ~REG_CLKGEN0_TSO_IN_MASK;
501 }
502
503 if(!bEnable)
504 {
505 u16value |= REG_CLKGEN0_TSO_IN_DISABLE;
506 }
507 else
508 {
509 #ifndef CONFIG_MSTAR_CLKM
510 u16value |= (u16ClkSel << REG_CLKGEN0_TSO_IN_SHIFT);
511 #endif
512
513 if(bClkInvert)
514 {
515 u16value |= REG_CLKGEN0_TSO_IN_INVERT;
516 }
517 }
518
519 if(isCLKGEN0)
520 {
521 TSO_CLKGEN0_REG(u16Reg) = u16value;
522 }
523 else
524 {
525 TSO_CLKGEN2_REG(u16Reg) = u16value;
526 }
527
528 #ifdef CONFIG_MSTAR_CLKM
529
530 MS_S32 s32Handle;
531 char u8ClkSrcName[20] = "";
532 MS_U8 u8Idx = u8TsIf - 1;
533
534 switch(u16ClkSel)
535 {
536 case TSO_CLKIN_TS0:
537 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD0", u8Idx);
538 break;
539 case TSO_CLKIN_TS1:
540 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD1", u8Idx);
541 break;
542 case TSO_CLKIN_TS2:
543 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD2", u8Idx);
544 break;
545 case TSO_CLKIN_TS3:
546 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD3", u8Idx);
547 break;
548 case TSO_CLKIN_TS4:
549 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD4", u8Idx);
550 break;
551 case TSO_CLKIN_TS5:
552 sprintf(u8ClkSrcName, "CLK_TSOIN%u_PAD5", u8Idx);
553 break;
554 default:
555 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
556 return FALSE;
557 }
558
559 switch(u8TsIf)
560 {
561 case HAL_TSO_TSIF_LIVE1:
562 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
563 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
564 break;
565 case HAL_TSO_TSIF_LIVE2:
566 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
567 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
568 break;
569 case HAL_TSO_TSIF_LIVE3:
570 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
571 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
572 break;
573 case HAL_TSO_TSIF_LIVE4:
574 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
575 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
576 break;
577 case HAL_TSO_TSIF_LIVE5:
578 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
579 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
580 break;
581 case HAL_TSO_TSIF_LIVE6:
582 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
583 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcName);
584 break;
585 default:
586 printf("Not support !!\n");
587 return FALSE;
588 }
589
590 #endif
591
592 return TRUE;
593 }
594
595 #if 0
596 #define NPM_REG_ANAMISC 0x10C00 //0x110c00 //ana misc
597 #define NPM_REG_MIPS_PLLCLK (NPM_REG_ANAMISC+0x0002)
598 static MS_U32 _HAL_TSO_CPU_QueryClock(void)
599 {
600 MS_U32 u32Count = 0;
601 MS_U32 u32Speed = 0;
602 //here we assum that _u32TSORegBase is the same as non-PM bank
603 u32Speed = (MS_U32)((volatile MS_U16*)(_u32TSORegBase))[NPM_REG_MIPS_PLLCLK];
604 u32Count = ((u32Speed & 0xFF00) >> 8) * 12000000;
605
606 return u32Count;
607 }
608
609 static void _HAL_TSO_Delay(MS_U32 u32Us)
610 {
611 MS_U32 u32CPUClk = _HAL_TSO_CPU_QueryClock();
612 register MS_U32 u32Loop = (((u32CPUClk/1000000)/3)*(u32Us));// 3 cycles / loop
613 while(u32Loop--);
614 }
615 #endif
616
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)617 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
618 {
619 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
620 {
621 return FALSE; //not support yet
622 }
623
624 switch(u16PadSel)
625 {
626 case HAL_TSOIN_MUX_TS0:
627 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
628 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
629 break;
630 case HAL_TSOIN_MUX_TS1:
631 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
632 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
633 break;
634 case HAL_TSOIN_MUX_TS2:
635 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
636 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
637 break;
638 case HAL_TSOIN_MUX_TS3:
639 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
640 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS3IN;
641 break;
642 case HAL_TSOIN_MUX_TS4:
643 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
644 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS4IN;
645 break;
646 case HAL_TSOIN_MUX_TS5:
647 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
648 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS5IN;
649 break;
650 /*
651 case HAL_TSOIN_MUX_TSDEMOD0:
652 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
653 break;
654 */
655 case HAL_TSOIN_MUX_MEM:
656 case HAL_TSOIN_MUX_MEM1:
657 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV2N;
658 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
659 pstOutClkSet->u16OutDivNum = 0x0F; //default: 172.8/2*(15+1) = 5.4M
660 break;
661 default:
662 return FALSE;
663 }
664
665 return TRUE;
666 }
667
668
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)669 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16 *pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
670 {
671 //clock source for clock divide
672 if(bSet == TRUE)
673 {
674 /*
675 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
676 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
677 */
678
679 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
680 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
681
682 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
683 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum << REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT);
684 }
685 else
686 {
687 *pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
688 *pu16ClkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> REG_CLKGEN0_TSO_OUT_DIVNUM_SHIFT;
689 }
690
691 return TRUE;
692 }
693
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)694 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
695 {
696 if(bSet == TRUE)
697 {
698 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS6IN)
699 {
700 return FALSE;
701 }
702
703 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) =
704 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | ((*pu16PreTsoOutSel) << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
705 }
706 else
707 {
708 *pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN_TSO_P_TSO_OUT_MASK) >> REG_CLKGEN_TSO_P_TSO_OUT_SHIFT;
709 }
710
711 return TRUE;
712 }
713
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)714 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
715 {
716 if(bSet == TRUE)
717 {
718 if(pstOutClkSet->bEnable == FALSE)
719 {
720 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
721 return;
722 }
723
724 switch(pstOutClkSet->u16OutClk)
725 {
726 case HAL_TSO_OUT_SEL_TSO_OUT_DIV2N:
727 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
728 break;
729 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
730 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
731 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
732 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
733 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
734 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
735 break;
736 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
737 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
738 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
739 break;
740 default:
741 return;
742 }
743
744 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
745 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //always need TSO out clock
746 }
747 else
748 {
749 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
750 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV)
751 {
752 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
753 }
754 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
755 {
756 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
757 }
758 }
759 }
760
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)761 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
762 {
763 MS_U16 u16value = 0;
764 if(u8Eng == 0)
765 {
766 if(!bPhaseEnable)
767 {
768 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
769 }
770 else
771 {
772 u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)
773 | (u16ClkOutPhase << REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT);
774
775 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;
776 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
777 }
778 }
779 else
780 {
781 return FALSE;
782 }
783
784 return TRUE;
785 }
786
HAL_TSO_Set_PreTsoOutClk(MS_U8 u8Eng,MS_U16 u16PreTsoOutSel)787 MS_BOOL HAL_TSO_Set_PreTsoOutClk(MS_U8 u8Eng, MS_U16 u16PreTsoOutSel)
788 {
789 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
790 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | (u16PreTsoOutSel << REG_CLKGEN_TSO_P_TSO_OUT_SHIFT);
791
792 return TRUE;
793 }
794
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)795 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
796 {
797 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
798
799 if(bSet == TRUE)
800 {
801 if(*pbEnable == FALSE)
802 {
803 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
804 }
805 else
806 {
807 /*
808 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
809 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
810 */
811 #ifndef CONFIG_MSTAR_CLKM
812 u16Clk |= (*pu16ClkOutSel << REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT);
813 #endif
814
815 if(*pbClkInvert)
816 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT;
817 }
818
819 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;
820
821 #ifdef CONFIG_MSTAR_CLKM
822
823 MS_S32 s32Handle;
824 MS_U8 u8NameIdx = 0;
825 char* u8ClkSrcNames[] =
826 {
827 "CLK_TSOOUT_27M",
828 "CLK_TSOOUT_62M",
829 "CLK_TSOOUT_108M",
830 "CLK_TSOOUT_FROMPAD",
831 "CLK_TSOOUT_DIV8",
832 "CLK_TSOOUT_DIV",
833 "CLK_TSOOUT_86M",
834 "CLK_TSOOUT_123M"
835 };
836
837 switch(*pu16ClkOutSel)
838 {
839 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
840 u8NameIdx = 0;
841 break;
842 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
843 u8NameIdx = 1;
844 break;
845 case HAL_TSO_OUT_SEL_TSO_OUT_108MHz:
846 u8NameIdx = 2;
847 break;
848 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
849 u8NameIdx = 3;
850 break;
851 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
852 u8NameIdx = 4;
853 break;
854 case HAL_TSO_OUT_SEL_TSO_OUT_DIV:
855 u8NameIdx = 5;
856 break;
857 case HAL_TSO_OUT_SEL_TSO_OUT_86MHz:
858 u8NameIdx = 6;
859 break;
860 case HAL_TSO_OUT_SEL_TSO_OUT_123MHz:
861 u8NameIdx = 7;
862 break;
863 default:
864 printf("[%s][%d] Not support !!\n", __FUNCTION__, __LINE__);
865 return FALSE;
866 }
867
868 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_out");
869 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
870
871 #endif
872 }
873 else
874 {
875 *pbEnable = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_DISABLE) == 0);
876 *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT);
877 *pu16ClkOutSel = u16Clk >> REG_CLKGEN0_TSO_OUT_CLK_SRC_SHIFT;
878 }
879
880 return TRUE;
881 }
882
HAL_TSO_Set_PidBypass(MS_U8 u8Eng,MS_BOOL bEnable)883 MS_BOOL HAL_TSO_Set_PidBypass(MS_U8 u8Eng, MS_BOOL bEnable)
884 {
885 if(bEnable)
886 {
887 switch(u8Eng)
888 {
889 case HAL_TSO_TSIF_LIVE1:
890 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
891 break;
892 case HAL_TSO_TSIF_LIVE2:
893 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
894 break;
895 case HAL_TSO_TSIF_LIVE3:
896 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
897 break;
898 case HAL_TSO_TSIF_LIVE4:
899 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
900 break;
901 case HAL_TSO_TSIF_LIVE5:
902 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
903 break;
904 case HAL_TSO_TSIF_LIVE6:
905 _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
906 break;
907 default:
908 printf("Not support !!\n");
909 break;
910 }
911 }
912 else
913 {
914 switch(u8Eng)
915 {
916 case HAL_TSO_TSIF_LIVE1:
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL);
918 break;
919 case HAL_TSO_TSIF_LIVE2:
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL);
921 break;
922 case HAL_TSO_TSIF_LIVE3:
923 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL);
924 break;
925 case HAL_TSO_TSIF_LIVE4:
926 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL);
927 break;
928 case HAL_TSO_TSIF_LIVE5:
929 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL);
930 break;
931 case HAL_TSO_TSIF_LIVE6:
932 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL);
933 break;
934 default:
935 printf("Not support !!\n");
936 break;
937 }
938 }
939
940 return TRUE;
941 }
942
943 // ------------------------------------------------------
944 // APIS
945 //-------------------------------------------------------
946 #define TSO_PIDFLT_ADDR(FltId) (REG_PIDFLT_BASE + ((FltId) << 2))
947
_HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr,MS_U16 u16Wdata,MS_U8 u8Sid)948 static void _HAL_TSO_PageTableIndW_withSid(MS_U32 u32Addr, MS_U16 u16Wdata, MS_U8 u8Sid)
949 {
950 // addr
951 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
952 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
953
954 // Wdata
955 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
956 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), (u8Sid & 0x003F));
957
958 // Wen
959 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
960 }
961
_HAL_TSO_PageTableIndW(MS_U32 u32Addr,MS_U16 u16Wdata)962 static void _HAL_TSO_PageTableIndW(MS_U32 u32Addr, MS_U16 u16Wdata)
963 {
964 // addr
965 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
966 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
967
968 // Wdata
969 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_L), u16Wdata);
970 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_WDATA_H), 0x0000);
971
972 // Wen
973 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_W_EN);
974 }
975
_HAL_TSO_PageTableIndR(MS_U32 u32Addr)976 static MS_U16 _HAL_TSO_PageTableIndR(MS_U32 u32Addr)
977 {
978 // addr
979 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_L), (u32Addr & 0x0000FFFF));
980 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_ADDR_H), (u32Addr >> 16));
981
982 // Ren
983 _HAL_REG16_W(&(_TSOCtrl->PDTABLE_EN), TSO_PDTABLE_R_EN);
984
985 // Rdata
986 return _HAL_REG16_R(&(_TSOCtrl->PDTABLE_RDATA));
987 }
988
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)989 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
990 {
991 MS_U16 u16Temp = 0;
992
993 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
994 u16Temp = (u16Temp & (TSO_PIDFLT_IN_MASK << TSO_PIDFLT_IN_SHIFT)) | (u16PID & TSO_PIDFLT_PID_MASK);
995 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
996 }
997
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32Addr)998 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32Addr)
999 {
1000 REG32_TSO *FileInRaddr;
1001
1002 MS_U8 u8MiuSel;
1003 MS_PHY phyMiuOffsetFileinBuf;
1004 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinBuf, u32Addr);
1005
1006 if(u8FileEng == 0)
1007 {
1008 FileInRaddr = &(_TSOCtrl->CFG_TSO_60_63[0]);
1009 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_CH5FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH5FILEIN_SHIFT) & REG_MIU_SEL_CH5FILEIN_MASK));
1010 }
1011 else
1012 {
1013 FileInRaddr = &(_TSOCtrl->CFG_TSO_65_68[0]);
1014 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_2, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_2) & (~REG_MIU_SEL_CH6FILEIN_MASK)) | ((u8MiuSel << REG_MIU_SEL_CH6FILEIN_SHIFT) & REG_MIU_SEL_CH6FILEIN_MASK));
1015 }
1016
1017 _HAL_REG32_W(FileInRaddr, phyMiuOffsetFileinBuf);
1018 }
1019
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)1020 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
1021 {
1022 REG32_TSO *FileInRlen = (u8FileEng == 0)? &(_TSOCtrl->CFG_TSO_60_63[1]) : &(_TSOCtrl->CFG_TSO_65_68[1]);
1023
1024 _HAL_REG32_W(FileInRlen, u32len);
1025 }
1026
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)1027 MS_U32 HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
1028 {
1029 MS_U32 u32temp = 0;
1030 REG32_TSO *TSO2MI_RADDR = (u8FileEng == 0)? &(_TSOCtrl->TSO2MI_RADDR) : &(_TSOCtrl->TSO2MI_RADDR1);
1031 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1032
1033
1034 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1035 u32temp = (_HAL_REG32_R(TSO2MI_RADDR) << TSO_MIU_BUS);
1036 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ);
1037
1038 return u32temp;
1039 }
1040
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)1041 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
1042 {
1043 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1044
1045 _HAL_REG16_W(FileinCtrl, (_HAL_REG16_R(FileinCtrl) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1046 }
1047
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)1048 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
1049 {
1050 REG16_TSO *FileinCtrl = (u8FileEng == 0)? &(_TSOCtrl->TSO_Filein_Ctrl) : &(_TSOCtrl->TSO_Filein_Ctrl1);
1051
1052 return (_HAL_REG16_R(FileinCtrl) & TSO_FILEIN_CTRL_MASK);
1053 }
1054
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1055 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1056 {
1057 MS_U16 u16ChIf = (u8FileEng == 0)? TSO_CFG1_TSO_TSIF5_EN : TSO_CFG1_TSO_TSIF6_EN;
1058
1059 HAL_TSO_Cfg1_Enable(0, u16ChIf, bEnable);
1060 HAL_TSO_File_Cfg1_Enable(u8FileEng, (TSO_FILE_CONFIG_TSO_FILE_IN|TSO_FILE_CONFIG_TSP_FILE_SEGMENT|TSO_FILE_CONFIG_TS_DATA_PORT_SEL), bEnable);
1061
1062 return TRUE;
1063 }
1064
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1065 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1066 {
1067 REG16_TSO *pReg = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1068
1069 if(bEnable)
1070 {
1071 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) | TSO_FILE_CONFIG_TIMER_EN);
1072 }
1073 else
1074 {
1075 _HAL_REG16_W(pReg, _HAL_REG16_R(pReg) & ~TSO_FILE_CONFIG_TIMER_EN);
1076 }
1077 }
1078
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1079 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1080 {
1081 _HAL_REG16_W(&(_TSOCtrl->FILE_TIMER[u8FileEng]), u16timer);
1082 }
1083
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1084 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1085 {
1086 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1087
1088 if(bEnable)
1089 {
1090 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_EN));
1091 }
1092 else
1093 {
1094 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_EN));
1095 }
1096 }
1097
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1098 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1099 {
1100 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1101
1102 if(bEnable)
1103 {
1104 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) & ~TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1105 }
1106 else
1107 {
1108 _HAL_REG16_W(FILE_CONFIG, (_HAL_REG16_R(FILE_CONFIG) | TSO_FILE_CONFIG_PKT_192_BLK_DISABLE));
1109 }
1110 }
1111
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1112 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1113 {
1114 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK;
1115 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT;
1116
1117 return ((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1118 }
1119
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)1120 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng)
1121 {
1122 //@TODO not implement
1123 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_FULL);
1124 return FALSE;
1125 }
1126
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)1127 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng)
1128 {
1129 //@TODO not implement
1130 //return (MS_BOOL)(_HAL_REG16_R(&(_TSOCtrl[u8Eng].CmdQSts)) & TSO_CMDQ_STS_FIFO_EMPTY);
1131 return FALSE;
1132 }
1133
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1134 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1135 {
1136 MS_U16 u16Mask = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK;
1137 MS_U16 u16Shift = (u8FileEng == 0)? TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT : TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT;
1138
1139 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].CMD_QUEUE_STATUS)) & u16Mask) >> u16Shift);
1140 }
1141
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1142 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1143 {
1144 MS_U16 u16data = ((u8FileEng == 0)? TSO_SW_RST_CMDQ : TSO_SW_RST_CMDQ1);
1145
1146 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1147 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1148
1149 return TRUE;
1150 }
1151
HAL_TSO_Cfg0_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1152 void HAL_TSO_Cfg0_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1153 {
1154 //@TODO not implement
1155 /*
1156 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG0));
1157
1158 if(benable)
1159 {
1160 u16data |= u16CfgItem;
1161 }
1162 else
1163 {
1164 u16data &= ~u16CfgItem;
1165 }
1166
1167 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG0), u16data);
1168 */
1169 }
1170
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1171 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1172 {
1173 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1));
1174
1175 if(benable)
1176 {
1177 u16data |= u16CfgItem;
1178 }
1179 else
1180 {
1181 u16data &= ~u16CfgItem;
1182 }
1183
1184 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), (u16data | TSO_CFG1_PKT_PARAM_LD));
1185 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1186 }
1187
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1188 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1189 {
1190 switch(u8ChIf)
1191 {
1192 case HAL_TSO_TSIF_LIVE1:
1193 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1194 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_1);
1195 break;
1196 case HAL_TSO_TSIF_LIVE2:
1197 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1198 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_2);
1199 break;
1200 case HAL_TSO_TSIF_LIVE3:
1201 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1202 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_3);
1203 break;
1204 case HAL_TSO_TSIF_LIVE4:
1205 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1206 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_4);
1207 break;
1208 case HAL_TSO_TSIF_LIVE5:
1209 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1210 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_5);
1211 break;
1212 case HAL_TSO_TSIF_LIVE6:
1213 _REG16_SET(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1214 _REG16_CLR(&(_TSOCtrl[u8Eng].CLR_BYTE_CNT),TSO_CLR_BYTE_CNT_6);
1215 break;
1216 default:
1217 return FALSE;
1218 }
1219
1220 return TRUE;
1221 }
1222
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1223 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1224 {
1225 switch(u8ChIf)
1226 {
1227 case HAL_TSO_TSIF_LIVE1:
1228 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF1_EN, bEnable);
1229 break;
1230 case HAL_TSO_TSIF_LIVE2:
1231 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF2_EN, bEnable);
1232 break;
1233 case HAL_TSO_TSIF_LIVE3:
1234 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF3_EN, bEnable);
1235 break;
1236 case HAL_TSO_TSIF_LIVE4:
1237 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF4_EN, bEnable);
1238 break;
1239 case HAL_TSO_TSIF_LIVE5:
1240 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF5_EN, bEnable);
1241 break;
1242 case HAL_TSO_TSIF_LIVE6:
1243 HAL_TSO_Cfg1_Enable(u8Eng, TSO_CFG1_TSO_TSIF6_EN, bEnable);
1244 break;
1245 default:
1246 return FALSE;
1247 }
1248
1249 return TRUE;
1250 }
1251
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1252 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1253 {
1254 REG16_TSO *reg = NULL;
1255 MS_U16 u16data = 0;
1256
1257 switch(u8ChIf)
1258 {
1259 case HAL_TSO_TSIF_LIVE1:
1260 reg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1261 break;
1262 case HAL_TSO_TSIF_LIVE2:
1263 reg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1264 break;
1265 case HAL_TSO_TSIF_LIVE3:
1266 reg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1267 break;
1268 case HAL_TSO_TSIF_LIVE4:
1269 reg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1270 break;
1271 case HAL_TSO_TSIF_LIVE5:
1272 reg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1273 break;
1274 case HAL_TSO_TSIF_LIVE6:
1275 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1276 break;
1277 default:
1278 return FALSE;
1279 }
1280
1281 u16data = _HAL_REG16_R(reg);
1282
1283 if(bEnable)
1284 {
1285 u16data |= u16Cfg;
1286 }
1287 else
1288 {
1289 u16data &= ~u16Cfg;
1290 }
1291
1292 _HAL_REG16_W(reg, u16data);
1293 return TRUE;
1294 }
1295
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1296 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1297 {
1298 REG16_TSO* pReg = NULL;
1299 MS_U16 u16data = 0;
1300
1301 *pu16Cfg = 0;
1302 *pbEnable = FALSE;
1303
1304 switch(u8ChIf)
1305 {
1306 case HAL_TSO_TSIF_LIVE1:
1307 pReg = &(_TSOCtrl->CHANNEL0_IF1_CONFIG2);
1308 break;
1309 case HAL_TSO_TSIF_LIVE2:
1310 pReg = &(_TSOCtrl->CHANNEL0_IF2_CONFIG2);
1311 break;
1312 case HAL_TSO_TSIF_LIVE3:
1313 pReg = &(_TSOCtrl->CHANNEL0_IF3_CONFIG2);
1314 break;
1315 case HAL_TSO_TSIF_LIVE4:
1316 pReg = &(_TSOCtrl->CHANNEL0_IF4_CONFIG2);
1317 break;
1318 case HAL_TSO_TSIF_LIVE5:
1319 pReg = &(_TSOCtrl->CHANNEL0_IF5_CONFIG2);
1320 break;
1321 case HAL_TSO_TSIF_LIVE6:
1322 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2);
1323 break;
1324 default:
1325 return FALSE;
1326 }
1327
1328 *pu16Cfg = _HAL_REG16_R(pReg);
1329
1330 switch(u8ChIf)
1331 {
1332 case HAL_TSO_TSIF_LIVE1:
1333 u16data = TSO_CFG1_TSO_TSIF1_EN;
1334 break;
1335 case HAL_TSO_TSIF_LIVE2:
1336 u16data = TSO_CFG1_TSO_TSIF2_EN;
1337 break;
1338 case HAL_TSO_TSIF_LIVE3:
1339 u16data = TSO_CFG1_TSO_TSIF3_EN;
1340 break;
1341 case HAL_TSO_TSIF_LIVE4:
1342 u16data = TSO_CFG1_TSO_TSIF4_EN;
1343 break;
1344 case HAL_TSO_TSIF_LIVE5:
1345 u16data = TSO_CFG1_TSO_TSIF5_EN;
1346 break;
1347 case HAL_TSO_TSIF_LIVE6:
1348 u16data = TSO_CFG1_TSO_TSIF6_EN;
1349 break;
1350 default:
1351 return FALSE;
1352 }
1353
1354 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG1)) & u16data) == u16data);
1355
1356 return TRUE;
1357 }
1358
HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL benable)1359 void HAL_TSO_File_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL benable)
1360 {
1361 REG16_TSO *reg = (u8Eng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1362 MS_U16 u16data = _HAL_REG16_R(reg);
1363
1364 if(benable)
1365 {
1366 u16data |= u16CfgItem;
1367 }
1368 else
1369 {
1370 u16data &= ~u16CfgItem;
1371 }
1372
1373 _HAL_REG16_W(reg, u16data);
1374 }
1375
1376
1377
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U32 u32CfgItem,MS_BOOL benable)1378 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U32 u32CfgItem, MS_BOOL benable)
1379 {
1380 //@TODO not implement
1381 /*
1382 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CFG4));
1383
1384 if(benable)
1385 {
1386 u16data |= u32CfgItem;
1387 }
1388 else
1389 {
1390 u16data &= ~u32CfgItem;
1391 }
1392
1393 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CFG4), u16data);
1394 */
1395 }
1396
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1397 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1398 {
1399 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1400
1401 if(bWrite)
1402 {
1403 u16data &= ~TSO_CONFIG2_VALID_BYTE_CNT_MASK;
1404 u16data |= (*pu16ValidBlockCnt << TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1405 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1406
1407 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1408 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1409 }
1410 else
1411 {
1412 *pu16ValidBlockCnt = ((u16data & TSO_CONFIG2_VALID_BYTE_CNT_MASK) >> TSO_CONFIG2_VALID_BYTE_CNT_SHIFT);
1413 }
1414 }
1415
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1416 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1417 {
1418 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CONFIG2));
1419
1420 if(bWrite)
1421 {
1422 u16data &= ~TSO_CONFIG2_INVALID_BYTE_CNT_MASK;
1423 u16data |= (*pu16InvalidBlockCnt << TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT);
1424 _HAL_REG16_W(&(_TSOCtrl[u8Eng].TSO_CONFIG2), u16data);
1425
1426 _REG16_SET(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1427 _REG16_CLR(&(_TSOCtrl[u8Eng].TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD);
1428 }
1429 else
1430 {
1431 *pu16InvalidBlockCnt = (u16data & TSO_CONFIG2_INVALID_BYTE_CNT_MASK) >> TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT;
1432 }
1433 }
1434
HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)1435 MS_U32 HAL_TSO_Get_TsHDInfo_CC(MS_U8 u8Eng)
1436 {
1437 //@TODO not implement
1438 //return (_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK);
1439 return 0;
1440 }
1441
HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)1442 MS_U32 HAL_TSO_Get_TsHDInfo_ADP(MS_U8 u8Eng)
1443 {
1444 //@TODO not implement
1445 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_CONT_COUNTER_MASK) >> TSO_HD_ADP_FIELD_SHIFT);
1446 return 0;
1447 }
1448
HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)1449 MS_U32 HAL_TSO_Get_TsHDInfo_SCM(MS_U8 u8Eng)
1450 {
1451 //@TODO not implement
1452 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PID_MASK) >> TSO_HD_PID_SHIFT);
1453 return 0;
1454 }
1455
HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)1456 MS_U32 HAL_TSO_Get_TsHDInfo_PID(MS_U8 u8Eng)
1457 {
1458 //@TODO not implement
1459 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_SCRM_FIELD_MASK) >> TSO_HD_SCRM_FIELD_SHIFT);
1460 return 0;
1461 }
1462
HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)1463 MS_U32 HAL_TSO_Get_TsHDInfo_TSPri(MS_U8 u8Eng)
1464 {
1465 //@TODO not implement
1466 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_TS_PRIORITY_MASK) >> TSO_HD_TS_PRIORITY_SHIFT);
1467 return 0;
1468 }
1469
HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)1470 MS_U32 HAL_TSO_Get_TsHDInfo_PSI(MS_U8 u8Eng)
1471 {
1472 //@TODO not implement
1473 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_START_IND_MASK) >> TSO_HD_PAYLOAD_START_IND_SHIFT);
1474 return 0;
1475 }
1476
HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)1477 MS_U32 HAL_TSO_Get_TsHDInfo_ErrInd(MS_U8 u8Eng)
1478 {
1479 //@TODO not implement
1480 //return ((_HAL_REG32_R(&(_TSOCtrl[u8Eng].TSO_Header)) & TSO_HD_PAYLOAD_ERR_IND_MASK) >> TSO_HD_PAYLOAD_ERR_IND_SHIFT);
1481 return 0;
1482 }
1483
HAL_TSO_Get_Pid_Info(MS_U8 u8Eng,MS_U16 * pu16matchpid,MS_BOOL * pbchanged)1484 void HAL_TSO_Get_Pid_Info(MS_U8 u8Eng, MS_U16 *pu16matchpid, MS_BOOL *pbchanged)
1485 {
1486 //@TODO not implement
1487 /*
1488 MS_U16 u16temp;
1489
1490 u16temp = _HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_PID_Info));
1491
1492 *pu16matchpid = u16temp & TSO_PID_INFO_MATCH_PID_MASK;
1493 *pbchanged = (((u16temp & TSO_PID_INFO_MATCH_PID_CHANGE_MASK) > 0) ? TRUE: FALSE);
1494 */
1495 }
1496
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1497 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1498 {
1499 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1500 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1501
1502
1503 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1504 _HAL_REG32_W(LPCR2, u32lpcr2);
1505 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_WLD);
1506 }
1507
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1508 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1509 {
1510 MS_U32 u32temp = 0;
1511 REG32_TSO *LPCR2 = (u8FileEng == 0)? &(_TSOCtrl->LPCR2_BUF) : &(_TSOCtrl->LPCR2_BUF1);
1512 REG16_TSO *FILE_CONFIG = (u8FileEng == 0)? &(_TSOCtrl->TSO_FILE_CONFIG) : &(_TSOCtrl->TSO_FILE_CONFIG1);
1513
1514
1515 _REG16_SET(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1516 u32temp = _HAL_REG32_R(LPCR2);
1517 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_LPCR2_LOAD);
1518
1519 return u32temp;
1520 }
1521
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1522 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1523 {
1524 REG32_TSO *TIMESTAMP = (u8FileEng == 0)? &(_TSOCtrl->TIMESTAMP) : &(_TSOCtrl->TIMESTAMP1);
1525
1526 return _HAL_REG32_R(TIMESTAMP);
1527 }
1528
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1529 void HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1530 {
1531 switch(u8If)
1532 {
1533 case HAL_TSO_TSIF_LIVE1:
1534 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1535 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1536 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1537 break;
1538 case HAL_TSO_TSIF_LIVE2:
1539 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1540 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1541 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1542 break;
1543 case HAL_TSO_TSIF_LIVE3:
1544 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1545 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1546 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1547 break;
1548 case HAL_TSO_TSIF_LIVE4:
1549 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1550 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1551 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1552 break;
1553 case HAL_TSO_TSIF_LIVE5:
1554 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1555 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1556 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1557 break;
1558 case HAL_TSO_TSIF_LIVE6:
1559 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1560 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK)
1561 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK));
1562 break;
1563 default:
1564 printf("Not support !!\n");
1565 break;
1566 }
1567 }
1568
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1569 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1570 {
1571 if(bWrite)
1572 {
1573 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG3), *pu16PktSize);
1574 }
1575 else
1576 {
1577 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CONFIG3));
1578 }
1579
1580 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1581 _HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_PKT_PARAM_LD));
1582 }
1583
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1584 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1585 {
1586 switch(u8FileEng)
1587 {
1588 case 0:
1589 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1590 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN_MASK)
1591 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN_SHIFT)) & TSO_PKT_CHK_SIZE_FIN_MASK));
1592 break;
1593 case 1:
1594 _HAL_REG16_W(&(_TSOCtrl->PKT_CHK_SIZE_FIN),
1595 (_HAL_REG16_R(&(_TSOCtrl->PKT_CHK_SIZE_FIN)) & ~TSO_PKT_CHK_SIZE_FIN1_MASK)
1596 |(((MS_U16)(u8size << TSO_PKT_CHK_SIZE_FIN1_SHIFT)) & TSO_PKT_CHK_SIZE_FIN1_MASK));
1597 break;
1598 default:
1599 printf("Not support !!\n");
1600 break;
1601 }
1602 }
1603
HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1604 void HAL_TSO_Livein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1605 {
1606 switch(u8If)
1607 {
1608 case HAL_TSO_TSIF_LIVE1:
1609 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0),
1610 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG0)) & ~TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1611 |(((MS_U16)(u8size << TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1612 break;
1613 case HAL_TSO_TSIF_LIVE2:
1614 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0),
1615 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG0)) & ~TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1616 |(((MS_U16)(u8size << TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1617 break;
1618 case HAL_TSO_TSIF_LIVE3:
1619 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0),
1620 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG0)) & ~TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1621 |(((MS_U16)(u8size << TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1622 break;
1623 case HAL_TSO_TSIF_LIVE4:
1624 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0),
1625 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG0)) & ~TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1626 |(((MS_U16)(u8size << TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1627 break;
1628 case HAL_TSO_TSIF_LIVE5:
1629 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0),
1630 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG0)) & ~TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1631 |(((MS_U16)(u8size << TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1632 break;
1633 case HAL_TSO_TSIF_LIVE6:
1634 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0),
1635 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG0)) & ~TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK)
1636 |(((MS_U16)(u8size << TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK));
1637 break;
1638 default:
1639 printf("Not support !!\n");
1640 break;
1641 }
1642 }
1643
1644
HAL_TSO_Livein_Input_Config(MS_U8 u8Eng,MS_U8 u8PktInputMode,MS_U8 u8PktSyncByte,MS_U8 u8PktHeaderLength)1645 void HAL_TSO_Livein_Input_Config(MS_U8 u8Eng, MS_U8 u8PktInputMode, MS_U8 u8PktSyncByte, MS_U8 u8PktHeaderLength)
1646 {
1647 switch(u8Eng)
1648 {
1649 case HAL_TSO_TSIF_LIVE1:
1650 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1651 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK)
1652 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK));
1653
1654 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1655 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK)
1656 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK));
1657
1658 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1),
1659 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF1_CONFIG1)) & ~TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK)
1660 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK));
1661 break;
1662 case HAL_TSO_TSIF_LIVE2:
1663 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1664 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK)
1665 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK));
1666
1667 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1668 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK)
1669 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK));
1670
1671 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1),
1672 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF2_CONFIG1)) & ~TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK)
1673 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK));
1674 break;
1675 case HAL_TSO_TSIF_LIVE3:
1676 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1677 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK)
1678 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK));
1679
1680 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1681 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK)
1682 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK));
1683
1684 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1),
1685 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF3_CONFIG1)) & ~TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK)
1686 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK));
1687 break;
1688 case HAL_TSO_TSIF_LIVE4:
1689 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1690 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK)
1691 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK));
1692
1693 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1694 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK)
1695 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK));
1696
1697 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1),
1698 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF4_CONFIG1)) & ~TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK)
1699 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK));
1700 break;
1701 case HAL_TSO_TSIF_LIVE5:
1702 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1703 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK)
1704 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK));
1705
1706 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1707 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK)
1708 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK));
1709
1710 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1),
1711 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF5_CONFIG1)) & ~TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK)
1712 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK));
1713 break;
1714 case HAL_TSO_TSIF_LIVE6:
1715 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1716 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK)
1717 |(((MS_U16)(u8PktInputMode << TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK));
1718
1719 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1720 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK)
1721 |(((MS_U16)(u8PktSyncByte << TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK));
1722
1723 _HAL_REG16_W(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1),
1724 (_HAL_REG16_R(&(_TSOCtrl->CHANNEL0_IF6_CONFIG1)) & ~TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK)
1725 |(((MS_U16)(u8PktHeaderLength << TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT)) & TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK));
1726 break;
1727 default:
1728 printf("Not support !!\n");
1729 break;
1730 }
1731 }
1732
1733
HAL_TSO_Livein_3Wire(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1734 void HAL_TSO_Livein_3Wire(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1735 {
1736 if(bEnable)
1737 {
1738 switch(u8ChIf)
1739 {
1740 case HAL_TSO_TSIF_LIVE1:
1741 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1742 break;
1743 case HAL_TSO_TSIF_LIVE2:
1744 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1745 break;
1746 case HAL_TSO_TSIF_LIVE3:
1747 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1748 break;
1749 case HAL_TSO_TSIF_LIVE4:
1750 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1751 break;
1752 case HAL_TSO_TSIF_LIVE5:
1753 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1754 break;
1755 case HAL_TSO_TSIF_LIVE6:
1756 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1757 break;
1758 default:
1759 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1760 break;
1761 }
1762 }
1763 else
1764 {
1765 switch(u8ChIf)
1766 {
1767 case HAL_TSO_TSIF_LIVE1:
1768 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_1);
1769 break;
1770 case HAL_TSO_TSIF_LIVE2:
1771 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_2);
1772 break;
1773 case HAL_TSO_TSIF_LIVE3:
1774 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_3);
1775 break;
1776 case HAL_TSO_TSIF_LIVE4:
1777 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_4);
1778 break;
1779 case HAL_TSO_TSIF_LIVE5:
1780 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_5);
1781 break;
1782 case HAL_TSO_TSIF_LIVE6:
1783 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_3_WIRE_EN_6);
1784 break;
1785 default:
1786 HAL_TSO_DBGMSG(E_HAL_TSO_DBG_LEVEL_ERR, E_HAL_TSO_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] ChIf not support !!\n",__FUNCTION__,__LINE__));
1787 break;
1788 }
1789
1790 }
1791 }
1792
HAL_TSO_TsioMode_En(MS_BOOL bEnable)1793 void HAL_TSO_TsioMode_En(MS_BOOL bEnable)
1794 {
1795 if(bEnable)
1796 {
1797 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE);
1798 }
1799 else
1800 {
1801 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO_MODE);
1802 }
1803 }
1804
HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)1805 void HAL_TSO_Tsio2Opif_En(MS_BOOL bEnable)
1806 {
1807 if(bEnable)
1808 {
1809 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF);
1810 }
1811 else
1812 {
1813 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_REG_TSIO2OPIF);
1814 }
1815 }
1816
HAL_TSO_SerialMode_En(MS_BOOL bEnable)1817 void HAL_TSO_SerialMode_En(MS_BOOL bEnable)
1818 {
1819 if(bEnable)
1820 {
1821 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1822 }
1823 else
1824 {
1825 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1),TSO_CONFIG1_SERIAL_OUT_EN);
1826 }
1827 }
1828
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1829 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1830 {
1831 REG32_TSO *Base = NULL;
1832 REG16_TSO *Size = NULL, *TX_Config = NULL;
1833 // Check MIU select
1834 MS_U8 u8MiuSel;
1835 MS_PHY phyMiuOffsetSVQBuf;
1836 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSVQBuf, phyBufAddr);
1837 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQRX_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQRX_SHIFT) & REG_MIU_SEL_SVQRX_MASK));
1838
1839
1840 switch(u8ChIf)
1841 {
1842 case HAL_TSO_TSIF_LIVE1:
1843 Base = &(_TSOCtrl1->SVQ1_BASE);
1844 Size = &(_TSOCtrl1->SVQ1_SIZE_200BYTE);
1845 TX_Config = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1846 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX1_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX1_SHIFT) & REG_MIU_SEL_SVQTX1_MASK));
1847 break;
1848 case HAL_TSO_TSIF_LIVE2:
1849 Base = &(_TSOCtrl1->SVQ2_BASE);
1850 Size = &(_TSOCtrl1->SVQ2_SIZE_200BYTE);
1851 TX_Config = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1852 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX2_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX2_SHIFT) & REG_MIU_SEL_SVQTX2_MASK));
1853 break;
1854 case HAL_TSO_TSIF_LIVE3:
1855 Base = &(_TSOCtrl1->SVQ3_BASE);
1856 Size = &(_TSOCtrl1->SVQ3_SIZE_200BYTE);
1857 TX_Config = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1858 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX3_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX3_SHIFT) & REG_MIU_SEL_SVQTX3_MASK));
1859 break;
1860 case HAL_TSO_TSIF_LIVE4:
1861 Base = &(_TSOCtrl1->SVQ4_BASE);
1862 Size = &(_TSOCtrl1->SVQ4_SIZE_200BYTE);
1863 TX_Config = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1864 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX4_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX4_SHIFT) & REG_MIU_SEL_SVQTX4_MASK));
1865 break;
1866 case HAL_TSO_TSIF_LIVE5:
1867 Base = &(_TSOCtrl1->SVQ5_BASE);
1868 Size = &(_TSOCtrl1->SVQ5_SIZE_200BYTE);
1869 TX_Config = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1870 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX5_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX5_SHIFT) & REG_MIU_SEL_SVQTX5_MASK));
1871 break;
1872 case HAL_TSO_TSIF_LIVE6:
1873 Base = &(_TSOCtrl1->SVQ6_BASE);
1874 Size = &(_TSOCtrl1->SVQ6_SIZE_200BYTE);
1875 TX_Config = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1876 _HAL_REG16_W(&_TSOCtrl1->REG_TSO_MIU_SEL_1, (_HAL_REG16_R(&_TSOCtrl1->REG_TSO_MIU_SEL_1) & (~REG_MIU_SEL_SVQTX6_MASK)) | ((u8MiuSel << REG_MIU_SEL_SVQTX6_SHIFT) & REG_MIU_SEL_SVQTX6_MASK));
1877 break;
1878 default:
1879 printf("Not support !!\n");
1880 return FALSE;
1881 }
1882
1883 _HAL_REG32_W(Base, ((phyMiuOffsetSVQBuf >> TSO_MIU_BUS) & TSO1_SVQ1_BASE_MASK));
1884 _HAL_REG16_W(Size, ((u32BufSize / TSO_SVQ_UNIT_SIZE) & TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK));
1885 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1886 _REG16_CLR(TX_Config, TSO1_SVQ1_TX_CONFIG_TX_RESET);
1887 _REG16_SET(TX_Config, TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE);
1888
1889 return TRUE;
1890 }
1891
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1892 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1893 {
1894 REG16_TSO* p16Reg = NULL;
1895
1896 if(u8Eng > 0)
1897 {
1898 return FALSE;
1899 }
1900
1901 switch(u8ChIf)
1902 {
1903 case HAL_TSO_TSIF_LIVE1:
1904 p16Reg = &(_TSOCtrl1->SVQ1_TX_CONFIG);
1905 break;
1906 case HAL_TSO_TSIF_LIVE2:
1907 p16Reg = &(_TSOCtrl1->SVQ2_TX_CONFIG);
1908 break;
1909 case HAL_TSO_TSIF_LIVE3:
1910 p16Reg = &(_TSOCtrl1->SVQ3_TX_CONFIG);
1911 break;
1912 case HAL_TSO_TSIF_LIVE4:
1913 p16Reg = &(_TSOCtrl1->SVQ4_TX_CONFIG);
1914 break;
1915 case HAL_TSO_TSIF_LIVE5:
1916 p16Reg = &(_TSOCtrl1->SVQ5_TX_CONFIG);
1917 break;
1918 case HAL_TSO_TSIF_LIVE6:
1919 p16Reg = &(_TSOCtrl1->SVQ6_TX_CONFIG);
1920 break;
1921 default:
1922 printf("Not support !!\n");
1923 return FALSE;
1924 }
1925
1926 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1927 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET));
1928 return TRUE;
1929 }
1930
HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem,MS_BOOL benable)1931 void HAL_TSO1_SVQ_Rx_Enable(MS_U16 u16CfgItem, MS_BOOL benable)
1932 {
1933 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG));
1934
1935 if(benable)
1936 {
1937 u16data |= u16CfgItem;
1938 }
1939 else
1940 {
1941 u16data &= ~u16CfgItem;
1942 }
1943
1944 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), u16data);
1945 }
1946
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1947 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1948 {
1949 _HAL_REG16_W(&(_TSOCtrl1->SVQ_RX_CONFIG), (_HAL_REG16_R(&(_TSOCtrl1->SVQ_RX_CONFIG)) & ~TSO1_SVQ_RX_CONFIG_MODE_MASK) | u16mode);
1950
1951 return TRUE;
1952 }
1953
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1954 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1955 {
1956 MS_U32 u32data = 0;
1957 MS_U32 u32Shift = 0;
1958
1959 *pu16Status = 0;
1960 u32data = _HAL_REG32_R(&(_TSOCtrl1->SVQ_STATUS));
1961
1962 switch(u8ChIf)
1963 {
1964 case HAL_TSO_TSIF_LIVE1:
1965 u32Shift = TSO_SVQ1_STS_SHIFT;
1966 break;
1967 case HAL_TSO_TSIF_LIVE2:
1968 u32Shift = TSO_SVQ2_STS_SHIFT;
1969 break;
1970 case HAL_TSO_TSIF_LIVE3:
1971 u32Shift = TSO_SVQ3_STS_SHIFT;
1972 break;
1973 case HAL_TSO_TSIF_LIVE4:
1974 u32Shift = TSO_SVQ4_STS_SHIFT;
1975 break;
1976 case HAL_TSO_TSIF_LIVE5:
1977 u32Shift = TSO_SVQ5_STS_SHIFT;
1978 break;
1979 case HAL_TSO_TSIF_LIVE6:
1980 u32Shift = TSO_SVQ6_STS_SHIFT;
1981 break;
1982 default:
1983 return FALSE;
1984 }
1985
1986 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1987
1988 return TRUE;
1989 }
1990
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1991 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1992 {
1993 //@TODO not implement
1994 return TRUE;
1995 }
1996
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1997 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1998 {
1999 //@TODO not implement
2000 return TRUE;
2001 }
2002
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)2003 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
2004 {
2005 REG16_TSO* p16Reg = NULL;
2006
2007 switch(u8ChIf)
2008 {
2009 case HAL_TSO_TSIF_LIVE1:
2010 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_1_CONFIG_0);
2011 break;
2012 case HAL_TSO_TSIF_LIVE2:
2013 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_2_CONFIG_0);
2014 break;
2015 case HAL_TSO_TSIF_LIVE3:
2016 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_3_CONFIG_0);
2017 break;
2018 case HAL_TSO_TSIF_LIVE4:
2019 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_4_CONFIG_0);
2020 break;
2021 case HAL_TSO_TSIF_LIVE5:
2022 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_5_CONFIG_0);
2023 break;
2024 case HAL_TSO_TSIF_LIVE6:
2025 p16Reg = &(_TSOCtrl1->REG_PRE_HEADER_6_CONFIG_0);
2026 break;
2027 default:
2028 return FALSE;
2029 }
2030
2031 if(beSet == TRUE)
2032 {
2033 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2034 }
2035 else
2036 {
2037 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK);
2038 }
2039
2040 return TRUE;
2041
2042 }
2043
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)2044 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
2045 {
2046 MS_U16 u16Temp = 0;
2047
2048 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2049 u16Temp = (u16Temp & TSO_PIDFLT_PID_MASK) | ((u16InputSrc & TSO_PIDFLT_IN_MASK) << TSO_PIDFLT_IN_SHIFT);
2050 _HAL_TSO_PageTableIndW(TSO_PIDFLT_ADDR(u16FltId), u16Temp);
2051 }
2052
HAL_TSO_Flt_SetSid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8Sid)2053 void HAL_TSO_Flt_SetSid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8Sid)
2054 {
2055 MS_U16 u16Temp = 0;
2056
2057 u16Temp = _HAL_TSO_PageTableIndR(TSO_PIDFLT_ADDR(u16FltId));
2058 _HAL_TSO_PageTableIndW_withSid(TSO_PIDFLT_ADDR(u16FltId), u16Temp, u8Sid);
2059 }
2060
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)2061 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
2062 {
2063 //@TODO not implement
2064 return TRUE;
2065 }
2066
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)2067 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
2068 {
2069 //@TODO not implement
2070 return TRUE;
2071 }
2072
HAL_TSO_SaveRegs(void)2073 void HAL_TSO_SaveRegs(void)
2074 {
2075 //@TODO not implement
2076 }
2077
HAL_TSO_RestoreRegs(void)2078 void HAL_TSO_RestoreRegs(void)
2079 {
2080 //@TODO not implement
2081 }
2082
2083 #ifdef CONFIG_MSTAR_CLKM
HAL_TSO_PowerCtrl(MS_BOOL bOn)2084 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2085 {
2086 MS_S32 s32ClkHandle;
2087
2088 if (bOn)
2089 {
2090 // Enable TSO out Clock
2091 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2092 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOOUT_DIV");
2093
2094 // Enable TSO in Clock
2095 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2096 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSOIN0_PAD0");
2097
2098 // Enable TSO1 in Clock
2099 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2100 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN1_PAD0");
2101
2102 // Enable TSO2 in Clock
2103 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2104 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN2_PAD0");
2105
2106 // Enable TSO3 in Clock
2107 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2108 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN3_PAD0");
2109
2110 // Enable TSO4 in Clock
2111 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2112 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN4_PAD0");
2113
2114 // Enable TSO5 in Clock
2115 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2116 Drv_Clkm_Set_Clk_Source(s32ClkHandle , "CLK_TSIN5_PAD0");
2117
2118 // Disable MCM
2119 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2120 }
2121 else
2122 {
2123 // Enable MCM
2124 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2125
2126 // Disabel TSO out Clock
2127 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_out");
2128 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2129
2130 // Disabel TSO in Clock
2131 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso_in");
2132 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2133
2134 // Disabel TSO1 in Clock
2135 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso1_in");
2136 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2137
2138 // Disabel TSO2 in Clock
2139 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso2_in");
2140 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2141
2142 // Disabel TSO3 in Clock
2143 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso3_in");
2144 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2145
2146 // Disabel TSO4 in Clock
2147 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso4_in");
2148 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2149
2150 // Disabel TSO5 in Clock
2151 s32ClkHandle = Drv_Clkm_Get_Handle("g_clk_tso5_in");
2152 Drv_Clkm_Clk_Gate_Disable(s32ClkHandle);
2153 }
2154 }
2155 #else
HAL_TSO_PowerCtrl(MS_BOOL bOn)2156 void HAL_TSO_PowerCtrl(MS_BOOL bOn)
2157 {
2158 if (bOn)
2159 {
2160 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
2161 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2162 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2163 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2164 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2165 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2166 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) &= ~REG_CLKGEN0_TSO_IN_MASK;
2167
2168 // Disable MCM
2169 _REG16_SET(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2170 }
2171 else
2172 {
2173 // Enable MCM
2174 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG1), TSO_CONFIG1_TURN_OFF_MCM);
2175
2176 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
2177 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2178 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO1_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2179 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO2_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2180 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO3_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2181 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO4_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2182 TSO_CLKGEN2_REG(REG_CLKGEN2_TSO5_IN) |= REG_CLKGEN0_TSO_IN_DISABLE;
2183 }
2184 }
2185 #endif
2186
HAL_TSO_PcrFlt_Enable(MS_U8 u8ChIf,MS_U16 u16PID,MS_BOOL bEnable)2187 MS_BOOL HAL_TSO_PcrFlt_Enable(MS_U8 u8ChIf, MS_U16 u16PID, MS_BOOL bEnable)
2188 {
2189 if(bEnable)
2190 {
2191 _HAL_REG16_W(&(_TSOCtrl2->REG_TSO2_PIDFLT_PCR_CFG32_37[u8ChIf]), (TSO2_REG_PIDFLT_PCR_ENPCR | (TSO2_REG_PIDFLT_PCR_PID_MASK & u16PID)));
2192 }
2193 else
2194 {
2195 _HAL_REG16_W(&(_TSOCtrl2->REG_TSO2_PIDFLT_PCR_CFG32_37[u8ChIf]), (~TSO2_REG_PIDFLT_PCR_ENPCR | TSO2_REG_PIDFLT_PCR_PID_MASK));
2196 }
2197 return TRUE;
2198 }
2199
HAL_TSO_Pcr_Get(MS_U8 u8ChIf,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)2200 MS_BOOL HAL_TSO_Pcr_Get(MS_U8 u8ChIf, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
2201 {
2202
2203 switch(u8ChIf)
2204 {
2205 case HAL_TSO_TSIF_LIVE1:
2206 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_READ);
2207 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR1_LOW32_CFG38_39));
2208 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR1_VAILD_CFG3A)) & 0x1;
2209 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_READ);
2210 break;
2211
2212 case HAL_TSO_TSIF_LIVE2:
2213 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_READ);
2214 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR2_LOW32_CFG3B_3C));
2215 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR2_VAILD_CFG3D)) & 0x1;
2216 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_READ);
2217 break;
2218
2219 case HAL_TSO_TSIF_LIVE3:
2220 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_READ);
2221 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR3_LOW32_CFG3E_3F));
2222 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR3_VAILD_CFG40)) & 0x1;
2223 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_READ);
2224 break;
2225
2226 case HAL_TSO_TSIF_LIVE4:
2227 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_READ);
2228 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR4_LOW32_CFG41_42));
2229 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR4_VAILD_CFG43)) & 0x1;
2230 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_READ);
2231 break;
2232
2233 case HAL_TSO_TSIF_LIVE5:
2234 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR5_READ);
2235 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR5_LOW32_CFG44_45));
2236 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR5_VAILD_CFG46)) & 0x1;
2237 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR5_READ);
2238 break;
2239
2240 case HAL_TSO_TSIF_LIVE6:
2241 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR6_READ);
2242 *pu32Pcr = _HAL_REG32_R(&(_TSOCtrl2->REG_TSO2_PCR6_LOW32_CFG47_48));
2243 *pu32Pcr_H = _HAL_REG16_R(&(_TSOCtrl2->REG_TSO2_PCR6_VAILD_CFG49)) & 0x1;
2244 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR2_CFG31),TSO2_REG_PCR6_READ);
2245 break;
2246
2247 default:
2248 return FALSE;
2249 }
2250 return TRUE;
2251 }
2252
2253
HAL_TSO_PcrClr(MS_U8 u8ChIf,MS_BOOL bEnable)2254 MS_BOOL HAL_TSO_PcrClr(MS_U8 u8ChIf, MS_BOOL bEnable)
2255 {
2256 if(bEnable == TRUE)
2257 {
2258 switch(u8ChIf)
2259 {
2260 case HAL_TSO_TSIF_LIVE1:
2261 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_RESET);
2262 break;
2263 case HAL_TSO_TSIF_LIVE2:
2264 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_RESET);
2265 break;
2266 case HAL_TSO_TSIF_LIVE3:
2267 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_RESET);
2268 break;
2269 case HAL_TSO_TSIF_LIVE4:
2270 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_RESET);
2271 break;
2272 case HAL_TSO_TSIF_LIVE5:
2273 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR5_RESET);
2274 break;
2275 case HAL_TSO_TSIF_LIVE6:
2276 _REG16_CLR(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR6_RESET);
2277 break;
2278 default:
2279 return FALSE;
2280 }
2281 return TRUE;
2282 }
2283 else
2284 {
2285 switch(u8ChIf)
2286 {
2287 case HAL_TSO_TSIF_LIVE1:
2288 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR1_RESET);
2289 break;
2290 case HAL_TSO_TSIF_LIVE2:
2291 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR2_RESET);
2292 break;
2293 case HAL_TSO_TSIF_LIVE3:
2294 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR3_RESET);
2295 break;
2296 case HAL_TSO_TSIF_LIVE4:
2297 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR4_RESET);
2298 break;
2299 case HAL_TSO_TSIF_LIVE5:
2300 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR5_RESET);
2301 break;
2302 case HAL_TSO_TSIF_LIVE6:
2303 _REG16_SET(&(_TSOCtrl2->REG_TSO2_PCR_CFG30),TSO2_REG_PCR6_RESET);
2304 break;
2305 default:
2306 return FALSE;
2307 }
2308 return TRUE;
2309
2310 }
2311
2312 }
2313
2314
HAL_TSO_Set_SvqBypass(MS_BOOL bEnable)2315 MS_BOOL HAL_TSO_Set_SvqBypass(MS_BOOL bEnable)
2316 {
2317 if(bEnable)
2318 {
2319 _REG16_SET(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1);
2320 }
2321 else
2322 {
2323 _REG16_CLR(&(_TSOCtrl->TSO_CONFIG5),TSO_CONFIG5_BYPASS_SVQ_FOR_CH1);
2324 }
2325
2326 return TRUE;
2327 }
2328