1 //<MStar Software>
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSO.c
97 // @brief TS I/O HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSO.h"
101 #include "halCHIP.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106 #define TSP_HAL_REG_SAFE_MODE 1UL // Register protection access between 1 task and 1+ ISR
107
108 //-------------------------------------------------------------------------------------------------
109 // Local Structures
110 //-------------------------------------------------------------------------------------------------
111 typedef struct _HalTSO_OutPad
112 {
113 MS_U16 u16OutPad[TSO_ENGINE_NUM];
114 MS_U16 u16TSCfgOld[TSO_ENGINE_NUM];
115 MS_U16 u16TSOutModeOld[TSO_ENGINE_NUM];
116 } HalTSO_OutPad;
117
118 //--------------------------------------------------------------------------------------------------
119 // TSP Hardware Abstraction Layer
120 //--------------------------------------------------------------------------------------------------
121 static REG_Ctrl_TSO* _TSOCtrl = NULL;
122 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
123
124
125 static MS_VIRT _virtTSORegBase = 0;
126 static MS_PHY _phyTSOFiMiuOffset[TSO_FILE_IF_NUM] = {[0 ... (TSO_FILE_IF_NUM-1)] = 0UL};
127 static MS_PHY _phyTSOVQiMiuOffset = 0U;
128
129 static HalTSO_OutPad _stOutPadCtrl;
130
131 //[NOTE] Jerry
132 // Some register has write order, for example, writing PCR_L will disable PCR counter
133 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
134 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFFUL); \
135 (reg)->H = ((value) >> 16UL); } while(0)
136
137 #define _HAL_REG16_W(reg, value) (reg)->data = (value);
138
139 //--------------------------------------------------------------------------------------------------
140 // Macro of bit operations
141 //--------------------------------------------------------------------------------------------------
142 #define HAS_FLAG(flag, bit) ((flag) & (bit))
143 #define SET_FLAG(flag, bit) ((flag)|= (bit))
144 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
145 #define SET_FLAG1(flag, bit) ((flag)| (bit))
146 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
147
148 #define TSO_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1600UL + ((addr)<<2UL))))
149 #define REG_CLKGEN0_TSO_IN 0x27UL
150 #define REG_CLKGEN0_TSO_TRACE_MASK 0x000FUL
151 #define REG_CLKGEN0_TSO_TRACE_DISABLE 0x0001UL
152 #define REG_CLKGEN0_TSO_TRACE_INVERT 0x0002UL
153 #define REG_CLKGEN0_TSO_TRACE_216M 0x0000UL
154 #define REG_CLKGEN0_TSO_IN_MASK 0x1F00UL
155 #define REG_CLKGEN0_TSO_IN_SHIFT 8UL
156 #define REG_CLKGEN0_TSO_IN_DISABLE 0x0100UL
157 #define REG_CLKGEN0_TSO_IN_INVERT 0x0200UL
158 // bit[12:8] -> 0: disable clock
159 // 1: invert clock
160 // bit [4:2] -> 000: Sel TS0 Clk
161 // 001: Sel TS1 Clk
162 // 010: Sel TS2 Clk
163 // 011: Sel TS3 Clk
164 // 100: Sel TS4 Clk
165 // 101: Sel TS5 Clk
166 // 110: Sel Dmd Clk
167 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL
168 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x001FUL
169 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK 0x1F00UL
170 #define REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT 8UL
171
172 #define REG_CLKGEN0_TSO_OUT_CLK 0x7DUL
173 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL
174 // bit[0] -> 0: CLK_DMPLLDIV2
175 // 1: CLK_DMPLLDIV3
176 #define REG_CLKGEN0_TSO_OUT_INV 0x0002UL
177 #define REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE 0x0004UL
178 #define REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK 0x0070UL
179 #define REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT 4UL
180 // bit[6:4] -> 000:CLK_TS0_IN
181 // 001:CLK_TS1_IN
182 // 010:CLK_TS2_IN
183 // 011:CLK_TS3_IN
184 // 100:CLK_TS4_IN
185 // 101:CLK_TS5_IN
186 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x1F00UL
187 #define REG_CLKGEN0_TSO_OUT_CLK_DISABLE 0x0100UL
188 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL
189 // bit[12:8] -> 0: disable clock
190 // 1: invert clock
191 // bit [4:2] -> 000: TSO_OUT_DIV2 (clock/2N+1)
192 // 001: 62MHz
193 // 010: 54MHz
194 // 011: clk_p_tso_out (live in)
195 // 100: clk_p_tso_out_div8 (live in)
196 // 101: 27MHz
197 // 111: clk_demod_ts_p
198 #define REG_CLKGEN0_RESERVED0 0x7EUL
199 #define REG_CLKGEN0_RES0_CLKTSO_TOPAD_INV 0x8000UL
200 #define TSO_CLKGEN2_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x1400UL + ((addr)<<2UL))))
201 #define REG_CLKGEN2_TSO1_IN 0x10UL
202 #define REG_CLKGEN2_TSO1_IN_MASK 0x001FUL
203 #define REG_CLKGEN2_TSO1_IN_SHIFT 0UL
204 #define REG_CLKGEN2_TSO1_IN_DISABLE 0x0001UL
205 #define REG_CLKGEN2_TSO1_IN_INVERT 0x0002UL
206 // bit[4:0] -> 0: disable clock
207 // 1: invert clock
208 // bit [4:2] -> 000: Sel TS0 Clk
209 // 001: Sel TS1 Clk
210 // 010: Sel TS2 Clk
211 // 011: Sel TS3 Clk
212 // 100: Sel TS4 Clk
213 // 101: Sel TS5 Clk
214 // 111: Sel Dmd Clk
215 #define REG_CLKGEN2_TSO2_IN_MASK 0x1F00UL
216 #define REG_CLKGEN2_TSO2_IN_SHIFT 8UL
217 #define REG_CLKGEN2_TSO2_IN_DISABLE 0x0001UL
218 #define REG_CLKGEN2_TSO2_IN_INVERT 0x0002UL
219 // bit[12:8] -> 0: disable clock
220 // 1: invert clock
221 // bit [12:10] -> 000: Sel TS0 Clk
222 // 001: Sel TS1 Clk
223 // 010: Sel TS2 Clk
224 // 011: Sel TS3 Clk
225 // 100: Sel TS4 Clk
226 // 101: Sel TS5 Clk
227 // 111: Sel Dmd Clk
228 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x3c00UL + ((addr)<<2UL))))
229 #define REG_TOP_TSO_MUX 0x10UL
230 #define REG_TOP_TSO_EVDMODE_MASK 0x0600UL
231 #define REG_TOP_TS3_OUT_MODE_TSO 0x0400UL
232 #define REG_TOP_TSO_MUX_MASK 0x7000UL
233 #define REG_TOP_TSO_MUX_SHIFT 12UL
234 // bit[14:12] -> 000: PAD_TS0
235 // 001: PAD_TS1
236 // 010: PAD_TS2
237 // 011: PAD_TS3
238 // 100: PAD_TS4
239 // 101: PAD_TS5
240 // 111: DEMOD
241 #define REG_TOP_TSO1_MUX 0x14UL
242 #define REG_TOP_TSO1_MUX_MASK 0x0007UL
243 #define REG_TOP_TSO1_MUX_SHIFT 0UL
244 // bit[2:0] -> 000: PAD_TS0
245 // 001: PAD_TS1
246 // 010: PAD_TS2
247 // 011: PAD_TS3
248 // 100: PAD_TS4
249 // 101: PAD_TS5
250 // 111: DEMOD
251 #define REG_TOP_TSO2_MUX_MASK 0x0070UL
252 #define REG_TOP_TSO2_MUX_SHIFT 4UL
253 // bit[6:4] -> 000: PAD_TS0
254 // 001: PAD_TS1
255 // 010: PAD_TS2
256 // 011: PAD_TS3
257 // 100: PAD_TS4
258 // 101: PAD_TS5
259 // 111: DEMOD
260 #define REG_TOP_TS4TS5_CFG 0x40UL
261 #define REG_TOP_TS_OUT_MODE_MASK 0x0070UL
262 #define REG_TOP_TS1_OUT_MODE_TSO 0x0030UL
263 #define REG_TOP_TS1_OUT_MODE_Ser2Par 0x0040UL
264 #define REG_TOP_TS1_OUT_MODE_Ser2Par1 0x0050UL
265 #define REG_TOP_TS4_CFG_MASK 0x0C00UL
266 #define REG_TOP_TS4_CFG_SHIFT 10UL
267 #define REG_TOP_TS4_CFG_SERIAL_IN 0x0400UL
268 #define REG_TOP_TS4_CFG_PARALLEL_IN 0x0800UL
269 #define REG_TOP_TS5_CFG_MASK 0x3000UL
270 #define REG_TOP_TS5_CFG_SHIFT 12UL
271 #define REG_TOP_TS5_CFG_SERIAL_IN 0x1000UL
272
273 #define REG_TOP_TS_CONFIG 0x57UL
274 #define REG_TOP_TS0_CONFIG_MASK 0x0700UL
275 #define REG_TOP_TS0_CONFIG_PARALLEL_IN 0x0100UL
276 #define REG_TOP_TS0_CONFIG_SERIAL_IN 0x0200UL
277 #define REG_TOP_TS0_CONFIG_MSPI_MODE 0x0300UL
278 #define REG_TOP_TS0_CONFIG_3WIRE_MODE 0x0400UL
279 #define REG_TOP_TS1_CONFIG_MASK 0x3800UL
280 #define REG_TOP_TS1_CONFIG_PARALLEL_IN 0x0800UL
281 #define REG_TOP_TS1_CONFIG_PARALLEL_OUT 0x1000UL //out from demod
282 #define REG_TOP_TS1_CONFIG_SERIAL_IN 0x1800UL
283 #define REG_TOP_TS1_CONFIG_3WIRE_MODE 0x2000UL
284 #define REG_TOP_TS1_CONFIG_MSPI_MODE 0x2800UL
285 #define REG_TOP_TS2_CONFIG_MASK 0xC000UL
286 #define REG_TOP_TS2_CONFIG_PARALLEL_IN 0x8000UL
287 #define REG_TOP_TS2_CONFIG_SERIAL_IN 0x4000UL
288
289 #define REG_TOP_TS3_CONFIG 0x67UL
290 #define REG_TOP_TS3_CONFIG_MASK 0xF000UL
291 #define REG_TOP_TS3_CONFIG_SERIAL_IN 0x1000UL
292 #define REG_TOP_TS3_CONFIG_PARALLEL_IN 0x2000UL
293 #define REG_TOP_TS3_CONFIG_MSPI 0x3000UL
294 #define REG_TOP_TS3_CONFIG_PAROUT_DMD 0x5000UL
295 #define REG_TOP_TS3_CONFIG_PAROUT_Ser2Par 0x7000UL
296 #define REG_TOP_TS3_CONFIG_PAROUT_Ser2Par1 0x8000UL
297
298 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0xc7600 + ((addr)<<2))))
299 #define REG_TSP5_TSOIN_MUX 0x13UL
300 #define REG_TSP5_TSOIN_MUX_MASK 0x000FUL
301 #define REG_TSP5_TSOIN0_MUX_SHIFT 0UL
302 #define REG_TSP5_TSOIN1_MUX_SHIFT 4UL
303 #define REG_TSP5_TSOIN2_MUX_SHIFT 8UL
304 #define REG_TSP5_TSOOUT_MUX 0x15UL
305 #define REG_TSP5_TSOOUT_MUX_MASK 0x000FUL
306 #define REG_TSP5_TSOOUT_MUX_TSO 0x0000UL
307 #define REG_TSP5_TSOOUT_MUX_S2P0 0x0001UL
308
309 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x21600 + ((addr)<<2))))
310 #define REG_TSO_OUT_CLK_SEL 0x30UL
311 #define REG_TSO_OUT_CLK_SEL_MASK 1UL
312 #define REG_TSO_OUT_TSO 0x0000UL
313 #define REG_TSO_OUT_S2P 0x0001UL
314
315 //--------------------------------------------------------------------------------------------------
316 // Implementation
317 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32 * reg)318 static MS_U32 _HAL_REG32_R(REG32 *reg)
319 {
320 MS_U32 value = 0UL;
321 value = (reg)->H << 16UL;
322 value |= (reg)->L;
323 return value;
324 }
325
_HAL_REG16_R(REG16 * reg)326 static MS_U16 _HAL_REG16_R(REG16 *reg)
327 {
328 MS_U16 value = 0;
329 value = (reg)->data;
330 return value;
331 }
332
_HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)333 static MS_PHY _HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)
334 {
335 #ifdef HAL_MIU2_BASE
336 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
337 return ((MS_PHY)HAL_MIU2_BASE & 0xFFFFFFFFUL);
338 else
339 #endif //HAL_MIU2_BASE
340 #ifdef HAL_MIU1_BASE
341 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
342 return ((MS_PHY)HAL_MIU1_BASE & 0xFFFFFFFFUL);
343 else
344 #endif //HAL_MIU1_BASE
345 return ((MS_PHY)HAL_MIU0_BASE & 0xFFFFFFFFUL);
346 }
347
HAL_TSO_SetBank(MS_VIRT virtBankAddr)348 void HAL_TSO_SetBank(MS_VIRT virtBankAddr)
349 {
350 _virtTSORegBase = virtBankAddr;
351 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO);
352 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1);
353 }
354
HAL_TSO_REG32_IndR(REG32 * reg)355 static MS_U32 HAL_TSO_REG32_IndR(REG32 *reg)
356 {
357 MS_U32 u32tmp;
358 MS_VIRT virtReg = (MS_VIRT)reg;
359
360 u32tmp = ((MS_U32)virtReg)>> 1UL;
361
362 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
363 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_R_ENABLE)); // set command
364
365 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value
366
367 return u32tmp;
368 }
369
HAL_TSO_REG32_IndW(REG32 * reg,MS_U32 value)370 static void HAL_TSO_REG32_IndW(REG32 *reg, MS_U32 value)
371 {
372 MS_VIRT virtReg = (MS_VIRT)reg;
373 MS_U32 u32tmp = 0;
374
375 u32tmp = ((MS_U32)virtReg)>> 1;
376
377 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
378 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value
379 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_W_ENABLE)); // set command
380 }
381
382 //
383 // General API
384 //
HAL_TSO_Init(void)385 void HAL_TSO_Init(void)
386 {
387 MS_U8 u8ii = 0;
388
389 //select MIU0, and 128bit MIU bus
390 #if 0
391 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
392 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
393 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
394 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
395 #endif
396
397 for(u8ii = 0; u8ii < (MS_U8)TSO_ENGINE_NUM; u8ii++)
398 {
399 _stOutPadCtrl.u16OutPad[u8ii] = 0;
400 _stOutPadCtrl.u16TSCfgOld[u8ii] = 0;
401 _stOutPadCtrl.u16TSOutModeOld[u8ii] = 0;
402 }
403
404 //reset
405 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
406 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
407 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
408 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
409
410 //default local stream id
411 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER1_CFG0), 0x47);
412 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER5_CFG0), 0x47);
413 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER6_CFG0), 0x47);
414
415 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | TSO_SVQ_RX_CFG_MODE_CIPL);
416
417 // Set SVQ FIFO timeout value
418 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ1_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ1_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
419 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ5_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ5_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
420 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ6_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ6_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
421
422 }
423
HAL_TSO_Reset_All(MS_U8 u8Eng)424 void HAL_TSO_Reset_All(MS_U8 u8Eng)
425 {
426 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
427 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
428
429 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
430 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
431 }
432
HAL_TSO_Reset(MS_U8 u8Eng)433 void HAL_TSO_Reset(MS_U8 u8Eng)
434 {
435 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
436 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
437 }
438
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)439 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
440 {
441 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | u16RstItem));
442 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~u16RstItem));
443 }
444
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL bEnable,MS_U16 u16init)445 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL bEnable, MS_U16 u16init)
446 {
447 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt));
448
449 if(bEnable)
450 {
451 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data | u16init));
452 }
453 else
454 {
455 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data & ~u16init));
456 }
457 }
458
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)459 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
460 {
461 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & ~u16Int));
462 }
463
HAL_TSO_HWInt_Status(MS_U8 u8Eng)464 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
465 {
466 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & TSO_INT_STATUS_MASK);
467 }
468
HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)469 void HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)
470 {
471 switch(_stOutPadCtrl.u16OutPad[u8Eng])
472 {
473 case HAL_TSOOUT_MUX_TS1:
474 TSP_TOP_REG(REG_TOP_TS_CONFIG) = (TSP_TOP_REG(REG_TOP_TS_CONFIG) & ~REG_TOP_TS1_CONFIG_MASK) | _stOutPadCtrl.u16TSCfgOld[u8Eng];
475 TSP_TOP_REG(REG_TOP_TS4TS5_CFG) = (TSP_TOP_REG(REG_TOP_TS4TS5_CFG) & ~REG_TOP_TS_OUT_MODE_MASK) | _stOutPadCtrl.u16TSOutModeOld[u8Eng];
476 break;
477 case HAL_TSOOUT_MUX_TS3:
478 TSP_TOP_REG(REG_TOP_TS3_CONFIG) = TSP_TOP_REG(REG_TOP_TS3_CONFIG) & ~REG_TOP_TS3_CONFIG_MASK;
479 TSP_TOP_REG(REG_TOP_TSO_MUX) = (TSP_TOP_REG(REG_TOP_TSO_MUX) & ~REG_TOP_TSO_EVDMODE_MASK) | REG_TOP_TS3_OUT_MODE_TSO;
480 break;
481 default:
482 return;
483 }
484 }
485
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)486 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad, MS_BOOL bSet)
487 {
488 if(bSet)
489 {
490 switch(*pu16OutPad)
491 {
492 case HAL_TSOOUT_MUX_TS1:
493 _stOutPadCtrl.u16OutPad[u8Eng] = *pu16OutPad;
494 _stOutPadCtrl.u16TSCfgOld[u8Eng] = TSP_TOP_REG(REG_TOP_TS_CONFIG) & REG_TOP_TS1_CONFIG_MASK;
495 _stOutPadCtrl.u16TSOutModeOld[u8Eng] = TSP_TOP_REG(REG_TOP_TS4TS5_CFG) & REG_TOP_TS_OUT_MODE_MASK;
496 TSP_TOP_REG(REG_TOP_TS_CONFIG) = TSP_TOP_REG(REG_TOP_TS_CONFIG) & ~REG_TOP_TS1_CONFIG_MASK;
497 TSP_TOP_REG(REG_TOP_TS4TS5_CFG) = (TSP_TOP_REG(REG_TOP_TS4TS5_CFG) & ~REG_TOP_TS_OUT_MODE_MASK) | REG_TOP_TS1_OUT_MODE_TSO;
498 return TRUE;
499 case HAL_TSOOUT_MUX_TS3:
500 _stOutPadCtrl.u16OutPad[u8Eng] = *pu16OutPad;
501 _stOutPadCtrl.u16TSCfgOld[u8Eng] = TSP_TOP_REG(REG_TOP_TS3_CONFIG) & REG_TOP_TS3_CONFIG_MASK;
502 _stOutPadCtrl.u16TSOutModeOld[u8Eng] = TSP_TOP_REG(REG_TOP_TSO_MUX) & REG_TOP_TSO_EVDMODE_MASK;
503 TSP_TOP_REG(REG_TOP_TS3_CONFIG) = TSP_TOP_REG(REG_TOP_TS3_CONFIG) & ~REG_TOP_TS3_CONFIG_MASK;
504 TSP_TOP_REG(REG_TOP_TSO_MUX) = (TSP_TOP_REG(REG_TOP_TSO_MUX) & ~REG_TOP_TSO_EVDMODE_MASK) | REG_TOP_TS3_OUT_MODE_TSO;
505 return TRUE;
506 default:
507 return FALSE;
508 }
509 }
510 else
511 {
512 *pu16OutPad = HAL_TSOOUT_MUX_NONE;
513
514 if((TSP_TOP_REG(REG_TOP_TS4TS5_CFG) & REG_TOP_TS_OUT_MODE_MASK) == REG_TOP_TS1_OUT_MODE_TSO)
515 {
516 if((TSP_TOP_REG(REG_TOP_TS_CONFIG) & REG_TOP_TS1_CONFIG_MASK) == 0)
517 {
518 *pu16OutPad = HAL_TSOOUT_MUX_TS1;
519 }
520 }
521 else if((TSP_TOP_REG(REG_TOP_TSO_MUX) & REG_TOP_TSO_EVDMODE_MASK) == REG_TOP_TS3_OUT_MODE_TSO)
522 {
523 if((TSP_TOP_REG(REG_TOP_TS3_CONFIG) & REG_TOP_TS3_CONFIG_MASK) == 0)
524 {
525 *pu16OutPad = HAL_TSOOUT_MUX_TS3;
526 }
527 }
528
529 return TRUE;
530 }
531 }
532
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)533 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
534 {
535 MS_U16 u16Reg, u16RegMask, u16RegShift;
536 MS_U16 u16data = 0;
537
538 // Set pad mux
539 switch(u8TsIf)
540 {
541 case HAL_TSO_TSIF_LIVE1:
542 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT;
543 break;
544 case HAL_TSO_TSIF_LIVE2:
545 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT;
546 break;
547 case HAL_TSO_TSIF_LIVE3:
548 u16RegShift = REG_TSP5_TSOIN2_MUX_SHIFT;
549 break;
550 default:
551 return FALSE;
552 }
553
554 //set pad configure
555 switch(u16InPadSel)
556 {
557 case HAL_TSOIN_MUX_TS0:
558 u16Reg = REG_TOP_TS_CONFIG;
559 u16RegMask = REG_TOP_TS0_CONFIG_MASK;
560 if(bParallel)
561 {
562 u16data = REG_TOP_TS0_CONFIG_PARALLEL_IN;
563 }
564 else
565 {
566 u16data = REG_TOP_TS0_CONFIG_SERIAL_IN;
567 }
568 break;
569 case HAL_TSOIN_MUX_TS1:
570 u16Reg = REG_TOP_TS_CONFIG;
571 u16RegMask = REG_TOP_TS1_CONFIG_MASK;
572 if(bParallel)
573 {
574 u16data = REG_TOP_TS1_CONFIG_PARALLEL_IN;
575 }
576 else
577 {
578 u16data = REG_TOP_TS1_CONFIG_SERIAL_IN;
579 }
580 break;
581 case HAL_TSOIN_MUX_TS2:
582 u16Reg = REG_TOP_TS_CONFIG;
583 u16RegMask = REG_TOP_TS2_CONFIG_MASK;
584 if(bParallel)
585 {
586 u16data = REG_TOP_TS2_CONFIG_PARALLEL_IN;
587 }
588 else
589 {
590 u16data = REG_TOP_TS2_CONFIG_SERIAL_IN;
591 }
592 break;
593 case HAL_TSOIN_MUX_TS3:
594 u16Reg = REG_TOP_TS3_CONFIG;
595 u16RegMask = REG_TOP_TS3_CONFIG_MASK;
596 if(bParallel)
597 {
598 u16data = REG_TOP_TS3_CONFIG_PARALLEL_IN;
599 }
600 else
601 {
602 u16data = REG_TOP_TS3_CONFIG_SERIAL_IN;
603 }
604 break;
605 case HAL_TSOIN_MUX_TS4:
606 u16Reg = REG_TOP_TS4TS5_CFG;
607 u16RegMask = REG_TOP_TS4_CFG_MASK;
608 if(bParallel)
609 {
610 u16data = REG_TOP_TS4_CFG_PARALLEL_IN;
611 }
612 else
613 {
614 u16data = REG_TOP_TS4_CFG_SERIAL_IN;
615 }
616 break;
617 case HAL_TSOIN_MUX_TS5:
618 u16Reg = REG_TOP_TS4TS5_CFG;
619 u16RegMask = REG_TOP_TS5_CFG_MASK;
620 if(bParallel)
621 {
622 return FALSE;
623 }
624 else
625 {
626 u16data = REG_TOP_TS5_CFG_SERIAL_IN;
627 }
628 break;
629 case HAL_TSOIN_MUX_TSDEMOD0:
630 TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) = (TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
631 return TRUE;
632
633 default:
634 return FALSE;
635 }
636
637 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~u16RegMask) | u16data;
638
639 TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) = (TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK)) | (u16InPadSel << u16RegShift);
640
641 return TRUE;
642 }
643
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)644 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
645 {
646 MS_U16 u16Reg, u16RegMask, u16RegShift;
647 MS_U16 u16value = 0;
648
649 //printf("[%s] u8TsIf %x, u16ClkSel %d\n", __FUNCTION__, (int)u8TsIf, u16ClkSel);
650
651 //set clock
652 switch(u8TsIf)
653 {
654 case HAL_TSO_TSIF_LIVE1:
655 u16Reg = REG_CLKGEN0_TSO_IN;
656 u16RegMask = REG_CLKGEN0_TSO_IN_MASK;
657 u16RegShift = REG_CLKGEN0_TSO_IN_SHIFT;
658 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask;
659 break;
660 case HAL_TSO_TSIF_LIVE2:
661 u16Reg = REG_CLKGEN2_TSO1_IN;
662 u16RegMask = REG_CLKGEN2_TSO1_IN_MASK;
663 u16RegShift = REG_CLKGEN2_TSO1_IN_SHIFT;
664 u16value = TSO_CLKGEN2_REG(u16Reg) & ~u16RegMask;
665 break;
666 case HAL_TSO_TSIF_LIVE3:
667 u16Reg = REG_CLKGEN2_TSO1_IN;
668 u16RegMask = REG_CLKGEN2_TSO2_IN_MASK;
669 u16RegShift = REG_CLKGEN2_TSO2_IN_SHIFT;
670 u16value = TSO_CLKGEN2_REG(u16Reg) & ~u16RegMask;
671 break;
672 default:
673 return FALSE;
674 }
675
676 //printf("[%s] u16RegMask %x, u16RegShift %d\n", __FUNCTION__, u16RegMask, u16RegShift);
677
678 if(!bEnable)
679 {
680 u16value |= ((REG_CLKGEN2_TSO1_IN_DISABLE << u16RegShift) & 0xFFFFUL);
681 }
682 else
683 {
684 if(u16ClkSel > TSO_CLKIN_TS5)
685 {
686 return FALSE;
687 }
688
689 u16value |= (u16ClkSel << u16RegShift);
690 if(bClkInvert)
691 {
692 u16value |= ((REG_CLKGEN2_TSO1_IN_INVERT << u16RegShift) & 0xFFFFUL);
693 }
694 }
695
696 switch(u8TsIf)
697 {
698 case HAL_TSO_TSIF_LIVE1:
699 TSO_CLKGEN0_REG(u16Reg) = u16value;
700 break;
701 case HAL_TSO_TSIF_LIVE2:
702 case HAL_TSO_TSIF_LIVE3:
703 TSO_CLKGEN2_REG(u16Reg) = u16value;
704 break;
705 default:
706 return FALSE;
707 }
708
709 return TRUE;
710 }
711
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)712 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
713 {
714 MS_U16 u16Reg, u16RegMask, u16RegShift;
715 MS_U16 u16data = 0;
716 REG16* reg16 = 0;
717
718 // Set pad mux
719 switch(u8TsIf)
720 {
721 case HAL_TSO_TSIF_LIVE1:
722 u16Reg = REG_TOP_TSO_MUX;
723 u16RegMask = REG_TOP_TSO_MUX_MASK;
724 u16RegShift = REG_TOP_TSO_MUX_SHIFT;
725 break;
726 case HAL_TSO_TSIF_LIVE2:
727 u16Reg = REG_TOP_TSO1_MUX;
728 u16RegMask = REG_TOP_TSO1_MUX_MASK;
729 u16RegShift = REG_TOP_TSO1_MUX_SHIFT;
730 break;
731 case HAL_TSO_TSIF_LIVE3:
732 u16Reg = REG_TOP_TSO1_MUX;
733 u16RegMask = REG_TOP_TSO2_MUX_MASK;
734 u16RegShift = REG_TOP_TSO2_MUX_SHIFT;
735 break;
736 default:
737 return FALSE;
738 }
739
740 *pu16Pad = (TSP_TOP_REG(u16Reg) & u16RegMask) >> u16RegShift;
741
742 switch(u8TsIf)
743 {
744 case HAL_TSO_TSIF_LIVE1:
745 u16data = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & REG_CLKGEN0_TSO_IN_MASK) >> REG_CLKGEN0_TSO_IN_SHIFT;
746 reg16 = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
747 break;
748 case HAL_TSO_TSIF_LIVE2:
749 u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO1_IN_MASK) >> REG_CLKGEN2_TSO1_IN_SHIFT;
750 reg16 = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
751 break;
752 case HAL_TSO_TSIF_LIVE3:
753 u16data = (TSO_CLKGEN0_REG(REG_CLKGEN2_TSO1_IN) & REG_CLKGEN2_TSO2_IN_MASK) >> REG_CLKGEN2_TSO2_IN_SHIFT;
754 reg16 = &(_TSOCtrl->TSO_CH0_IF6_CFG2);
755 break;
756 default:
757 return FALSE;
758 }
759
760 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
761 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
762 *pbClkInvert = ((u16data & REG_CLKGEN2_TSO1_IN_INVERT) == REG_CLKGEN2_TSO1_IN_INVERT);
763
764 return TRUE;
765
766 }
767
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)768 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
769 {
770 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
771 {
772 return FALSE; //not support yet
773 }
774
775 switch(u16PadSel)
776 {
777 case HAL_TSOIN_MUX_TS0:
778 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
779 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
780 break;
781 case HAL_TSOIN_MUX_TS1:
782 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
783 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
784 break;
785 case HAL_TSOIN_MUX_TS2:
786 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
787 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
788 break;
789 case HAL_TSOIN_MUX_TS3:
790 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
791 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS3IN;
792 break;
793 case HAL_TSOIN_MUX_TS4:
794 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
795 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS4IN;
796 break;
797 case HAL_TSOIN_MUX_TS5:
798 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
799 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS5IN;
800 break;
801 case HAL_TSOIN_MUX_TSDEMOD0:
802 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
803 break;
804 case HAL_TSOIN_MUX_MEM:
805 case HAL_TSOIN_MUX_MEM1:
806 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV2N;
807 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
808 pstOutClkSet->u16OutDivNum = 0x0F; //default: 172.8/2(15+1) = 5.4M
809 break;
810 default:
811 return FALSE;
812 }
813
814 return TRUE;
815 }
816
817 // default: dmplldiv5 / 2 (11+1) = 7.2 MHz
818 // default: dmplldiv_3 / 2 (17+1) = 8 MHz
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)819 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
820 {
821 if(bSet == TRUE)
822 {
823 if(pstOutClkSet->bEnable == FALSE)
824 {
825 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
826 return;
827 }
828
829 switch(pstOutClkSet->u16OutClk)
830 {
831 case HAL_TSO_OUT_SEL_TSO_OUT_DIV2N:
832 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
833 break;
834 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
835 case HAL_TSO_OUT_SEL_TSO_OUT_54MHz:
836 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
837 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
838 break;
839 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
840 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
841 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
842 break;
843 default:
844 return;
845 }
846
847 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
848 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //alyays need TSO out clock
849 }
850 else
851 {
852 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
853 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV2N)
854 {
855 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
856 }
857 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
858 {
859 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
860 }
861 }
862 }
863
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)864 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
865 {
866 MS_U16 u16value = 0;
867
868 if(!bPhaseEnable)
869 {
870 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
871 }
872 else
873 {
874 u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK)
875 | (u16ClkOutPhase << REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_SHIFT);
876
877 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value;
878 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE;
879 }
880
881 return TRUE;
882 }
883
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)884 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
885 {
886 if(bSet == TRUE)
887 {
888 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS5IN)
889 {
890 return FALSE;
891 }
892
893 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) =
894 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSel << REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT);
895 }
896 else
897 {
898 *pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) >> REG_CLKGEN1_TSO_OUT_PRE_CLK_SHIFT;
899 }
900
901 return TRUE;
902 }
903
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)904 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16* pu16ClkOutDivSrcSel, MS_U16 *pu16ClkOutDivNum, MS_BOOL bSet)
905 {
906 //clock source for clock divide
907 if(bSet == TRUE)
908 {
909 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
910 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
911
912 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) =
913 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSrcSel);
914
915 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) =
916 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivNum);
917 }
918 else
919 {
920 *pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
921 *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK;
922 }
923
924 return TRUE;
925 }
926
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)927 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable, MS_BOOL bSet)
928 {
929 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
930
931 if(bSet == TRUE)
932 {
933 if(*pbEnable == FALSE)
934 {
935 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE;
936 }
937 else
938 {
939 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) =
940 (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN0_TSO_TRACE_216M;
941
942 u16Clk |= (*pu16ClkOutSel);
943
944 if(*pbClkInvert)
945 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT;
946
947 TSO_CLKGEN0_REG(REG_CLKGEN0_RESERVED0) |= REG_CLKGEN0_RES0_CLKTSO_TOPAD_INV;
948 }
949 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk;
950 }
951 else
952 {
953 *pbEnable = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_DISABLE) == 0);
954 *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT);
955 *pu16ClkOutSel = u16Clk;
956 }
957
958 return TRUE;
959 }
960
961 // ------------------------------------------------------
962 // APIS
963 //-------------------------------------------------------
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)964 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
965 {
966 MS_U32 u32value;
967 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
968
969 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_PID_MASK) | (((MS_U32)u16PID << TSO_PIDFLT_PID_SHFT) & TSO_PIDFLT_PID_MASK);
970 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
971 }
972
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)973 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
974 {
975 MS_U32 u32value;
976 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
977
978 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_IN_MASK) | (u16InputSrc << TSO_PIDFLT_IN_SHIFT);
979 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
980 }
981
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)982 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
983 {
984 REG32 *pReg = 0;
985 MS_U32 u32data = (((MS_U32)u16OldPid) & REP_PIDFLT_ORG_PID_MASK) | (((MS_U32)u8TsIf) << REP_PIDFLT_SRC_SHIFT) |
986 ((((MS_U32)u16NewPid) << REP_PIDFLT_NEW_PID_SHIFT) & REP_PIDFLT_NEW_PID_MASK);
987 pReg = &(_TSOCtrl->REP_PidFlt[u16FltId]);
988 _HAL_REG32_W(pReg, u32data);
989
990 return TRUE;
991 }
992
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)993 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
994 {
995 if(bEnable)
996 {
997 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), SET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
998 }
999 else
1000 {
1001 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
1002 }
1003
1004 return TRUE;
1005 }
1006
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_PHY phyAddr)1007 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_PHY phyAddr)
1008 {
1009 _phyTSOFiMiuOffset[u8FileEng] = _HAL_TSO_MIU_OFFSET(phyAddr);
1010
1011 if(u8FileEng == 0)
1012 {
1013 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_raddr), (MS_U32)(phyAddr-_phyTSOFiMiuOffset[u8FileEng]));
1014 }
1015 else if(u8FileEng == 1)
1016 {
1017 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_raddr1), (MS_U32)(phyAddr-_phyTSOFiMiuOffset[u8FileEng]));
1018 }
1019 }
1020
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)1021 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
1022 {
1023 if(u8FileEng == 0)
1024 {
1025 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_rNum), u32len);
1026 }
1027 else if(u8FileEng == 1)
1028 {
1029 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_rNum1), u32len);
1030 }
1031 }
1032
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)1033 MS_PHY HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
1034 {
1035 MS_PHY phyvalue = 0;
1036
1037 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_RADDR_READ);
1038 phyvalue = ((MS_PHY)_HAL_REG32_R(&(_TSOCtrl->TSO_TSO2MI_RADDR[u8FileEng])) & 0xFFFFFFFFUL) << TSO_MIU_BUS;
1039 phyvalue += _phyTSOFiMiuOffset[u8FileEng];
1040 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_RADDR_READ);
1041 return phyvalue;
1042 }
1043
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)1044 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
1045 {
1046 if(u8FileEng == 0)
1047 {
1048 _HAL_REG16_W(&(_TSOCtrl->TSO_Filein_Ctrl), (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1049 }
1050 else if(u8FileEng == 1)
1051 {
1052 _HAL_REG16_W(&(_TSOCtrl->TSO_Filein_Ctrl1), (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl1)) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
1053 }
1054 }
1055
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)1056 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
1057 {
1058 if(u8FileEng == 0)
1059 {
1060 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & TSO_FILEIN_CTRL_MASK);
1061 }
1062 else if(u8FileEng == 1)
1063 {
1064 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl1)) & TSO_FILEIN_CTRL_MASK);
1065 }
1066
1067 return 0;
1068 }
1069
HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng,MS_U32 u32Key,MS_BOOL bSecured)1070 MS_BOOL HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng, MS_U32 u32Key, MS_BOOL bSecured)
1071 {
1072 MS_U16 u16data = (bSecured ? TSO_FILEIN_RIU_TSO_NS : 0);
1073 REG16* pReg = ((u8FileEng == 0)? (&(_TSOCtrl->TSO_Filein_Ctrl)) : (&(_TSOCtrl->TSO_Filein_Ctrl1)));
1074
1075 if((_HAL_REG16_R(pReg) & (TSO_FILEIN_RSTART|TSO_FILEIN_ABORT)) != 0)
1076 {
1077 return FALSE;
1078 }
1079
1080 u16data |= ((MS_U16)(u32Key << TSO_FILEIN_MOBF_IDX_SHIFT) & TSO_FILEIN_MOBF_IDX_MASK);
1081 _HAL_REG16_W(pReg, u16data)
1082
1083 return TRUE;
1084 }
1085
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1086 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1087 {
1088 MS_U16 u16ChIf = ((u8Eng == 0)? TSO_CFG1_TSO_TSIF5_EN: TSO_CFG1_TSO_TSIF6_EN);
1089
1090 if(bEnable)
1091 {
1092 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf));
1093 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1094 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
1095 }
1096 else
1097 {
1098 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf));
1099 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1100 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
1101 }
1102
1103 return TRUE;
1104 }
1105
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1106 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1107 {
1108 if(bEnable)
1109 {
1110 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_TIMER_ENABLE);
1111 }
1112 else
1113 {
1114 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_TIMER_ENABLE);
1115 }
1116 }
1117
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)1118 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
1119 {
1120 _HAL_REG16_W(&(_TSOCtrl->TSO_FI_TIMER[u8FileEng]), u16timer);
1121 }
1122
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1123 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1124 {
1125 if(bEnable)
1126 {
1127 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
1128 }
1129 else
1130 {
1131 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1132 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
1133 }
1134 }
1135
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)1136 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
1137 {
1138 if(bEnable)
1139 {
1140 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1141 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
1142 }
1143 else
1144 {
1145 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
1146 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
1147 }
1148 }
1149
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)1150 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
1151 {
1152 MS_U16 u16Shift = ((u8FileEng == 0) ? 0: 8);
1153
1154 return ((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_WCNT_MASK);
1155 }
1156
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng,MS_U8 u8FileEng)1157 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng, MS_U8 u8FileEng)
1158 {
1159 MS_U16 u16Shift = ((u8FileEng == 0) ? 0: 8);
1160
1161 return (MS_BOOL)((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_FIFO_FULL);
1162 }
1163
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng,MS_U8 u8FileEng)1164 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng, MS_U8 u8FileEng)
1165 {
1166 MS_U16 u16Shift = ((u8FileEng == 0) ? 0: 8);
1167
1168 return (MS_BOOL)((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_FIFO_EMPTY);
1169 }
1170
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1171 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1172 {
1173 MS_U16 u16Shift = ((u8FileEng == 0) ? 0: 8);
1174
1175 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_WLEVEL_MASK);
1176 }
1177
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1178 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1179 {
1180 MS_U16 u16data = ((u8FileEng == 0)? TSO_SW_RSTZ_CMDQ : TSO_SW_RSTZ_CMDQ1);
1181
1182 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1183 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1184 return TRUE;
1185 }
1186
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1187 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1188 {
1189 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1190
1191 if(bWrite)
1192 {
1193 u16data &= ~TSO_CFG2_VALID_BYTECNT_MASK;
1194 u16data |= (*pu16ValidBlockCnt << TSO_CFG2_VALID_BYTECNT_SHIFT);
1195 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1196
1197 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1198 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1199 }
1200 else
1201 {
1202 *pu16ValidBlockCnt = (u16data & TSO_CFG2_VALID_BYTECNT_MASK) >> TSO_CFG2_VALID_BYTECNT_SHIFT;
1203 }
1204 }
1205
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1206 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1207 {
1208 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1209
1210 if(bWrite)
1211 {
1212 u16data &= ~TSO_CFG2_INVALID_BYTECNT_MASK;
1213 u16data |= (*pu16InvalidBlockCnt << TSO_CFG2_INVALID_BYTECNT_SHIFT);
1214 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1215
1216 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1217 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1218 }
1219 else
1220 {
1221 *pu16InvalidBlockCnt = u16data & TSO_CFG2_INVALID_BYTECNT_MASK;
1222 }
1223 }
1224
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1225 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1226 {
1227 if(bWrite)
1228 {
1229 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG3), *pu16PktSize);
1230 }
1231 else
1232 {
1233 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG3));
1234 }
1235
1236 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1237 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1238 }
1239
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1240 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1241 {
1242 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1243
1244 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp | TSO_FICFG_LPCR2_WLD);
1245 _HAL_REG32_W(&(_TSOCtrl->TSO_LPCR2[u8FileEng]), u32lpcr2);
1246 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1247 }
1248
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1249 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1250 {
1251 MS_U32 u32temp = 0;
1252 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1253
1254 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), ((u16temp & ~TSO_FICFG_LPCR2_WLD)|TSO_FICFG_LPCR2_LD));
1255 u32temp = _HAL_REG32_R(&_TSOCtrl->TSO_LPCR2[u8FileEng]);
1256 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1257
1258 return u32temp;
1259 }
1260
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1261 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1262 {
1263 return _HAL_REG32_R(&(_TSOCtrl->TSO_TIMESTAMP[u8FileEng]));
1264 }
1265
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1266 MS_BOOL HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1267 {
1268 MS_U16 u16data = 0;
1269
1270 if(u8If == HAL_TSO_TSIF_LIVE1)
1271 {
1272 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF1_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1273 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF1_CFG0), u16data | (MS_U16)u8size);
1274 }
1275 else if((u8If == HAL_TSO_TSIF_LIVE2) || (u8If == HAL_TSO_TSIF_FILE1))
1276 {
1277 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF5_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1278 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF5_CFG0), u16data | (MS_U16)u8size);
1279 }
1280 else if((u8If == HAL_TSO_TSIF_LIVE3) || (u8If == HAL_TSO_TSIF_FILE2))
1281 {
1282 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF6_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1283 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF6_CFG0), u16data | (MS_U16)u8size);
1284 }
1285 else
1286 {
1287 return FALSE;
1288 }
1289
1290 return TRUE;
1291 }
1292
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1293 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1294 {
1295 MS_U16 u16temp = 0, u16shift = ((u8FileEng == 0) ? 0: 8);
1296
1297 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI)) & ~(TSO_PKT_CHKSIZE_FI_MASK << u16shift);
1298 u16temp |= (((MS_U16)(u8size & 0xFF)) << u16shift);
1299
1300 _HAL_REG16_W(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI), u16temp);
1301 }
1302
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1303 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1304 {
1305 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG1));
1306
1307 if(bEnable)
1308 {
1309 u16data |= u16CfgItem;
1310 }
1311 else
1312 {
1313 u16data &= ~u16CfgItem;
1314 }
1315
1316 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), u16data);
1317 }
1318
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1319 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1320 {
1321 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG4));
1322
1323 if(bEnable)
1324 {
1325 u16data |= u16CfgItem;
1326 }
1327 else
1328 {
1329 u16data &= ~u16CfgItem;
1330 }
1331
1332 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4), u16data);
1333 }
1334
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1335 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1336 {
1337 MS_U16 u16data = 0;
1338
1339 if(u8Eng > 0)
1340 {
1341 return FALSE;
1342 }
1343
1344 switch(u8ChIf)
1345 {
1346 case HAL_TSO_TSIF_LIVE1:
1347 u16data = TSO_CFG1_TSO_TSIF1_EN;
1348 break;
1349 case HAL_TSO_TSIF_LIVE2:
1350 u16data = TSO_CFG1_TSO_TSIF5_EN;
1351 break;
1352 case HAL_TSO_TSIF_LIVE3:
1353 u16data = TSO_CFG1_TSO_TSIF6_EN;
1354 break;
1355 default:
1356 return FALSE;
1357 }
1358
1359 if(bEnable)
1360 {
1361 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16data));
1362 }
1363 else
1364 {
1365 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16data));
1366 }
1367
1368 return FALSE;
1369
1370 }
1371
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1372 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1373 {
1374 REG16* pReg = NULL;
1375
1376 if(u8Eng > 0)
1377 {
1378 return FALSE;
1379 }
1380
1381 switch(u8ChIf)
1382 {
1383 case HAL_TSO_TSIF_LIVE1:
1384 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1385 break;
1386 case HAL_TSO_TSIF_LIVE2:
1387 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1388 break;
1389 case HAL_TSO_TSIF_LIVE3:
1390 pReg = &(_TSOCtrl->TSO_CH0_IF6_CFG2);
1391 break;
1392 default:
1393 return FALSE;
1394 }
1395
1396 if(bEnable)
1397 {
1398 _HAL_REG16_W(pReg, SET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1399 }
1400 else
1401 {
1402 _HAL_REG16_W(pReg, RESET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1403 }
1404
1405 return TRUE;
1406 }
1407
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1408 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1409 {
1410 REG16* pReg = NULL;
1411 MS_U16 u16data = 0;
1412
1413 *pu16Cfg = 0;
1414 *pbEnable = FALSE;
1415
1416 if(u8Eng > 0)
1417 {
1418 return FALSE;
1419 }
1420
1421 switch(u8ChIf)
1422 {
1423 case HAL_TSO_TSIF_LIVE1:
1424 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1425 break;
1426 case HAL_TSO_TSIF_LIVE2:
1427 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1428 break;
1429 case HAL_TSO_TSIF_LIVE3:
1430 pReg = &(_TSOCtrl->TSO_CH0_IF6_CFG2);
1431 break;
1432 default:
1433 return FALSE;
1434 }
1435
1436 *pu16Cfg = _HAL_REG16_R(pReg);
1437
1438 switch(u8ChIf)
1439 {
1440 case HAL_TSO_TSIF_LIVE1:
1441 u16data = TSO_CFG1_TSO_TSIF1_EN;
1442 break;
1443 case HAL_TSO_TSIF_LIVE2:
1444 u16data = TSO_CFG1_TSO_TSIF5_EN;
1445 break;
1446 case HAL_TSO_TSIF_LIVE3:
1447 u16data = TSO_CFG1_TSO_TSIF6_EN;
1448 break;
1449 default:
1450 return FALSE;
1451 }
1452
1453 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)) & u16data) == u16data);
1454
1455 return TRUE;
1456
1457 }
1458
1459
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1460 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1461 {
1462 REG32* p32Reg = NULL;
1463 REG16* p16Reg = NULL;
1464 REG16* p16RegCfg = NULL;
1465 MS_U32 u32addr = 0;
1466
1467 _phyTSOVQiMiuOffset = _HAL_TSO_MIU_OFFSET(phyBufAddr);
1468 u32addr = (MS_U32)(phyBufAddr - _phyTSOVQiMiuOffset);
1469
1470 if(u8Eng > 0)
1471 {
1472 return FALSE;
1473 }
1474
1475 switch(u8ChIf)
1476 {
1477 case HAL_TSO_TSIF_LIVE1:
1478 p32Reg = &(_TSOCtrl1->TSO_SVQ1_BASE);
1479 p16Reg = &(_TSOCtrl1->TSO_SVQ1_SIZE);
1480 p16RegCfg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1481 break;
1482 case HAL_TSO_TSIF_LIVE2:
1483 p32Reg = &(_TSOCtrl1->TSO_SVQ5_BASE);
1484 p16Reg = &(_TSOCtrl1->TSO_SVQ5_SIZE);
1485 p16RegCfg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1486 break;
1487 case HAL_TSO_TSIF_LIVE3:
1488 p32Reg = &(_TSOCtrl1->TSO_SVQ6_BASE);
1489 p16Reg = &(_TSOCtrl1->TSO_SVQ6_SIZE);
1490 p16RegCfg = &(_TSOCtrl1->TSO_SVQ6_TX_CFG);
1491 break;
1492 default:
1493 return FALSE;
1494 }
1495
1496 _HAL_REG32_W(p32Reg, u32addr >> TSO_MIU_BUS);
1497 _HAL_REG16_W(p16Reg , u32BufSize/TSO_SVQ_UNIT_SIZE);
1498
1499 // Reset SVQ
1500 _HAL_REG16_W(p16RegCfg , SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1501 _HAL_REG16_W(p16RegCfg , RESET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1502
1503 _HAL_REG16_W(p16RegCfg, SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_SVQ_EN));
1504
1505 return TRUE;
1506 }
1507
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1508 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1509 {
1510 MS_U16 u16data = 0;
1511
1512 switch(u8ChIf)
1513 {
1514 case HAL_TSO_TSIF_LIVE1:
1515 u16data = TSO_CLR_BYTE_CNT_1;
1516 break;
1517 case HAL_TSO_TSIF_LIVE2:
1518 u16data = TSO_CLR_BYTE_CNT_5;
1519 break;
1520 case HAL_TSO_TSIF_LIVE3:
1521 u16data = TSO_CLR_BYTE_CNT_6;
1522 break;
1523 default:
1524 return FALSE;
1525 }
1526
1527
1528 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1529 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1530
1531 return TRUE;
1532 }
1533
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1534 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1535 {
1536 REG16* p16Reg = NULL;
1537
1538 if(beSet == FALSE)
1539 {
1540 *pu8StrID = 0xFF;
1541 }
1542
1543 if(u8Eng > 0)
1544 {
1545 return FALSE;
1546 }
1547
1548 switch(u8ChIf)
1549 {
1550 case HAL_TSO_TSIF_LIVE1:
1551 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER1_CFG0);
1552 break;
1553 case HAL_TSO_TSIF_LIVE2:
1554 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER5_CFG0);
1555 break;
1556 case HAL_TSO_TSIF_LIVE3:
1557 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER6_CFG0);
1558 break;
1559 default:
1560 return FALSE;
1561 }
1562
1563 if(beSet == TRUE)
1564 {
1565 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & 0xFF);
1566 }
1567 else
1568 {
1569 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & 0xFF);
1570 }
1571
1572 return TRUE;
1573
1574 }
1575
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1576 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1577 {
1578 REG16* p16Reg = NULL;
1579
1580 if(u8Eng > 0)
1581 {
1582 return FALSE;
1583 }
1584
1585 switch(u8ChIf)
1586 {
1587 case HAL_TSO_TSIF_LIVE1:
1588 p16Reg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1589 break;
1590 case HAL_TSO_TSIF_LIVE2:
1591 p16Reg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1592 break;
1593 case HAL_TSO_TSIF_LIVE3:
1594 p16Reg = &(_TSOCtrl1->TSO_SVQ6_TX_CFG);
1595 break;
1596 default:
1597 return FALSE;
1598 }
1599
1600 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1601 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1602
1603 return TRUE;
1604
1605 }
1606
HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng,MS_U32 u32Key,MS_BOOL bSecured)1607 MS_BOOL HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng, MS_U32 u32Key, MS_BOOL bSecured)
1608 {
1609 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK;
1610
1611 u16data |= ((MS_U16)(u32Key << TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT) & TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK);
1612
1613 if(bSecured)
1614 {
1615 u16data |= TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1616 }
1617 else
1618 {
1619 u16data &= ~TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1620 }
1621
1622 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), u16data);
1623
1624 return TRUE;
1625 }
1626
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1627 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1628 {
1629 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | u16mode);
1630
1631 return TRUE;
1632 }
1633
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1634 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1635 {
1636 MS_U8 u8ii = 0, u8jj = 0;
1637 MS_U16 u16shift = 0;
1638
1639 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_ARBMODE_MASK) | u16mode);
1640
1641 if(u16mode != TSO_SVQ_RX_CFG_ARBMODE_FIXPRI)
1642 {
1643 return TRUE;
1644 }
1645
1646 for(u8ii = 0; u8ii < TSO_SVQ_RX_NUM; u8ii++)
1647 {
1648 u8jj = u8ii >> 1;
1649 u16shift = ((u8ii % 2) ? TSO_SVQ_RX_PRI_SHIFT: 0);
1650
1651 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj]),
1652 (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj])) & ~(TSO_SVQ_RX_PRI_MASK << u16shift)) | (pu16SvqRxPri[u8ii] << u16shift));
1653 }
1654
1655 return TRUE;
1656 }
1657
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1658 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1659 {
1660 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1661 _HAL_REG32_W(&(_TSOCtrl->TSO_SYSTIMESTAMP), u32systime);
1662 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1663
1664 return FALSE;
1665 }
1666
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1667 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1668 {
1669 MS_U32 u32data = 0;
1670 MS_U32 u32Shift = 0;
1671
1672 *pu16Status = 0;
1673
1674 if(u8Eng > 0)
1675 {
1676 return FALSE;
1677 }
1678
1679 u32data = _HAL_REG32_R(&(_TSOCtrl1->TSO_SVQ_STATUS));
1680
1681 switch(u8ChIf)
1682 {
1683 case HAL_TSO_TSIF_LIVE1:
1684 u32Shift = 0;
1685 break;
1686 case HAL_TSO_TSIF_LIVE2:
1687 u32Shift = 16;
1688 break;
1689 case HAL_TSO_TSIF_LIVE3:
1690 u32Shift = 20;
1691 break;
1692 default:
1693 return FALSE;
1694 }
1695
1696 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1697
1698 return TRUE;
1699
1700 }
1701
HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U32 * pu32time)1702 MS_BOOL HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U32 *pu32time)
1703 {
1704 *pu32time = 0;
1705
1706 if(u8Eng > 0)
1707 {
1708 return FALSE;
1709 }
1710
1711 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1712 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1713
1714 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) ,
1715 (_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & ~TSO_DELTA_CFG_SEL_CH_MASK) | u8ChIf);
1716
1717 *pu32time = _HAL_REG32_R(&(_TSOCtrl1->TSO_DELTA));
1718
1719 return TRUE;
1720 }
1721
HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng,MS_U8 * pu8ChIf)1722 MS_BOOL HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng, MS_U8 *pu8ChIf)
1723 {
1724 *pu8ChIf = 0xFF;
1725
1726 *pu8ChIf = (MS_U8)((_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & TSO_DELTA_CFG_MAX_ID_MASK) >> TSO_DELTA_CFG_MAX_ID_SHIFT);
1727
1728 return TRUE;
1729 }
1730
HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng,MS_U16 u16ClkBase)1731 MS_BOOL HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng, MS_U16 u16ClkBase)
1732 {
1733 if(u16ClkBase == HAL_TSO_TIMESTAMP_27M)
1734 {
1735 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_27M));
1736 }
1737 else
1738 {
1739 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_BASE_MASK));
1740 }
1741
1742 return TRUE;
1743 }
1744
1745
1746
1747