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Searched refs:hw_regs (Results 1 – 20 of 20) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c142 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu382H265dRegSet)); in hal_h265d_vdpu382_init()
150 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu382_init()
199 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu382_deinit()
222 Vdpu382H265dRegSet *hw_reg = (Vdpu382H265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v382_output_pps_packet()
439 Vdpu382H265dRegSet *hw_regs, in h265d_refine_rcb_size() argument
514 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
523 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
542 Vdpu382H265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
563 h265d_refine_rcb_size((Vdpu382RcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
654 Vdpu382H265dRegSet *hw_regs; in hal_h265d_vdpu382_gen_regs() local
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H A Dhal_h265d_vdpu384a.c131 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu384aH265dRegSet)); in hal_h265d_vdpu384a_init()
140 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu384a_init()
179 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu384a_deinit()
349 Vdpu384aH265dRegSet *hw_reg = (Vdpu384aH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
722 Vdpu384aH265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
732 (void)hw_regs; in hal_h265d_rcb_info_update()
783 Vdpu384aH265dRegSet *hw_regs; in hal_h265d_vdpu384a_gen_regs() local
813 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu384a_gen_regs()
842 hw_regs = (Vdpu384aH265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu384a_gen_regs()
843 memset(hw_regs, 0, sizeof(Vdpu384aH265dRegSet)); in hal_h265d_vdpu384a_gen_regs()
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H A Dhal_h265d_vdpu383.c154 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu383H265dRegSet)); in hal_h265d_vdpu383_init()
164 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu383_init()
210 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu383_deinit()
381 Vdpu383H265dRegSet *hw_reg = (Vdpu383H265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
726 Vdpu383H265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
736 (void)hw_regs; in hal_h265d_rcb_info_update()
862 Vdpu383H265dRegSet *hw_regs; in hal_h265d_vdpu383_gen_regs() local
894 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu383_gen_regs()
930 hw_regs = (Vdpu383H265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu383_gen_regs()
931 memset(hw_regs, 0, sizeof(Vdpu383H265dRegSet)); in hal_h265d_vdpu383_gen_regs()
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H A Dhal_h265d_vdpu34x.c144 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xH265dRegSet)); in hal_h265d_vdpu34x_init()
152 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu34x_init()
206 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu34x_deinit()
229 Vdpu34xH265dRegSet *hw_reg = (Vdpu34xH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
668 Vdpu34xH265dRegSet *hw_regs, in h265d_refine_rcb_size() argument
742 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
751 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
771 Vdpu34xH265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
792 h265d_refine_rcb_size((Vdpu34xRcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
844 Vdpu34xH265dRegSet *hw_regs; in hal_h265d_vdpu34x_gen_regs() local
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H A Dhal_h265d_rkv.c48 reg_ctx->g_buf[i].hw_regs = in hal_h265d_alloc_res()
73 reg_ctx->hw_regs = mpp_calloc_size(void, sizeof(H265d_REGS_t)); in hal_h265d_alloc_res()
127 if (reg_ctx->g_buf[i].hw_regs) { in hal_h265d_release_res()
128 mpp_free(reg_ctx->g_buf[i].hw_regs); in hal_h265d_release_res()
129 reg_ctx->g_buf[i].hw_regs = NULL; in hal_h265d_release_res()
156 if (reg_ctx->hw_regs) { in hal_h265d_release_res()
157 mpp_free(reg_ctx->hw_regs); in hal_h265d_release_res()
158 reg_ctx->hw_regs = NULL; in hal_h265d_release_res()
731 H265d_REGS_t *hw_regs; in hal_h265d_rkv_gen_regs() local
760 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_rkv_gen_regs()
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H A Dhal_h265d_ctx.h22 void* hw_regs; member
56 void* hw_regs; member
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_rkv.c40 void* hw_regs; member
63 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS)); in hal_vp9d_alloc_res()
90 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS)); in hal_vp9d_alloc_res()
152 if (hw_ctx->g_buf[i].hw_regs) { in hal_vp9d_release_res()
153 mpp_free(hw_ctx->g_buf[i].hw_regs); in hal_vp9d_release_res()
154 hw_ctx->g_buf[i].hw_regs = NULL; in hal_vp9d_release_res()
186 if (hw_ctx->hw_regs) { in hal_vp9d_release_res()
187 mpp_free(hw_ctx->hw_regs); in hal_vp9d_release_res()
188 hw_ctx->hw_regs = NULL; in hal_vp9d_release_res()
282 hw_ctx->hw_regs = hw_ctx->g_buf[i].hw_regs; in hal_vp9d_rkv_gen_regs()
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H A Dhal_vp9d_vdpu34x.c54 void* hw_regs; member
108 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet)); in hal_vp9d_alloc_res()
116 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet)); in hal_vp9d_alloc_res()
163 if (hw_ctx->g_buf[i].hw_regs) { in hal_vp9d_release_res()
164 mpp_free(hw_ctx->g_buf[i].hw_regs); in hal_vp9d_release_res()
165 hw_ctx->g_buf[i].hw_regs = NULL; in hal_vp9d_release_res()
184 if (hw_ctx->hw_regs) { in hal_vp9d_release_res()
185 mpp_free(hw_ctx->hw_regs); in hal_vp9d_release_res()
186 hw_ctx->hw_regs = NULL; in hal_vp9d_release_res()
331 static void hal_vp9d_rcb_info_update(void *hal, Vdpu34xVp9dRegSet *hw_regs, void *data) in hal_vp9d_rcb_info_update() argument
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H A Dhal_vp9d_vdpu382.c54 void* hw_regs; member
108 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu382Vp9dRegSet)); in hal_vp9d_alloc_res()
116 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu382Vp9dRegSet)); in hal_vp9d_alloc_res()
164 if (hw_ctx->g_buf[i].hw_regs) { in hal_vp9d_release_res()
165 mpp_free(hw_ctx->g_buf[i].hw_regs); in hal_vp9d_release_res()
166 hw_ctx->g_buf[i].hw_regs = NULL; in hal_vp9d_release_res()
185 if (hw_ctx->hw_regs) { in hal_vp9d_release_res()
186 mpp_free(hw_ctx->hw_regs); in hal_vp9d_release_res()
187 hw_ctx->hw_regs = NULL; in hal_vp9d_release_res()
343 static void hal_vp9d_rcb_info_update(void *hal, Vdpu382Vp9dRegSet *hw_regs, void *data) in hal_vp9d_rcb_info_update() argument
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H A Dhal_vp9d_vdpu383.c48 void* hw_regs; member
145 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu383Vp9dRegSet)); in hal_vp9d_alloc_res()
169 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu383Vp9dRegSet)); in hal_vp9d_alloc_res()
254 if (hw_ctx->g_buf[i].hw_regs) { in hal_vp9d_release_res()
255 mpp_free(hw_ctx->g_buf[i].hw_regs); in hal_vp9d_release_res()
256 hw_ctx->g_buf[i].hw_regs = NULL; in hal_vp9d_release_res()
288 if (hw_ctx->hw_regs) { in hal_vp9d_release_res()
289 mpp_free(hw_ctx->hw_regs); in hal_vp9d_release_res()
290 hw_ctx->hw_regs = NULL; in hal_vp9d_release_res()
443 static void hal_vp9d_rcb_info_update(void *hal, Vdpu383Vp9dRegSet *hw_regs, void *data) in hal_vp9d_rcb_info_update() argument
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H A Dhal_vp9d_ctx.h48 void *hw_regs; member
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c240 JpegV540cRegSet *hw_regs = ctx->regs; in hal_jpege_v540c_start() local
252 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_jpege_v540c_start()
262 cfg.reg = &hw_regs->jpeg_table; in hal_jpege_v540c_start()
272 cfg.reg = &hw_regs->reg_base; in hal_jpege_v540c_start()
H A Dhal_jpege_vepu511.c469 JpegV511RegSet *hw_regs = ctx->regs; in hal_jpege_vepu511_start() local
481 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_jpege_vepu511_start()
491 cfg.reg = &hw_regs->jpeg_table; in hal_jpege_vepu511_start()
501 cfg.reg = &hw_regs->reg_base; in hal_jpege_vepu511_start()
511 cfg.reg = &hw_regs->reg_osd; in hal_jpege_vepu511_start()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu580.c2163 static MPP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *… in hal_h265e_v580_send_regs() argument
2165 RK_U32 *regs = (RK_U32*)hw_regs; in hal_h265e_v580_send_regs()
2171 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v580_send_regs()
2182 regs = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v580_send_regs()
2188 cfg.reg = &hw_regs->reg_base; in hal_h265e_v580_send_regs()
2199 regs = (RK_U32*)(&hw_regs->reg_base); in hal_h265e_v580_send_regs()
2209 cfg.reg = &hw_regs->reg_rc_klut; in hal_h265e_v580_send_regs()
2216 regs = (RK_U32*)&hw_regs->reg_rc_klut; in hal_h265e_v580_send_regs()
2227 cfg.reg = &hw_regs->reg_wgt; in hal_h265e_v580_send_regs()
2238 regs = (RK_U32*)&hw_regs->reg_wgt; in hal_h265e_v580_send_regs()
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H A Dhal_h265e_vepu511.c2244 H265eV511RegSet *hw_regs = frm->regs_set; in hal_h265e_vepu511_start() local
2257 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_vepu511_start()
2268 regs = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_vepu511_start()
2274 cfg.reg = &hw_regs->reg_frm; in hal_h265e_vepu511_start()
2285 regs = (RK_U32*)(&hw_regs->reg_frm); in hal_h265e_vepu511_start()
2294 cfg.reg = &hw_regs->reg_rc_roi; in hal_h265e_vepu511_start()
2305 regs = (RK_U32*)&hw_regs->reg_rc_roi; in hal_h265e_vepu511_start()
2311 cfg.reg = &hw_regs->reg_param; in hal_h265e_vepu511_start()
2322 regs = (RK_U32*)&hw_regs->reg_param; in hal_h265e_vepu511_start()
2328 cfg.reg = &hw_regs->reg_sqi; in hal_h265e_vepu511_start()
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H A Dhal_h265e_vepu540c.c1330 H265eV540cRegSet *hw_regs = ctx->regs; in hal_h265e_v540c_start() local
1343 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v540c_start()
1354 regs = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v540c_start()
1360 cfg.reg = &hw_regs->reg_base; in hal_h265e_v540c_start()
1371 regs = (RK_U32*)(&hw_regs->reg_base); in hal_h265e_v540c_start()
1380 cfg.reg = &hw_regs->reg_rc_roi; in hal_h265e_v540c_start()
1391 regs = (RK_U32*)&hw_regs->reg_rc_roi; in hal_h265e_v540c_start()
1397 cfg.reg = &hw_regs->reg_wgt; in hal_h265e_v540c_start()
1408 regs = (RK_U32*)&hw_regs->reg_wgt; in hal_h265e_v540c_start()
1414 cfg.reg = &hw_regs->reg_rdo; in hal_h265e_v540c_start()
H A Dhal_h265e_vepu510.c2083 H265eV510RegSet *hw_regs = frm->regs_set; in hal_h265e_v510_start() local
2096 cfg.reg = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v510_start()
2107 regs = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v510_start()
2113 cfg.reg = &hw_regs->reg_frm; in hal_h265e_v510_start()
2124 regs = (RK_U32*)(&hw_regs->reg_frm); in hal_h265e_v510_start()
2133 cfg.reg = &hw_regs->reg_rc_roi; in hal_h265e_v510_start()
2144 regs = (RK_U32*)&hw_regs->reg_rc_roi; in hal_h265e_v510_start()
2150 cfg.reg = &hw_regs->reg_param; in hal_h265e_v510_start()
2161 regs = (RK_U32*)&hw_regs->reg_param; in hal_h265e_v510_start()
2167 cfg.reg = &hw_regs->reg_sqi; in hal_h265e_v510_start()
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H A Dhal_h265e_vepu541.c1684 H265eV541RegSet *hw_regs = ctx->regs; in hal_h265e_v540_start() local
1688 vepu540_h265_set_me_ram(syn, hw_regs, k, tile_start_x); in hal_h265e_v540_start()
1694 hal_h265e_v540_set_uniform_tile(hw_regs, syn, k, tile_start_x); in hal_h265e_v540_start()
1699 hw_regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output); in hal_h265e_v540_start()
1700 hw_regs->bsbw_addr_hevc = hw_regs->bsbb_addr_hevc; in hal_h265e_v540_start()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu382.c282 Vdpu382Avs2dRegSet *hw_regs, in avs2d_refine_rcb_size() argument
343 if (hw_regs->common.reg012.fbc_e) in avs2d_refine_rcb_size()
354 static void hal_avs2d_rcb_info_update(void *hal, Vdpu382Avs2dRegSet *hw_regs) in hal_avs2d_rcb_info_update() argument
365 avs2d_refine_rcb_size(reg_ctx->rcb_info, hw_regs, width, height, (void *)&p_hal->syntax); in hal_avs2d_rcb_info_update()
H A Dhal_avs2d_rkv.c296 static void hal_avs2d_rcb_info_update(void *hal, Vdpu34xAvs2dRegSet *hw_regs) in hal_avs2d_rcb_info_update() argument
306 (void) hw_regs; in hal_avs2d_rcb_info_update()