Lines Matching refs:hw_regs
142 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu382H265dRegSet)); in hal_h265d_vdpu382_init()
150 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu382_init()
199 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu382_deinit()
222 Vdpu382H265dRegSet *hw_reg = (Vdpu382H265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v382_output_pps_packet()
439 Vdpu382H265dRegSet *hw_regs, in h265d_refine_rcb_size() argument
514 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
523 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
542 Vdpu382H265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
563 h265d_refine_rcb_size((Vdpu382RcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
654 Vdpu382H265dRegSet *hw_regs; in hal_h265d_vdpu382_gen_regs() local
684 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu382_gen_regs()
710 hw_regs = (Vdpu382H265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu382_gen_regs()
711 memset(hw_regs, 0, sizeof(Vdpu382H265dRegSet)); in hal_h265d_vdpu382_gen_regs()
713 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu382_gen_regs()
736 hw_regs->common.reg013.h26x_error_mode = 1; in hal_h265d_vdpu382_gen_regs()
737 hw_regs->common.reg021.error_deb_en = 1; in hal_h265d_vdpu382_gen_regs()
738 hw_regs->common.reg021.inter_error_prc_mode = 0; in hal_h265d_vdpu382_gen_regs()
739 hw_regs->common.reg021.error_intra_mode = 1; in hal_h265d_vdpu382_gen_regs()
741 hw_regs->common.reg017.slice_num = dxva_cxt->slice_count; in hal_h265d_vdpu382_gen_regs()
742 hw_regs->h265d_param.reg64.h26x_rps_mode = 0; in hal_h265d_vdpu382_gen_regs()
743 hw_regs->h265d_param.reg64.h26x_frame_orslice = 0; in hal_h265d_vdpu382_gen_regs()
744 hw_regs->h265d_param.reg64.h26x_stream_mode = 0; in hal_h265d_vdpu382_gen_regs()
750 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu382_gen_regs()
751 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
752 hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
753 hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; in hal_h265d_vdpu382_gen_regs()
755 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu382_gen_regs()
756 hw_regs->common.reg018.y_hor_virstride = stride_y >> 4; in hal_h265d_vdpu382_gen_regs()
757 hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4; in hal_h265d_vdpu382_gen_regs()
758 hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4; in hal_h265d_vdpu382_gen_regs()
763 hw_regs->common_addr.reg130_decout_base = mpp_buffer_get_fd(framebuf); //just index need map in hal_h265d_vdpu382_gen_regs()
767 if (hw_regs->common_addr.reg130_decout_base == 0) { in hal_h265d_vdpu382_gen_regs()
771 hw_regs->common_addr.reg130_decout_base = fd; in hal_h265d_vdpu382_gen_regs()
773 hw_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu382_gen_regs()
775 hw_regs->h265d_param.reg65.cur_top_poc = dxva_cxt->pp.CurrPicOrderCntVal; in hal_h265d_vdpu382_gen_regs()
783 hw_regs->h265d_param.reg103.ref_pic_layer_same_with_cur = 0xffff; in hal_h265d_vdpu382_gen_regs()
786 hw_regs->sw_sysctrl.sw_h26x_rps_mode = 1; in hal_h265d_vdpu382_gen_regs()
791 hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
793 hw_regs->h265d_addr.reg161_pps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
794 hw_regs->h265d_addr.reg163_rps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu382_gen_regs()
796 hw_regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu382_gen_regs()
797 hw_regs->common_addr.reg129_rlcwrite_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu382_gen_regs()
799 hw_regs->common.reg016_str_len = ((dxva_cxt->bitstream_size + 15) in hal_h265d_vdpu382_gen_regs()
801 hw_regs->common.reg016_str_len = stream_buf_size > hw_regs->common.reg016_str_len ? in hal_h265d_vdpu382_gen_regs()
802 hw_regs->common.reg016_str_len : stream_buf_size; in hal_h265d_vdpu382_gen_regs()
804 aglin_offset = hw_regs->common.reg016_str_len - dxva_cxt->bitstream_size; in hal_h265d_vdpu382_gen_regs()
809 hw_regs->common.reg010.dec_e = 1; in hal_h265d_vdpu382_gen_regs()
810 hw_regs->common.reg012.colmv_compress_en = reg_ctx->hw_info ? in hal_h265d_vdpu382_gen_regs()
813 hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff; in hal_h265d_vdpu382_gen_regs()
814 hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff; in hal_h265d_vdpu382_gen_regs()
816 hw_regs->common.reg011.dec_clkgate_e = 1; in hal_h265d_vdpu382_gen_regs()
817 hw_regs->common.reg011.err_head_fill_e = 1; in hal_h265d_vdpu382_gen_regs()
818 hw_regs->common.reg011.err_colmv_fill_e = 1; in hal_h265d_vdpu382_gen_regs()
820 hw_regs->common.reg026.inter_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
821 hw_regs->common.reg026.filterd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
822 hw_regs->common.reg026.strmd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
823 hw_regs->common.reg026.mcp_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
824 hw_regs->common.reg026.busifd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
825 hw_regs->common.reg026.dec_ctrl_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
826 hw_regs->common.reg026.intra_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
827 hw_regs->common.reg026.mc_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
828 hw_regs->common.reg026.transd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
829 hw_regs->common.reg026.sram_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
830 hw_regs->common.reg026.cru_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
831 hw_regs->common.reg026.reg_cfg_gating_en = 1; in hal_h265d_vdpu382_gen_regs()
832 hw_regs->common.reg032_timeout_threshold = 0x3ffff; in hal_h265d_vdpu382_gen_regs()
834 valid_ref = hw_regs->common_addr.reg130_decout_base; in hal_h265d_vdpu382_gen_regs()
836 hw_regs->common_addr.reg132_error_ref_base = valid_ref; in hal_h265d_vdpu382_gen_regs()
838 memset(&hw_regs->highpoc.reg205, 0, sizeof(RK_U32)); in hal_h265d_vdpu382_gen_regs()
845 hw_regs->h265d_param.reg67_82_ref_poc[i] = dxva_cxt->pp.PicOrderCntValList[i]; in hal_h265d_vdpu382_gen_regs()
852 hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(framebuf); in hal_h265d_vdpu382_gen_regs()
853 valid_ref = hw_regs->h265d_addr.reg164_179_ref_base[i]; in hal_h265d_vdpu382_gen_regs()
858 … hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i]; in hal_h265d_vdpu382_gen_regs()
860 hw_regs->common.reg021.error_intra_mode = 0; in hal_h265d_vdpu382_gen_regs()
864 hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref; in hal_h265d_vdpu382_gen_regs()
868 hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu382_gen_regs()
870 SET_REF_VALID(hw_regs->h265d_param, i, 1); in hal_h265d_vdpu382_gen_regs()
896 … hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base; in hal_h265d_vdpu382_gen_regs()
897 hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu382_gen_regs()
901 hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base; in hal_h265d_vdpu382_gen_regs()
902 hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu382_gen_regs()
905 SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3); in hal_h265d_vdpu382_gen_regs()
914 hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag; in hal_h265d_vdpu382_gen_regs()
916 hw_regs->common.reg011.buf_empty_en = 1; in hal_h265d_vdpu382_gen_regs()
918 hal_h265d_rcb_info_update(hal, dxva_cxt, hw_regs, width, height); in hal_h265d_vdpu382_gen_regs()
919 vdpu382_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu382_gen_regs()
929 hw_regs->h265d_addr.reg198_scale_down_luma_base = in hal_h265d_vdpu382_gen_regs()
930 hw_regs->common_addr.reg130_decout_base; in hal_h265d_vdpu382_gen_regs()
931 hw_regs->h265d_addr.reg199_scale_down_chorme_base = in hal_h265d_vdpu382_gen_regs()
932 hw_regs->common_addr.reg130_decout_base; in hal_h265d_vdpu382_gen_regs()
933 vdpu382_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->common); in hal_h265d_vdpu382_gen_regs()
935 hw_regs->h265d_addr.reg198_scale_down_luma_base = 0; in hal_h265d_vdpu382_gen_regs()
936 hw_regs->h265d_addr.reg199_scale_down_chorme_base = 0; in hal_h265d_vdpu382_gen_regs()
937 hw_regs->common.reg012.scale_down_en = 0; in hal_h265d_vdpu382_gen_regs()
940 vdpu382_setup_statistic(&hw_regs->common, &hw_regs->statistic); in hal_h265d_vdpu382_gen_regs()
950 Vdpu382H265dRegSet *hw_regs = NULL; in hal_h265d_vdpu382_start() local
963 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_start()
964 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_start()
966 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu382_start()
967 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu382_start()
970 if (hw_regs == NULL) { in hal_h265d_vdpu382_start()
985 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu382_start()
986 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu382_start()
995 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu382_start()
996 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu382_start()
1005 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu382_start()
1006 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu382_start()
1015 wr_cfg.reg = &hw_regs->h265d_addr; in hal_h265d_vdpu382_start()
1016 wr_cfg.size = sizeof(hw_regs->h265d_addr); in hal_h265d_vdpu382_start()
1025 wr_cfg.reg = &hw_regs->statistic; in hal_h265d_vdpu382_start()
1026 wr_cfg.size = sizeof(hw_regs->statistic); in hal_h265d_vdpu382_start()
1035 wr_cfg.reg = &hw_regs->highpoc; in hal_h265d_vdpu382_start()
1036 wr_cfg.size = sizeof(hw_regs->highpoc); in hal_h265d_vdpu382_start()
1045 rd_cfg.reg = &hw_regs->irq_status; in hal_h265d_vdpu382_start()
1046 rd_cfg.size = sizeof(hw_regs->irq_status); in hal_h265d_vdpu382_start()
1074 Vdpu382H265dRegSet *hw_regs = NULL; in hal_h265d_vdpu382_wait() local
1078 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu382_wait()
1080 hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu382_wait()
1083 p = (RK_U8*)hw_regs; in hal_h265d_vdpu382_wait()
1098 hw_regs->irq_status.reg224.dec_error_sta || in hal_h265d_vdpu382_wait()
1099 hw_regs->irq_status.reg224.buf_empty_sta || in hal_h265d_vdpu382_wait()
1100 hw_regs->irq_status.reg224.dec_bus_sta || in hal_h265d_vdpu382_wait()
1101 !hw_regs->irq_status.reg224.dec_rdy_sta) { in hal_h265d_vdpu382_wait()