Lines Matching refs:hw_regs
144 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xH265dRegSet)); in hal_h265d_vdpu34x_init()
152 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu34x_init()
206 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu34x_deinit()
229 Vdpu34xH265dRegSet *hw_reg = (Vdpu34xH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
668 Vdpu34xH265dRegSet *hw_regs, in h265d_refine_rcb_size() argument
742 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
751 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
771 Vdpu34xH265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
792 h265d_refine_rcb_size((Vdpu34xRcbInfo*)reg_ctx->rcb_info, hw_regs, width, height, dxva_cxt); in hal_h265d_rcb_info_update()
844 Vdpu34xH265dRegSet *hw_regs; in hal_h265d_vdpu34x_gen_regs() local
878 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu34x_gen_regs()
904 hw_regs = (Vdpu34xH265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu34x_gen_regs()
905 memset(hw_regs, 0, sizeof(Vdpu34xH265dRegSet)); in hal_h265d_vdpu34x_gen_regs()
907 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu34x_gen_regs()
945 hw_regs->common.reg013.h26x_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
946 hw_regs->common.reg013.h26x_streamd_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
947 hw_regs->common.reg013.colmv_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
948 hw_regs->common.reg021.error_deb_en = 1; in hal_h265d_vdpu34x_gen_regs()
949 hw_regs->common.reg021.inter_error_prc_mode = 0; in hal_h265d_vdpu34x_gen_regs()
950 hw_regs->common.reg021.error_intra_mode = 1; in hal_h265d_vdpu34x_gen_regs()
952 hw_regs->common.reg017.slice_num = dxva_cxt->slice_count; in hal_h265d_vdpu34x_gen_regs()
953 hw_regs->h265d_param.reg64.h26x_rps_mode = 0; in hal_h265d_vdpu34x_gen_regs()
954 hw_regs->h265d_param.reg64.h26x_frame_orslice = 0; in hal_h265d_vdpu34x_gen_regs()
955 hw_regs->h265d_param.reg64.h26x_stream_mode = 0; in hal_h265d_vdpu34x_gen_regs()
961 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu34x_gen_regs()
962 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu34x_gen_regs()
963 hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu34x_gen_regs()
964 hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; in hal_h265d_vdpu34x_gen_regs()
966 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu34x_gen_regs()
967 hw_regs->common.reg018.y_hor_virstride = stride_y >> 4; in hal_h265d_vdpu34x_gen_regs()
968 hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4; in hal_h265d_vdpu34x_gen_regs()
969 hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4; in hal_h265d_vdpu34x_gen_regs()
974 hw_regs->common_addr.reg130_decout_base = mpp_buffer_get_fd(framebuf); //just index need map in hal_h265d_vdpu34x_gen_regs()
978 if (hw_regs->common_addr.reg130_decout_base == 0) { in hal_h265d_vdpu34x_gen_regs()
982 hw_regs->common_addr.reg130_decout_base = fd; in hal_h265d_vdpu34x_gen_regs()
984 hw_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu34x_gen_regs()
986 hw_regs->h265d_param.reg65.cur_top_poc = dxva_cxt->pp.CurrPicOrderCntVal; in hal_h265d_vdpu34x_gen_regs()
995 hw_regs->common.reg012.wait_reset_en = 1; in hal_h265d_vdpu34x_gen_regs()
996 hw_regs->h265d_param.reg103.ref_pic_layer_same_with_cur = 0xffff; in hal_h265d_vdpu34x_gen_regs()
999 hw_regs->sw_sysctrl.sw_h26x_rps_mode = 1; in hal_h265d_vdpu34x_gen_regs()
1007 hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1009 hw_regs->h265d_addr.reg161_pps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1010 hw_regs->h265d_addr.reg163_rps_base = reg_ctx->bufs_fd; in hal_h265d_vdpu34x_gen_regs()
1012 hw_regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu34x_gen_regs()
1013 hw_regs->common_addr.reg129_rlcwrite_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu34x_gen_regs()
1015 hw_regs->common.reg016_str_len = ((dxva_cxt->bitstream_size + 15) in hal_h265d_vdpu34x_gen_regs()
1017 hw_regs->common.reg016_str_len = stream_buf_size > hw_regs->common.reg016_str_len ? in hal_h265d_vdpu34x_gen_regs()
1018 hw_regs->common.reg016_str_len : stream_buf_size; in hal_h265d_vdpu34x_gen_regs()
1020 aglin_offset = hw_regs->common.reg016_str_len - dxva_cxt->bitstream_size; in hal_h265d_vdpu34x_gen_regs()
1025 hw_regs->common.reg010.dec_e = 1; in hal_h265d_vdpu34x_gen_regs()
1026 hw_regs->common.reg011.dec_timeout_e = 1; in hal_h265d_vdpu34x_gen_regs()
1027 hw_regs->common.reg012.wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_vdpu34x_gen_regs()
1029 hw_regs->common.reg012.colmv_compress_en = COLMV_COMPRESS_EN; in hal_h265d_vdpu34x_gen_regs()
1032 hw_regs->common.reg026.swreg_block_gating_e = 0xfffef; in hal_h265d_vdpu34x_gen_regs()
1033 hw_regs->common.reg024.cabac_err_en_lowbits = 0; in hal_h265d_vdpu34x_gen_regs()
1034 hw_regs->common.reg025.cabac_err_en_highbits = 0; in hal_h265d_vdpu34x_gen_regs()
1036 hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff; in hal_h265d_vdpu34x_gen_regs()
1037 hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff; in hal_h265d_vdpu34x_gen_regs()
1038 hw_regs->common.reg026.swreg_block_gating_e = 0xfffff; in hal_h265d_vdpu34x_gen_regs()
1041 hw_regs->common.reg011.dec_clkgate_e = 1; in hal_h265d_vdpu34x_gen_regs()
1042 hw_regs->common.reg011.dec_e_strmd_clkgate_dis = 0; in hal_h265d_vdpu34x_gen_regs()
1043 hw_regs->common.reg026.reg_cfg_gating_en = 1; in hal_h265d_vdpu34x_gen_regs()
1044 hw_regs->common.reg032_timeout_threshold = 0x3ffff; in hal_h265d_vdpu34x_gen_regs()
1046 valid_ref = hw_regs->common_addr.reg130_decout_base; in hal_h265d_vdpu34x_gen_regs()
1048 hw_regs->common_addr.reg132_error_ref_base = valid_ref; in hal_h265d_vdpu34x_gen_regs()
1056 hw_regs->h265d_param.reg67_82_ref_poc[i] = dxva_cxt->pp.PicOrderCntValList[i]; in hal_h265d_vdpu34x_gen_regs()
1081 hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(ref_buf); in hal_h265d_vdpu34x_gen_regs()
1082 valid_ref = hw_regs->h265d_addr.reg164_179_ref_base[i]; in hal_h265d_vdpu34x_gen_regs()
1087 … hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i]; in hal_h265d_vdpu34x_gen_regs()
1089 hw_regs->common.reg021.error_intra_mode = 0; in hal_h265d_vdpu34x_gen_regs()
1093 hw_regs->common_addr.reg132_error_ref_base); in hal_h265d_vdpu34x_gen_regs()
1097 hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref; in hal_h265d_vdpu34x_gen_regs()
1102 SET_REF_VALID(hw_regs->h265d_param, i, 1); in hal_h265d_vdpu34x_gen_regs()
1104 if (hw_regs->common.reg013.h26x_error_mode && in hal_h265d_vdpu34x_gen_regs()
1105 !hw_regs->common.reg021.error_intra_mode && in hal_h265d_vdpu34x_gen_regs()
1109 … hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base; in hal_h265d_vdpu34x_gen_regs()
1113 hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base; in hal_h265d_vdpu34x_gen_regs()
1116 SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3); in hal_h265d_vdpu34x_gen_regs()
1118 hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu34x_gen_regs()
1138 hw_regs->common.reg013.timeout_mode = 1; in hal_h265d_vdpu34x_gen_regs()
1139 hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag; in hal_h265d_vdpu34x_gen_regs()
1141 hw_regs->common.reg011.buf_empty_en = 1; in hal_h265d_vdpu34x_gen_regs()
1143 hal_h265d_rcb_info_update(hal, dxva_cxt, hw_regs, width, height); in hal_h265d_vdpu34x_gen_regs()
1144 vdpu34x_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu34x_gen_regs()
1147 vdpu34x_setup_statistic(&hw_regs->common, &hw_regs->statistic); in hal_h265d_vdpu34x_gen_regs()
1157 Vdpu34xH265dRegSet *hw_regs = NULL; in hal_h265d_vdpu34x_start() local
1170 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_start()
1171 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_start()
1173 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu34x_start()
1174 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu34x_start()
1177 if (hw_regs == NULL) { in hal_h265d_vdpu34x_start()
1192 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu34x_start()
1193 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu34x_start()
1202 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu34x_start()
1203 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu34x_start()
1212 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu34x_start()
1213 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu34x_start()
1222 wr_cfg.reg = &hw_regs->h265d_addr; in hal_h265d_vdpu34x_start()
1223 wr_cfg.size = sizeof(hw_regs->h265d_addr); in hal_h265d_vdpu34x_start()
1232 wr_cfg.reg = &hw_regs->statistic; in hal_h265d_vdpu34x_start()
1233 wr_cfg.size = sizeof(hw_regs->statistic); in hal_h265d_vdpu34x_start()
1243 wr_cfg.reg = &hw_regs->highpoc; in hal_h265d_vdpu34x_start()
1244 wr_cfg.size = sizeof(hw_regs->highpoc); in hal_h265d_vdpu34x_start()
1254 rd_cfg.reg = &hw_regs->irq_status; in hal_h265d_vdpu34x_start()
1255 rd_cfg.size = sizeof(hw_regs->irq_status); in hal_h265d_vdpu34x_start()
1284 Vdpu34xH265dRegSet *hw_regs = NULL; in hal_h265d_vdpu34x_wait() local
1288 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu34x_wait()
1290 hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu34x_wait()
1293 p = (RK_U8*)hw_regs; in hal_h265d_vdpu34x_wait()
1308 hw_regs->irq_status.reg224.dec_error_sta || in hal_h265d_vdpu34x_wait()
1309 hw_regs->irq_status.reg224.buf_empty_sta || in hal_h265d_vdpu34x_wait()
1310 hw_regs->irq_status.reg224.dec_bus_sta || in hal_h265d_vdpu34x_wait()
1311 !hw_regs->irq_status.reg224.dec_rdy_sta) { in hal_h265d_vdpu34x_wait()