Lines Matching refs:hw_regs
131 reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu384aH265dRegSet)); in hal_h265d_vdpu384a_init()
140 reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs; in hal_h265d_vdpu384a_init()
179 MPP_FREE(reg_ctx->g_buf[i].hw_regs); in hal_h265d_vdpu384a_deinit()
349 Vdpu384aH265dRegSet *hw_reg = (Vdpu384aH265dRegSet*)(reg_ctx->hw_regs); in hal_h265d_v345_output_pps_packet()
722 Vdpu384aH265dRegSet *hw_regs, in hal_h265d_rcb_info_update() argument
732 (void)hw_regs; in hal_h265d_rcb_info_update()
783 Vdpu384aH265dRegSet *hw_regs; in hal_h265d_vdpu384a_gen_regs() local
813 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_vdpu384a_gen_regs()
842 hw_regs = (Vdpu384aH265dRegSet*)reg_ctx->hw_regs; in hal_h265d_vdpu384a_gen_regs()
843 memset(hw_regs, 0, sizeof(Vdpu384aH265dRegSet)); in hal_h265d_vdpu384a_gen_regs()
845 if (NULL == reg_ctx->hw_regs) { in hal_h265d_vdpu384a_gen_regs()
906 hw_regs->ctrl_regs.reg9.dpb_data_sel = 0; in hal_h265d_vdpu384a_gen_regs()
907 hw_regs->ctrl_regs.reg9.dpb_output_dis = 0; in hal_h265d_vdpu384a_gen_regs()
908 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 0; in hal_h265d_vdpu384a_gen_regs()
910 hw_regs->h265d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64; in hal_h265d_vdpu384a_gen_regs()
912 hw_regs->h265d_addrs.reg193_dpb_fbc64x4_payload_offset = fbd_offset; in hal_h265d_vdpu384a_gen_regs()
913 … hw_regs->h265d_paras.reg80_error_ref_hor_virstride = hw_regs->h265d_paras.reg68_dpb_hor_virstride; in hal_h265d_vdpu384a_gen_regs()
915 hw_regs->ctrl_regs.reg9.dpb_data_sel = 1; in hal_h265d_vdpu384a_gen_regs()
916 hw_regs->ctrl_regs.reg9.dpb_output_dis = 1; in hal_h265d_vdpu384a_gen_regs()
917 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 2; in hal_h265d_vdpu384a_gen_regs()
920 hw_regs->h265d_paras.reg77_pp_m_hor_stride = stride_y * 4 / 16; in hal_h265d_vdpu384a_gen_regs()
922 hw_regs->h265d_paras.reg77_pp_m_hor_stride = stride_y * 8 / 16; in hal_h265d_vdpu384a_gen_regs()
924 hw_regs->h265d_paras.reg77_pp_m_hor_stride = stride_y * 12 / 16; in hal_h265d_vdpu384a_gen_regs()
926 hw_regs->h265d_paras.reg77_pp_m_hor_stride = stride_y * 6 / 16; in hal_h265d_vdpu384a_gen_regs()
928 hw_regs->h265d_paras.reg79_pp_m_y_virstride = (virstrid_y + virstrid_uv) / 16; in hal_h265d_vdpu384a_gen_regs()
929 … hw_regs->h265d_paras.reg80_error_ref_hor_virstride = hw_regs->h265d_paras.reg77_pp_m_hor_stride; in hal_h265d_vdpu384a_gen_regs()
931 hw_regs->ctrl_regs.reg9.dpb_data_sel = 1; in hal_h265d_vdpu384a_gen_regs()
932 hw_regs->ctrl_regs.reg9.dpb_output_dis = 1; in hal_h265d_vdpu384a_gen_regs()
933 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 1; in hal_h265d_vdpu384a_gen_regs()
935 hw_regs->h265d_paras.reg77_pp_m_hor_stride = stride_y >> 4; in hal_h265d_vdpu384a_gen_regs()
936 hw_regs->h265d_paras.reg78_pp_m_uv_hor_stride = stride_uv >> 4; in hal_h265d_vdpu384a_gen_regs()
937 hw_regs->h265d_paras.reg79_pp_m_y_virstride = virstrid_y >> 4; in hal_h265d_vdpu384a_gen_regs()
938 … hw_regs->h265d_paras.reg80_error_ref_hor_virstride = hw_regs->h265d_paras.reg77_pp_m_hor_stride; in hal_h265d_vdpu384a_gen_regs()
940 …hw_regs->h265d_paras.reg81_error_ref_raster_uv_hor_virstride = hw_regs->h265d_paras.reg78_pp_m_uv_… in hal_h265d_vdpu384a_gen_regs()
941 … hw_regs->h265d_paras.reg82_error_ref_virstride = hw_regs->h265d_paras.reg79_pp_m_y_virstride; in hal_h265d_vdpu384a_gen_regs()
955 … hw_regs->common_addr.reg135_pp_m_decout_base = mpp_buffer_get_fd(framebuf); //just index need map in hal_h265d_vdpu384a_gen_regs()
956 hw_regs->h265d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(framebuf); in hal_h265d_vdpu384a_gen_regs()
964 if (!hw_regs->common_addr.reg135_pp_m_decout_base) in hal_h265d_vdpu384a_gen_regs()
971 hw_regs->common_addr.reg135_pp_m_decout_base = fd; in hal_h265d_vdpu384a_gen_regs()
972 hw_regs->h265d_addrs.reg192_dpb_payload64x4_st_cur_base = fd; in hal_h265d_vdpu384a_gen_regs()
975 hw_regs->h265d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu384a_gen_regs()
1002 hw_regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu384a_gen_regs()
1003 hw_regs->h265d_paras.reg66_stream_len = ((dxva_ctx->bitstream_size + 15) & (~15)) + 64; in hal_h265d_vdpu384a_gen_regs()
1004 hw_regs->common_addr.reg129_stream_buf_st_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu384a_gen_regs()
1005 hw_regs->common_addr.reg130_stream_buf_end_base = mpp_buffer_get_fd(streambuf); in hal_h265d_vdpu384a_gen_regs()
1007 aglin_offset = hw_regs->h265d_paras.reg66_stream_len - dxva_ctx->bitstream_size; in hal_h265d_vdpu384a_gen_regs()
1012 hw_regs->ctrl_regs.reg8_dec_mode = 0; // hevc in hal_h265d_vdpu384a_gen_regs()
1013 hw_regs->ctrl_regs.reg9.low_latency_en = 0; in hal_h265d_vdpu384a_gen_regs()
1015 hw_regs->ctrl_regs.reg10.strmd_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1016 hw_regs->ctrl_regs.reg10.inter_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1017 hw_regs->ctrl_regs.reg10.intra_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1018 hw_regs->ctrl_regs.reg10.transd_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1019 hw_regs->ctrl_regs.reg10.recon_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1020 hw_regs->ctrl_regs.reg10.filterd_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1021 hw_regs->ctrl_regs.reg10.bus_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1022 hw_regs->ctrl_regs.reg10.ctrl_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1023 hw_regs->ctrl_regs.reg10.rcb_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1024 hw_regs->ctrl_regs.reg10.err_prc_auto_gating_e = 1; in hal_h265d_vdpu384a_gen_regs()
1026 hw_regs->ctrl_regs.reg11.rd_outstanding = 32; in hal_h265d_vdpu384a_gen_regs()
1027 hw_regs->ctrl_regs.reg11.wr_outstanding = 250; in hal_h265d_vdpu384a_gen_regs()
1030 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu384a_gen_regs()
1031 hw_regs->ctrl_regs.reg16.error_spread_disable = 0; in hal_h265d_vdpu384a_gen_regs()
1032 hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0; in hal_h265d_vdpu384a_gen_regs()
1034 hw_regs->ctrl_regs.reg20_cabac_error_en_lowbits = 0xffffffff; in hal_h265d_vdpu384a_gen_regs()
1035 hw_regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3ff3f9ff; in hal_h265d_vdpu384a_gen_regs()
1037 hw_regs->ctrl_regs.reg13_core_timeout_threshold = 0xffff; in hal_h265d_vdpu384a_gen_regs()
1043 valid_ref = hw_regs->common_addr.reg135_pp_m_decout_base; in hal_h265d_vdpu384a_gen_regs()
1046 hw_regs->h265d_addrs.reg169_error_ref_base = valid_ref; in hal_h265d_vdpu384a_gen_regs()
1063 hw_regs->h265d_addrs.reg170_185_ref_base[i] = mpp_buffer_get_fd(framebuf); in hal_h265d_vdpu384a_gen_regs()
1064 … hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = mpp_buffer_get_fd(framebuf); in hal_h265d_vdpu384a_gen_regs()
1065 valid_ref = hw_regs->h265d_addrs.reg170_185_ref_base[i]; in hal_h265d_vdpu384a_gen_regs()
1070 … hw_regs->h265d_addrs.reg169_error_ref_base = hw_regs->h265d_addrs.reg170_185_ref_base[i]; in hal_h265d_vdpu384a_gen_regs()
1072 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu384a_gen_regs()
1075 hw_regs->h265d_addrs.reg170_185_ref_base[i] = valid_ref; in hal_h265d_vdpu384a_gen_regs()
1076 hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = valid_ref; in hal_h265d_vdpu384a_gen_regs()
1080 hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu384a_gen_regs()
1092 hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd; in hal_h265d_vdpu384a_gen_regs()
1093 hw_regs->h265d_paras.reg67_global_len = SPSPPS_ALIGNED_SIZE / 16; in hal_h265d_vdpu384a_gen_regs()
1114 … hw_regs->h265d_addrs.reg170_185_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base; in hal_h265d_vdpu384a_gen_regs()
1115 …hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_bas… in hal_h265d_vdpu384a_gen_regs()
1116 … hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu384a_gen_regs()
1120 … hw_regs->h265d_addrs.reg170_185_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base; in hal_h265d_vdpu384a_gen_regs()
1121 …hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_bas… in hal_h265d_vdpu384a_gen_regs()
1122 hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in hal_h265d_vdpu384a_gen_regs()
1126 hal_h265d_rcb_info_update(hal, dxva_ctx, hw_regs, width, height); in hal_h265d_vdpu384a_gen_regs()
1127 vdpu384a_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ? in hal_h265d_vdpu384a_gen_regs()
1130 vdpu384a_setup_statistic(&hw_regs->ctrl_regs); in hal_h265d_vdpu384a_gen_regs()
1146 hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer); in hal_h265d_vdpu384a_gen_regs()
1152 hw_regs->common_addr.reg135_pp_m_decout_base = fd; in hal_h265d_vdpu384a_gen_regs()
1153 hw_regs->h265d_addrs.reg192_dpb_payload64x4_st_cur_base = fd; in hal_h265d_vdpu384a_gen_regs()
1154 hw_regs->h265d_addrs.reg169_error_ref_base = fd; in hal_h265d_vdpu384a_gen_regs()
1155 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu384a_gen_regs()
1158 hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer); in hal_h265d_vdpu384a_gen_regs()
1159 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras); in hal_h265d_vdpu384a_gen_regs()
1163 hw_regs->ctrl_regs.reg9.scale_down_en = 0; in hal_h265d_vdpu384a_gen_regs()
1175 Vdpu384aH265dRegSet *hw_regs = NULL; in hal_h265d_vdpu384a_start() local
1188 p = (RK_U8*)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_start()
1189 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_start()
1191 p = (RK_U8*)reg_ctx->hw_regs; in hal_h265d_vdpu384a_start()
1192 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu384a_start()
1195 if (hw_regs == NULL) { in hal_h265d_vdpu384a_start()
1210 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_h265d_vdpu384a_start()
1211 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_h265d_vdpu384a_start()
1219 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu384a_start()
1220 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu384a_start()
1228 wr_cfg.reg = &hw_regs->h265d_paras; in hal_h265d_vdpu384a_start()
1229 wr_cfg.size = sizeof(hw_regs->h265d_paras); in hal_h265d_vdpu384a_start()
1237 wr_cfg.reg = &hw_regs->h265d_addrs; in hal_h265d_vdpu384a_start()
1238 wr_cfg.size = sizeof(hw_regs->h265d_addrs); in hal_h265d_vdpu384a_start()
1246 rd_cfg.reg = &hw_regs->ctrl_regs.reg15; in hal_h265d_vdpu384a_start()
1247 rd_cfg.size = sizeof(hw_regs->ctrl_regs.reg15); in hal_h265d_vdpu384a_start()
1275 Vdpu384aH265dRegSet *hw_regs = NULL; in hal_h265d_vdpu384a_wait() local
1279 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_vdpu384a_wait()
1281 hw_regs = ( Vdpu384aH265dRegSet *)reg_ctx->hw_regs; in hal_h265d_vdpu384a_wait()
1284 p = (RK_U8*)hw_regs; in hal_h265d_vdpu384a_wait()
1299 (!hw_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) || in hal_h265d_vdpu384a_wait()
1300 hw_regs->ctrl_regs.reg15.rkvdec_strm_error_sta || in hal_h265d_vdpu384a_wait()
1301 hw_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta || in hal_h265d_vdpu384a_wait()
1302 hw_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta || in hal_h265d_vdpu384a_wait()
1303 hw_regs->ctrl_regs.reg15.rkvdec_bus_error_sta || in hal_h265d_vdpu384a_wait()
1304 hw_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta || in hal_h265d_vdpu384a_wait()
1305 hw_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) { in hal_h265d_vdpu384a_wait()