1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v580"
18
19 #include <string.h>
20 #include <math.h>
21 #include <limits.h>
22
23 #include "mpp_env.h"
24 #include "mpp_mem.h"
25 #include "mpp_soc.h"
26 #include "mpp_common.h"
27 #include "mpp_frame_impl.h"
28 #include "mpp_packet_impl.h"
29 #include "mpp_dmabuf.h"
30
31 #include "hal_h265e_debug.h"
32 #include "h265e_syntax_new.h"
33 #include "hal_h265e_stream_amend.h"
34 #include "hal_bufs.h"
35 #include "rkv_enc_def.h"
36 #include "h265e_dpb.h"
37 #include "vepu5xx_common.h"
38 #include "vepu580_common.h"
39 #include "hal_h265e_vepu580.h"
40 #include "hal_h265e_vepu580_reg.h"
41 #include "mpp_enc_cb_param.h"
42 #include "vepu5xx.h"
43
44 #include "mpp_service.h"
45
46 #define MAX_FRAME_TASK_NUM 2
47 #define MAX_TILE_NUM 4
48 #define MAX_REGS_SET ((MAX_FRAME_TASK_NUM) * (MAX_TILE_NUM))
49
50 #define hal_h265e_err(fmt, ...) \
51 do {\
52 mpp_err_f(fmt, ## __VA_ARGS__);\
53 } while (0)
54
55 typedef struct vepu580_h265_fbk_t {
56 RK_U32 hw_status; /* 0:corret, 1:error */
57 RK_U32 qp_sum;
58 RK_U32 out_strm_size;
59 RK_U32 out_hw_strm_size;
60 RK_S64 sse_sum;
61 RK_U32 st_lvl64_inter_num;
62 RK_U32 st_lvl32_inter_num;
63 RK_U32 st_lvl16_inter_num;
64 RK_U32 st_lvl8_inter_num;
65 RK_U32 st_lvl32_intra_num;
66 RK_U32 st_lvl16_intra_num;
67 RK_U32 st_lvl8_intra_num;
68 RK_U32 st_lvl4_intra_num;
69 RK_U32 st_cu_num_qp[52];
70 RK_U32 st_madp;
71 RK_U32 st_madi;
72 RK_U32 st_md_sad_b16num0;
73 RK_U32 st_md_sad_b16num1;
74 RK_U32 st_md_sad_b16num2;
75 RK_U32 st_md_sad_b16num3;
76 RK_U32 st_madi_b16num0;
77 RK_U32 st_madi_b16num1;
78 RK_U32 st_madi_b16num2;
79 RK_U32 st_madi_b16num3;
80 RK_U32 st_mb_num;
81 RK_U32 st_ctu_num;
82 } Vepu580H265Fbk;
83
84 typedef struct Vepu580RoiHevcBsCfg_t {
85 RK_U8 amv_en : 1;
86 RK_U8 qp_adj : 1;
87 RK_U8 force_split : 1;
88 RK_U8 force_intra : 2;
89 RK_U8 force_inter : 2;
90 } Vepu580RoiHevcBsCfg;
91
92 typedef struct Vepu580MdInfo_t {
93 RK_U8 vld;
94 RK_U16 sad[16];
95 } Vepu580MdInfo;
96
97 typedef struct Vepu580RoiHevcQpCfg_t {
98 RK_U16 reserved : 4;
99 /*
100 * Qp area index
101 * The choosed qp area index.
102 */
103 RK_U16 qp_area_idx : 4;
104 /*
105 * Qp_adj
106 * Qp_adj
107 * in absolute qp mode qp_adj is the final qp used by encoder
108 * in relative qp mode qp_adj is a adjustment to final qp
109 */
110 RK_S16 qp_adj : 7;
111 /*
112 * Qp_adj_mode
113 * Qp adjustment mode
114 * 1 - absolute qp mode:
115 * the 16x16 MB qp is set to the qp_adj value
116 * 0 - relative qp mode
117 * the 16x16 MB qp is adjusted by qp_adj value
118 */
119 RK_U16 qp_adj_mode : 1;
120 } Vepu580RoiHevcQpCfg;
121
122 typedef struct Vepu580H265eFrmCfg_t {
123 RK_S32 frame_count;
124 RK_S32 frame_type;
125
126 /* dchs cfg on frame parallel */
127 RK_S32 dchs_curr_idx;
128 RK_S32 dchs_prev_idx;
129
130 /* hal dpb management slot idx */
131 RK_S32 hal_curr_idx;
132 RK_S32 hal_refr_idx;
133
134 /* regs cfg */
135 H265eV580RegSet *regs_set[MAX_TILE_NUM];
136 H265eV580StatusElem *regs_ret[MAX_TILE_NUM];
137
138 /* hardware return info collection cfg */
139 Vepu580H265Fbk feedback;
140
141 /* tile buffer */
142 MppBuffer hw_tile_buf[MAX_TILE_NUM];
143 MppBuffer hw_tile_stream[MAX_TILE_NUM - 1];
144
145 /* osd cfg */
146 Vepu5xxOsdCfg osd_cfg;
147 void *roi_data;
148
149 /* gdr roi cfg */
150 MppBuffer roi_base_cfg_buf;
151 void *roi_base_cfg_sw_buf;
152 RK_S32 roi_base_buf_size;
153
154 /* variable length cfg */
155 MppDevRegOffCfgs *reg_cfg;
156 } Vepu580H265eFrmCfg;
157
158 typedef struct H265eV580HalContext_t {
159 MppEncHalApi api;
160 MppDev dev;
161 Vepu580H265eFrmCfg *frms[MAX_FRAME_TASK_NUM];
162
163 /* current used frame config */
164 Vepu580H265eFrmCfg *frm;
165
166 /* slice split poll cfg */
167 RK_S32 poll_slice_max;
168 RK_S32 poll_cfg_size;
169
170 /* @frame_cnt starts from ZERO */
171 RK_U32 frame_count;
172
173 /* frame parallel info */
174 RK_S32 task_cnt;
175 RK_S32 task_idx;
176
177 /* dchs cfg */
178 RK_S32 curr_idx;
179 RK_S32 prev_idx;
180
181 /* debug cfg */
182 void *dump_files;
183
184 RK_S32 frame_type;
185 RK_S32 last_frame_type;
186
187 MppBufferGroup roi_grp;
188 MppBufferGroup qpmap_grp;
189
190 MppEncCfgSet *cfg;
191 H265eSyntax_new *syn;
192 H265eDpb *dpb;
193
194 /* single frame tile parallel info */
195 MppBufferGroup tile_grp;
196 RK_U32 tile_num;
197 RK_U32 tile_parall_en;
198 RK_U32 tile_dump_err;
199
200 MppBuffer buf_pass1;
201
202 RK_U32 enc_mode;
203 RK_U32 frame_size;
204 RK_S32 max_buf_cnt;
205 RK_S32 hdr_status;
206 void *input_fmt;
207 RK_U8 *src_buf;
208 RK_U8 *dst_buf;
209 RK_S32 buf_size;
210 HalBufs dpb_bufs;
211 RK_S32 fbc_header_len;
212
213 MppDevPollCfg *poll_cfgs;
214 MppCbCtx *output_cb;
215
216 /* finetune */
217 void *tune;
218 MppBuffer md_info_buf; /* md info buffer for deblurring */
219 MppBuffer qpmap_base_cfg_buf;
220 MppBuffer qpmap_qp_cfg_buf;
221 RK_U8* md_flag_buf;
222 RK_S32 md_info_buf_size;
223 RK_S32 qpmap_base_cfg_size;
224 RK_S32 qpmap_qp_cfg_size;
225 RK_S32 md_flag_size;
226 } H265eV580HalContext;
227
228 static RK_U32 aq_thd_default[16] = {
229 0, 0, 0, 0,
230 3, 3, 5, 5,
231 8, 8, 8, 15,
232 15, 20, 25, 35
233 };
234
235 static RK_U32 h265e_mode_bias[16] = {
236 0, 2, 4, 6,
237 8, 10, 12, 14,
238 16, 18, 20, 24,
239 28, 32, 64, 128
240 };
241
242 static RK_S32 aq_qp_dealt_default[16] = {
243 -8, -7, -6, -5,
244 -4, -3, -2, -1,
245 0, 1, 2, 3,
246 5, 7, 8, 9,
247 };
248
249
250 static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
251
252 static RK_U16 lvl16_intra_cst_thd[4] = {2, 6, 16, 36};
253
254 static RK_U8 lvl32_intra_cst_wgt[8] = {23, 22, 21, 20, 22, 24, 26};
255
256 static RK_U8 lvl16_intra_cst_wgt[8] = {17, 17, 17, 18, 17, 18, 18};
257
258 #include "hal_h265e_vepu580_tune.c"
259
vepu580_h265_set_me_ram(H265eSyntax_new * syn,hevc_vepu580_base * regs,RK_U32 index,RK_S32 tile_start_x)260 static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs,
261 RK_U32 index, RK_S32 tile_start_x)
262 {
263 RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
264 RK_S32 srch_w = regs->reg0220_me_rnge.cme_srch_h * 4;
265 RK_S32 srch_h = regs->reg0220_me_rnge.cme_srch_v * 4;
266 RK_S32 x_gmv = regs->reg0224_gmv.gmv_x;
267 RK_S32 y_gmv = regs->reg0224_gmv.gmv_y;
268 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64;
269
270 if (!syn->pp.tiles_enabled_flag) {
271 if (x_gmv - srch_w < 0) {
272 frm_sta = (x_gmv - srch_w - 15) / 16;
273 } else {
274 frm_sta = (x_gmv - srch_w) / 16;
275 }
276 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1);
277 if (x_gmv + srch_w < 0) {
278 frm_end = pic_wd64 - 1 + (x_gmv + srch_w) / 16;
279 } else {
280 frm_end = pic_wd64 - 1 + (x_gmv + srch_w + 15) / 16;
281 }
282 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1);
283 } else {
284 RK_S32 tile_ctu_stax = tile_start_x;
285 RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index];
286
287 if (x_gmv - srch_w < 0) {
288 frm_sta = tile_ctu_stax + (x_gmv - srch_w - 15) / 16;
289 } else {
290 frm_sta = tile_ctu_stax + (x_gmv - srch_w) / 16;
291 }
292 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1);
293
294 if (x_gmv + srch_w < 0) {
295 frm_end = tile_ctu_endx + (x_gmv + srch_w) / 16;
296 } else {
297 frm_end = tile_ctu_endx + (x_gmv + srch_w + 15) / 16;
298 }
299 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1);
300 }
301 pic_w = (frm_end - frm_sta + 1) * 64;
302 regs->reg0222_me_cach.cme_linebuf_w = (pic_w ? pic_w : 64) / 64;
303 {
304 RK_U32 cime_rama_max = 2464;
305 RK_U32 ctu_4_h = 4, ramb_h;
306 RK_U32 cur_srch_16_w, cur_srch_4_h, cur_srch_max;
307 RK_U32 cime_rama_h = ctu_4_h;
308
309 if ((x_gmv % 16 - srch_w % 16) < 0) {
310 cur_srch_16_w = (16 + (x_gmv % 16 - srch_w % 16) % 16 + srch_w * 2 + 15) / 16 + 1;
311 } else {
312 cur_srch_16_w = ((x_gmv % 16 - srch_w % 16) % 16 + srch_w * 2 + 15) / 16 + 1;
313 }
314 if ((y_gmv % 4 - srch_h % 4) < 0) {
315 cur_srch_4_h = (4 + (y_gmv % 4 - srch_h % 4) % 4 + srch_h * 2 + 3) / 4 + ctu_4_h;
316 } else {
317 cur_srch_4_h = ((y_gmv % 4 - srch_h % 4) % 4 + srch_h * 2 + 3) / 4 + ctu_4_h;
318 }
319 cur_srch_max = MPP_ALIGN(cur_srch_4_h, 4);
320 if (regs->reg0222_me_cach.cme_linebuf_w < cur_srch_16_w) {
321 cur_srch_16_w = regs->reg0222_me_cach.cme_linebuf_w;
322 }
323 ramb_h = cur_srch_4_h;
324 while ((cime_rama_h < cur_srch_max) && (cime_rama_max >
325 ((cime_rama_h - ctu_4_h) * regs->reg0222_me_cach.cme_linebuf_w * 4 + (ramb_h * 4 * cur_srch_16_w)))) {
326 cime_rama_h = cime_rama_h + ctu_4_h;
327 if (ramb_h > 2 * ctu_4_h) {
328 ramb_h = ramb_h - ctu_4_h;
329 } else {
330 ramb_h = ctu_4_h;
331 }
332 }
333 if (cur_srch_4_h == ctu_4_h) {
334 cime_rama_h = cime_rama_h + ctu_4_h;
335 ramb_h = 0;
336 }
337 if (cime_rama_max < ((cime_rama_h - ctu_4_h) * regs->reg0222_me_cach.cme_linebuf_w * 4 + (ramb_h * 4 * cur_srch_16_w))) {
338 cime_rama_h = cime_rama_h - ctu_4_h;
339 }
340 regs->reg0222_me_cach.cme_rama_h = cime_rama_h; /* cime_rama_max */
341
342 {
343 RK_U32 ram_col_h = (cime_rama_h - ctu_4_h) / ctu_4_h;
344 regs->reg0222_me_cach.cme_rama_max = ram_col_h * regs->reg0222_me_cach.cme_linebuf_w + cur_srch_16_w;
345 }
346
347 }
348
349 hal_h265e_dbg_detail("cime_rama_h %d, cime_rama_max %d, cime_linebuf_w %d",
350 regs->reg0222_me_cach.cme_rama_h, regs->reg0222_me_cach.cme_rama_max, regs->reg0222_me_cach.cme_linebuf_w);
351 }
352
vepu580_h265_setup_hal_bufs(H265eV580HalContext * ctx)353 static MPP_RET vepu580_h265_setup_hal_bufs(H265eV580HalContext *ctx)
354 {
355 MPP_RET ret = MPP_OK;
356 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
357 RK_U32 frame_size;
358 RK_S32 mb_wd64, mb_h64;
359 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
360 MppEncPrepCfg *prep = &ctx->cfg->prep;
361 RK_S32 old_max_cnt = ctx->max_buf_cnt;
362 RK_S32 new_max_cnt = 4;
363
364 hal_h265e_enter();
365
366 mb_wd64 = (prep->width + 63) / 64;
367 mb_h64 = (prep->height + 63) / 64 + 1;
368
369 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
370 vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);
371
372 if (ref_cfg) {
373 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
374 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
375 }
376
377 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
378 size_t size[3] = {0};
379
380 hal_bufs_deinit(ctx->dpb_bufs);
381 hal_bufs_init(&ctx->dpb_bufs);
382
383 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
384 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
385 size[1] = (mb_wd64 * mb_h64 << 8);
386 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 6, 256);
387 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
388
389 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
390 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
391
392 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
393
394 ctx->frame_size = frame_size;
395 ctx->max_buf_cnt = new_max_cnt;
396 }
397 hal_h265e_leave();
398 return ret;
399 }
400
vepu580_h265_sobel_cfg(hevc_vepu580_wgt * reg)401 static void vepu580_h265_sobel_cfg(hevc_vepu580_wgt *reg)
402 {
403 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10;
404 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11;
405 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12;
406 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13;
407 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14;
408
409 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9;
410 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15;
411 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8;
412 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16;
413 reg->pre_intra_cla0_B1.pre_intra_cla0_m9 = 7;
414
415 reg->pre_intra_cla1_B0.pre_intra_cla1_m0 = 10;
416 reg->pre_intra_cla1_B0.pre_intra_cla1_m1 = 9;
417 reg->pre_intra_cla1_B0.pre_intra_cla1_m2 = 8;
418 reg->pre_intra_cla1_B0.pre_intra_cla1_m3 = 7;
419 reg->pre_intra_cla1_B0.pre_intra_cla1_m4 = 6;
420 reg->pre_intra_cla1_B1.pre_intra_cla1_m5 = 11;
421 reg->pre_intra_cla1_B1.pre_intra_cla1_m6 = 5;
422 reg->pre_intra_cla1_B1.pre_intra_cla1_m7 = 12;
423 reg->pre_intra_cla1_B1.pre_intra_cla1_m8 = 4;
424 reg->pre_intra_cla1_B1.pre_intra_cla1_m9 = 13;
425
426 reg->pre_intra_cla2_B0.pre_intra_cla2_m0 = 18;
427 reg->pre_intra_cla2_B0.pre_intra_cla2_m1 = 17;
428 reg->pre_intra_cla2_B0.pre_intra_cla2_m2 = 16;
429 reg->pre_intra_cla2_B0.pre_intra_cla2_m3 = 15;
430 reg->pre_intra_cla2_B0.pre_intra_cla2_m4 = 14;
431 reg->pre_intra_cla2_B1.pre_intra_cla2_m5 = 19;
432 reg->pre_intra_cla2_B1.pre_intra_cla2_m6 = 13;
433 reg->pre_intra_cla2_B1.pre_intra_cla2_m7 = 20;
434 reg->pre_intra_cla2_B1.pre_intra_cla2_m8 = 12;
435 reg->pre_intra_cla2_B1.pre_intra_cla2_m9 = 21;
436
437 reg->pre_intra_cla3_B0.pre_intra_cla3_m0 = 18;
438 reg->pre_intra_cla3_B0.pre_intra_cla3_m1 = 19;
439 reg->pre_intra_cla3_B0.pre_intra_cla3_m2 = 20;
440 reg->pre_intra_cla3_B0.pre_intra_cla3_m3 = 21;
441 reg->pre_intra_cla3_B0.pre_intra_cla3_m4 = 22;
442 reg->pre_intra_cla3_B1.pre_intra_cla3_m5 = 17;
443 reg->pre_intra_cla3_B1.pre_intra_cla3_m6 = 23;
444 reg->pre_intra_cla3_B1.pre_intra_cla3_m7 = 16;
445 reg->pre_intra_cla3_B1.pre_intra_cla3_m8 = 24;
446 reg->pre_intra_cla3_B1.pre_intra_cla3_m9 = 15;
447
448 reg->pre_intra_cla4_B0.pre_intra_cla4_m0 = 25;
449 reg->pre_intra_cla4_B0.pre_intra_cla4_m1 = 26;
450 reg->pre_intra_cla4_B0.pre_intra_cla4_m2 = 24;
451 reg->pre_intra_cla4_B0.pre_intra_cla4_m3 = 23;
452 reg->pre_intra_cla4_B0.pre_intra_cla4_m4 = 22;
453 reg->pre_intra_cla4_B1.pre_intra_cla4_m5 = 27;
454 reg->pre_intra_cla4_B1.pre_intra_cla4_m6 = 21;
455 reg->pre_intra_cla4_B1.pre_intra_cla4_m7 = 28;
456 reg->pre_intra_cla4_B1.pre_intra_cla4_m8 = 20;
457 reg->pre_intra_cla4_B1.pre_intra_cla4_m9 = 29;
458
459 reg->pre_intra_cla5_B0.pre_intra_cla5_m0 = 27;
460 reg->pre_intra_cla5_B0.pre_intra_cla5_m1 = 26;
461 reg->pre_intra_cla5_B0.pre_intra_cla5_m2 = 28;
462 reg->pre_intra_cla5_B0.pre_intra_cla5_m3 = 29;
463 reg->pre_intra_cla5_B0.pre_intra_cla5_m4 = 30;
464 reg->pre_intra_cla5_B1.pre_intra_cla5_m5 = 25;
465 reg->pre_intra_cla5_B1.pre_intra_cla5_m6 = 31;
466 reg->pre_intra_cla5_B1.pre_intra_cla5_m7 = 24;
467 reg->pre_intra_cla5_B1.pre_intra_cla5_m8 = 32;
468 reg->pre_intra_cla5_B1.pre_intra_cla5_m9 = 23;
469
470 reg->pre_intra_cla6_B0.pre_intra_cla6_m0 = 34;
471 reg->pre_intra_cla6_B0.pre_intra_cla6_m1 = 33;
472 reg->pre_intra_cla6_B0.pre_intra_cla6_m2 = 32;
473 reg->pre_intra_cla6_B0.pre_intra_cla6_m3 = 31;
474 reg->pre_intra_cla6_B0.pre_intra_cla6_m4 = 30;
475 reg->pre_intra_cla6_B1.pre_intra_cla6_m5 = 2;
476 reg->pre_intra_cla6_B1.pre_intra_cla6_m6 = 29;
477 reg->pre_intra_cla6_B1.pre_intra_cla6_m7 = 3;
478 reg->pre_intra_cla6_B1.pre_intra_cla6_m8 = 28;
479 reg->pre_intra_cla6_B1.pre_intra_cla6_m9 = 4;
480
481 reg->pre_intra_cla7_B0.pre_intra_cla7_m0 = 34;
482 reg->pre_intra_cla7_B0.pre_intra_cla7_m1 = 2;
483 reg->pre_intra_cla7_B0.pre_intra_cla7_m2 = 3;
484 reg->pre_intra_cla7_B0.pre_intra_cla7_m3 = 4;
485 reg->pre_intra_cla7_B0.pre_intra_cla7_m4 = 5;
486 reg->pre_intra_cla7_B1.pre_intra_cla7_m5 = 33;
487 reg->pre_intra_cla7_B1.pre_intra_cla7_m6 = 6;
488 reg->pre_intra_cla7_B1.pre_intra_cla7_m7 = 32;
489 reg->pre_intra_cla7_B1.pre_intra_cla7_m8 = 7;
490 reg->pre_intra_cla7_B1.pre_intra_cla7_m9 = 31;
491
492 reg->pre_intra_cla8_B0.pre_intra_cla8_m0 = 10;
493 reg->pre_intra_cla8_B0.pre_intra_cla8_m1 = 26;
494 reg->pre_intra_cla8_B0.pre_intra_cla8_m2 = 18;
495 reg->pre_intra_cla8_B0.pre_intra_cla8_m3 = 34;
496 reg->pre_intra_cla8_B0.pre_intra_cla8_m4 = 6;
497 reg->pre_intra_cla8_B1.pre_intra_cla8_m5 = 14;
498 reg->pre_intra_cla8_B1.pre_intra_cla8_m6 = 22;
499 reg->pre_intra_cla8_B1.pre_intra_cla8_m7 = 30;
500 reg->pre_intra_cla8_B1.pre_intra_cla8_m8 = 2;
501 reg->pre_intra_cla8_B1.pre_intra_cla8_m9 = 24;
502
503 reg->pre_intra_cla9_B0.pre_intra_cla9_m0 = 0;
504 reg->pre_intra_cla9_B0.pre_intra_cla9_m1 = 0;
505 reg->pre_intra_cla9_B0.pre_intra_cla9_m2 = 0;
506 reg->pre_intra_cla9_B0.pre_intra_cla9_m3 = 0;
507 reg->pre_intra_cla9_B0.pre_intra_cla9_m4 = 0;
508 reg->pre_intra_cla9_B1.pre_intra_cla9_m5 = 0;
509 reg->pre_intra_cla9_B1.pre_intra_cla9_m6 = 0;
510 reg->pre_intra_cla9_B1.pre_intra_cla9_m7 = 0;
511 reg->pre_intra_cla9_B1.pre_intra_cla9_m8 = 0;
512 reg->pre_intra_cla9_B1.pre_intra_cla9_m9 = 0;
513
514 reg->pre_intra_cla10_B0.pre_intra_cla10_m0 = 0;
515 reg->pre_intra_cla10_B0.pre_intra_cla10_m1 = 0;
516 reg->pre_intra_cla10_B0.pre_intra_cla10_m2 = 0;
517 reg->pre_intra_cla10_B0.pre_intra_cla10_m3 = 0;
518 reg->pre_intra_cla10_B0.pre_intra_cla10_m4 = 0;
519 reg->pre_intra_cla10_B1.pre_intra_cla10_m5 = 0;
520 reg->pre_intra_cla10_B1.pre_intra_cla10_m6 = 0;
521 reg->pre_intra_cla10_B1.pre_intra_cla10_m7 = 0;
522 reg->pre_intra_cla10_B1.pre_intra_cla10_m8 = 0;
523 reg->pre_intra_cla10_B1.pre_intra_cla10_m9 = 0;
524
525 reg->pre_intra_cla11_B0.pre_intra_cla11_m0 = 0;
526 reg->pre_intra_cla11_B0.pre_intra_cla11_m1 = 0;
527 reg->pre_intra_cla11_B0.pre_intra_cla11_m2 = 0;
528 reg->pre_intra_cla11_B0.pre_intra_cla11_m3 = 0;
529 reg->pre_intra_cla11_B0.pre_intra_cla11_m4 = 0;
530 reg->pre_intra_cla11_B1.pre_intra_cla11_m5 = 0;
531 reg->pre_intra_cla11_B1.pre_intra_cla11_m6 = 0;
532 reg->pre_intra_cla11_B1.pre_intra_cla11_m7 = 0;
533 reg->pre_intra_cla11_B1.pre_intra_cla11_m8 = 0;
534 reg->pre_intra_cla11_B1.pre_intra_cla11_m9 = 0;
535
536 reg->pre_intra_cla12_B0.pre_intra_cla12_m0 = 0;
537 reg->pre_intra_cla12_B0.pre_intra_cla12_m1 = 0;
538 reg->pre_intra_cla12_B0.pre_intra_cla12_m2 = 0;
539 reg->pre_intra_cla12_B0.pre_intra_cla12_m3 = 0;
540 reg->pre_intra_cla12_B0.pre_intra_cla12_m4 = 0;
541 reg->pre_intra_cla12_B1.pre_intra_cla12_m5 = 0;
542 reg->pre_intra_cla12_B1.pre_intra_cla12_m6 = 0;
543 reg->pre_intra_cla12_B1.pre_intra_cla12_m7 = 0;
544 reg->pre_intra_cla12_B1.pre_intra_cla12_m8 = 0;
545 reg->pre_intra_cla12_B1.pre_intra_cla12_m9 = 0;
546
547 reg->pre_intra_cla13_B0.pre_intra_cla13_m0 = 0;
548 reg->pre_intra_cla13_B0.pre_intra_cla13_m1 = 0;
549 reg->pre_intra_cla13_B0.pre_intra_cla13_m2 = 0;
550 reg->pre_intra_cla13_B0.pre_intra_cla13_m3 = 0;
551 reg->pre_intra_cla13_B0.pre_intra_cla13_m4 = 0;
552 reg->pre_intra_cla13_B1.pre_intra_cla13_m5 = 0;
553 reg->pre_intra_cla13_B1.pre_intra_cla13_m6 = 0;
554 reg->pre_intra_cla13_B1.pre_intra_cla13_m7 = 0;
555 reg->pre_intra_cla13_B1.pre_intra_cla13_m8 = 0;
556 reg->pre_intra_cla13_B1.pre_intra_cla13_m9 = 0;
557
558 reg->pre_intra_cla14_B0.pre_intra_cla14_m0 = 0;
559 reg->pre_intra_cla14_B0.pre_intra_cla14_m1 = 0;
560 reg->pre_intra_cla14_B0.pre_intra_cla14_m2 = 0;
561 reg->pre_intra_cla14_B0.pre_intra_cla14_m3 = 0;
562 reg->pre_intra_cla14_B0.pre_intra_cla14_m4 = 0;
563 reg->pre_intra_cla14_B1.pre_intra_cla14_m5 = 0;
564 reg->pre_intra_cla14_B1.pre_intra_cla14_m6 = 0;
565 reg->pre_intra_cla14_B1.pre_intra_cla14_m7 = 0;
566 reg->pre_intra_cla14_B1.pre_intra_cla14_m8 = 0;
567 reg->pre_intra_cla14_B1.pre_intra_cla14_m9 = 0;
568
569 reg->pre_intra_cla15_B0.pre_intra_cla15_m0 = 0;
570 reg->pre_intra_cla15_B0.pre_intra_cla15_m1 = 0;
571 reg->pre_intra_cla15_B0.pre_intra_cla15_m2 = 0;
572 reg->pre_intra_cla15_B0.pre_intra_cla15_m3 = 0;
573 reg->pre_intra_cla15_B0.pre_intra_cla15_m4 = 0;
574 reg->pre_intra_cla15_B1.pre_intra_cla15_m5 = 0;
575 reg->pre_intra_cla15_B1.pre_intra_cla15_m6 = 0;
576 reg->pre_intra_cla15_B1.pre_intra_cla15_m7 = 0;
577 reg->pre_intra_cla15_B1.pre_intra_cla15_m8 = 0;
578 reg->pre_intra_cla15_B1.pre_intra_cla15_m9 = 0;
579
580 reg->pre_intra_cla16_B0.pre_intra_cla16_m0 = 0;
581 reg->pre_intra_cla16_B0.pre_intra_cla16_m1 = 0;
582 reg->pre_intra_cla16_B0.pre_intra_cla16_m2 = 0;
583 reg->pre_intra_cla16_B0.pre_intra_cla16_m3 = 0;
584 reg->pre_intra_cla16_B0.pre_intra_cla16_m4 = 0;
585 reg->pre_intra_cla16_B1.pre_intra_cla16_m5 = 0;
586 reg->pre_intra_cla16_B1.pre_intra_cla16_m6 = 0;
587 reg->pre_intra_cla16_B1.pre_intra_cla16_m7 = 0;
588 reg->pre_intra_cla16_B1.pre_intra_cla16_m8 = 0;
589 reg->pre_intra_cla16_B1.pre_intra_cla16_m9 = 0;
590
591 reg->i16_sobel_t.intra_l16_sobel_t0 = 64;
592 reg->i16_sobel_t.intra_l16_sobel_t1 = 200;
593 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp0 = 32;
594 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp1 = 32;
595 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp2 = 32;
596 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp3 = 32;
597 reg->i16_sobel_a_00.intra_l16_sobel_a0_qp4 = 32;
598 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp5 = 32;
599 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp6 = 32;
600 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp7 = 32;
601 reg->i16_sobel_a_01.intra_l16_sobel_a0_qp8 = 32;
602 reg->i16_sobel_b_00.intra_l16_sobel_b0_qp0 = 0;
603 reg->i16_sobel_b_00.intra_l16_sobel_b0_qp1 = 0;
604 reg->i16_sobel_b_01.intra_l16_sobel_b0_qp2 = 0;
605 reg->i16_sobel_b_01.intra_l16_sobel_b0_qp3 = 0;
606 reg->i16_sobel_b_02.intra_l16_sobel_b0_qp4 = 0;
607 reg->i16_sobel_b_02.intra_l16_sobel_b0_qp5 = 0;
608 reg->i16_sobel_b_03.intra_l16_sobel_b0_qp6 = 0;
609 reg->i16_sobel_b_03.intra_l16_sobel_b0_qp7 = 0;
610 reg->i16_sobel_b_04.intra_l16_sobel_b0_qp8 = 0;
611 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp0 = 13;
612 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp1 = 13;
613 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp2 = 13;
614 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp3 = 13;
615 reg->i16_sobel_c_00.intra_l16_sobel_c0_qp4 = 13;
616 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp5 = 13;
617 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp6 = 13;
618 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp7 = 13;
619 reg->i16_sobel_c_01.intra_l16_sobel_c0_qp8 = 13;
620 reg->i16_sobel_d_00.intra_l16_sobel_d0_qp0 = 23750;
621 reg->i16_sobel_d_00.intra_l16_sobel_d0_qp1 = 23750;
622 reg->i16_sobel_d_01.intra_l16_sobel_d0_qp2 = 23750;
623 reg->i16_sobel_d_01.intra_l16_sobel_d0_qp3 = 23750;
624 reg->i16_sobel_d_02.intra_l16_sobel_d0_qp4 = 23750;
625 reg->i16_sobel_d_02.intra_l16_sobel_d0_qp5 = 23750;
626 reg->i16_sobel_d_03.intra_l16_sobel_d0_qp6 = 23750;
627 reg->i16_sobel_d_03.intra_l16_sobel_d0_qp7 = 23750;
628 reg->i16_sobel_d_04.intra_l16_sobel_d0_qp8 = 23750;
629
630 reg->intra_l16_sobel_e0_qp0_low = 20000;
631 reg->intra_l16_sobel_e0_qp1_low = 20000;
632 reg->intra_l16_sobel_e0_qp2_low = 20000;
633 reg->intra_l16_sobel_e0_qp3_low = 20000;
634 reg->intra_l16_sobel_e0_qp4_low = 20000;
635 reg->intra_l16_sobel_e0_qp5_low = 20000;
636 reg->intra_l16_sobel_e0_qp6_low = 20000;
637 reg->intra_l16_sobel_e0_qp7_low = 20000;
638 reg->intra_l16_sobel_e0_qp8_low = 20000;
639 reg->i16_sobel_e_01.intra_l16_sobel_e0_qp0_high = 0;
640 reg->i16_sobel_e_03.intra_l16_sobel_e0_qp1_high = 0;
641 reg->i16_sobel_e_05.intra_l16_sobel_e0_qp2_high = 0;
642 reg->i16_sobel_e_07.intra_l16_sobel_e0_qp3_high = 0;
643 reg->i16_sobel_e_09.intra_l16_sobel_e0_qp4_high = 0;
644 reg->i16_sobel_e_11.intra_l16_sobel_e0_qp5_high = 0;
645 reg->i16_sobel_e_13.intra_l16_sobel_e0_qp6_high = 0;
646 reg->i16_sobel_e_15.intra_l16_sobel_e0_qp7_high = 0;
647 reg->i16_sobel_e_17.intra_l16_sobel_e0_qp8_high = 0;
648
649 reg->i32_sobel_t_00.intra_l32_sobel_t2 = 64;
650 reg->i32_sobel_t_00.intra_l32_sobel_t3 = 400;
651 reg->i32_sobel_t_01.intra_l32_sobel_t4 = 8;
652 reg->i32_sobel_t_02.intra_l32_sobel_t5 = 100;
653 reg->i32_sobel_t_02.intra_l32_sobel_t6 = 100;
654
655 reg->i32_sobel_a.intra_l32_sobel_a1_qp0 = 18;
656 reg->i32_sobel_a.intra_l32_sobel_a1_qp1 = 18;
657 reg->i32_sobel_a.intra_l32_sobel_a1_qp2 = 18;
658 reg->i32_sobel_a.intra_l32_sobel_a1_qp3 = 18;
659 reg->i32_sobel_a.intra_l32_sobel_a1_qp4 = 18;
660
661 reg->i32_sobel_b_00.intra_l32_sobel_b1_qp0 = 0;
662 reg->i32_sobel_b_00.intra_l32_sobel_b1_qp1 = 0;
663 reg->i32_sobel_b_01.intra_l32_sobel_b1_qp2 = 0;
664 reg->i32_sobel_b_01.intra_l32_sobel_b1_qp3 = 0;
665 reg->i32_sobel_b_02.intra_l32_sobel_b1_qp4 = 0;
666
667 reg->i32_sobel_c.intra_l32_sobel_c1_qp0 = 16;
668 reg->i32_sobel_c.intra_l32_sobel_c1_qp1 = 16;
669 reg->i32_sobel_c.intra_l32_sobel_c1_qp2 = 16;
670 reg->i32_sobel_c.intra_l32_sobel_c1_qp3 = 16;
671 reg->i32_sobel_c.intra_l32_sobel_c1_qp4 = 16;
672
673 reg->i32_sobel_d_00.intra_l32_sobel_d1_qp0 = 0;
674 reg->i32_sobel_d_00.intra_l32_sobel_d1_qp1 = 0;
675 reg->i32_sobel_d_01.intra_l32_sobel_d1_qp2 = 0;
676 reg->i32_sobel_d_01.intra_l32_sobel_d1_qp3 = 0;
677 reg->i32_sobel_d_02.intra_l32_sobel_d1_qp4 = 0;
678
679 reg->intra_l32_sobel_e1_qp0_low = 20000;
680 reg->intra_l32_sobel_e1_qp1_low = 20000;
681 reg->intra_l32_sobel_e1_qp2_low = 20000;
682 reg->intra_l32_sobel_e1_qp3_low = 20000;
683 reg->intra_l32_sobel_e1_qp4_low = 20000;
684
685 reg->i32_sobel_e_01.intra_l32_sobel_e1_qp0_high = 0;
686 reg->i32_sobel_e_03.intra_l32_sobel_e1_qp1_high = 0;
687 reg->i32_sobel_e_05.intra_l32_sobel_e1_qp2_high = 0;
688 reg->i32_sobel_e_07.intra_l32_sobel_e1_qp3_high = 0;
689 reg->i32_sobel_e_09.intra_l32_sobel_e1_qp4_high = 0;
690 }
691
vepu580_h265_rdo_bias_cfg(vepu580_rdo_cfg * reg,MppEncHwCfg * hw)692 static void vepu580_h265_rdo_bias_cfg (vepu580_rdo_cfg *reg, MppEncHwCfg *hw)
693 {
694 RdoAtfCfg* p_rdo_atf;
695 RdoAtfSkipCfg* p_rdo_atf_skip;
696 RK_U8 bias = h265e_mode_bias[hw->mode_bias[4]];
697
698 p_rdo_atf = ®->rdo_b64_inter_atf;
699 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
700 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
701 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
702 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
703 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
704 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
705 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
706 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
707 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
708 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
709 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
710 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
711
712 if (hw->skip_bias_en) {
713 bias = h265e_mode_bias[hw->skip_bias];
714
715 p_rdo_atf_skip = ®->rdo_b64_skip_atf;
716 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
717 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
718 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
719 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
720 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = bias > 24 ? bias : 24;
721 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = bias < 4 ? bias : 4;
722 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = bias < 6 ? bias : 6;
723 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = bias < 8 ? bias : 8;
724 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
725 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 10 ? bias : 10;
726 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 10 ? bias : 10;
727 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 10 ? bias : 10;
728 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 14 ? bias : 14;
729 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 14 ? bias : 14;
730 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 15 ? bias : 15;
731 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
732 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
733 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
734 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
735 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
736 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
737 }
738
739 bias = h265e_mode_bias[hw->mode_bias[0]];
740
741 p_rdo_atf = ®->rdo_b32_intra_atf;
742 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
743 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
744 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
745 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
746 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
747 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
748 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
749 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
750 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
751 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
752 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
753 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
754
755 bias = h265e_mode_bias[hw->mode_bias[5]];
756
757 p_rdo_atf = ®->rdo_b32_inter_atf;
758 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
759 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
760 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
761 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
762 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
763 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
764 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
765 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
766 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
767 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
768 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
769 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
770
771 if (hw->skip_bias_en) {
772 bias = h265e_mode_bias[hw->skip_bias];
773
774 p_rdo_atf_skip = ®->rdo_b32_skip_atf;
775 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
776 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4;
777 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6;
778 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
779 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 18 ? bias : 18;
780 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias < 11 ? bias : 11;
781 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias < 11 ? bias : 11;
782 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias < 11 ? bias : 11;
783 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias < 13 ? bias : 13;
784 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias < 13 ? bias : 13;
785 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias < 13 ? bias : 13;
786 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias < 15 ? bias : 15;
787 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias < 15 ? bias : 15;
788 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias < 15 ? bias : 15;
789 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
790 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
791 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
792 }
793
794 bias = h265e_mode_bias[hw->mode_bias[1]];
795
796 p_rdo_atf = ®->rdo_b16_intra_atf;
797 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
798 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
799 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
800 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
801 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
802 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
803 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
804 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
805 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
806 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
807 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
808 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
809
810 bias = h265e_mode_bias[hw->mode_bias[6]];
811
812 p_rdo_atf = ®->rdo_b16_inter_atf;
813 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
814 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
815 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
816 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
817 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
818 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
819 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
820 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
821 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
822 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
823 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
824 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
825
826 if (hw->skip_bias_en) {
827 bias = h265e_mode_bias[hw->skip_bias];
828
829 p_rdo_atf_skip = ®->rdo_b16_skip_atf;
830 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
831 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
832 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
833 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
834 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
835 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
836 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
837 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
838 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
839 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
840 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
841 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
842 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
843 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
844 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
845 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
846 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
847 }
848
849 bias = h265e_mode_bias[hw->mode_bias[2]];
850
851 p_rdo_atf = ®->rdo_b8_intra_atf;
852 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias > 26 ? bias : 26;
853 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias > 25 ? bias : 25;
854 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias > 25 ? bias : 25;
855 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias > 25 ? bias : 25;
856 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias > 24 ? bias : 24;
857 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias > 23 ? bias : 23;
858 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias > 21 ? bias : 21;
859 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias > 19 ? bias : 19;
860 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias > 18 ? bias : 18;
861 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
862 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
863 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
864
865 bias = h265e_mode_bias[hw->mode_bias[7]];
866
867 p_rdo_atf = ®->rdo_b8_inter_atf;
868 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
869 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = bias;
870 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = bias;
871 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = bias;
872 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = bias;
873 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = bias;
874 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = bias;
875 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = bias;
876 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = bias;
877 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = bias;
878 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = bias;
879 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = bias;
880
881 if (hw->skip_bias_en) {
882 bias = h265e_mode_bias[hw->skip_bias];
883
884 p_rdo_atf_skip = ®->rdo_b8_skip_atf;
885 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24;
886 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 24 ? hw->skip_sad : 24;
887 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 48 ? hw->skip_sad : 48;
888 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad;
889 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = bias;
890 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = bias;
891 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = bias;
892 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = bias;
893 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = bias;
894 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = bias;
895 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = bias;
896 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = bias;
897 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = bias;
898 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = bias;
899 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = bias;
900 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = bias;
901 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = bias;
902 }
903 }
904
vepu580_h265_rdo_cfg(vepu580_rdo_cfg * reg)905 static void vepu580_h265_rdo_cfg (vepu580_rdo_cfg *reg)
906 {
907 RdoAtfCfg* p_rdo_atf;
908 RdoAtfSkipCfg* p_rdo_atf_skip;
909 reg->rdo_sqi_cfg.rdo_segment_en = 1;
910 reg->rdo_sqi_cfg.rdo_smear_en = 1;
911 p_rdo_atf = ®->rdo_b64_inter_atf;
912 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
913 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
914 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
915 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
916 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
917 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
918 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
919 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
920 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
921 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
922 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
923 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
924 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
925 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
926 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
927 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
928 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
929 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
930 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
931 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
932 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
933 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
934 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
935
936 p_rdo_atf_skip = ®->rdo_b64_skip_atf;
937 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
938 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 4;
939 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 6;
940 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 8;
941 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
942 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
943 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
944 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
945 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
946 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
947 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
948 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
949 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
950 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 10;
951 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 10;
952 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 10;
953 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 14;
954 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 14;
955 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 15;
956 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 15;
957 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 15;
958 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
959 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
960 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
961 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
962
963 p_rdo_atf = ®->rdo_b32_intra_atf;
964 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
965 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
966 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
967 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
968 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
969 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
970 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
971 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
972 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
973 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
974 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
975 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
976 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
977 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
978 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
979 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
980 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
981 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
982 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
983 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
984 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
985 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
986 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
987
988 p_rdo_atf = ®->rdo_b32_inter_atf;
989 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
990 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
991 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
992 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
993 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
994 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
995 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
996 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
997 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
998 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
999 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1000 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1001 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
1002 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
1003 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
1004 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
1005 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
1006 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
1007 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
1008 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
1009 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1010 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1011 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1012
1013 p_rdo_atf_skip = ®->rdo_b32_skip_atf;
1014 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1015 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 4;
1016 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 6;
1017 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 8;
1018 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
1019 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
1020 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
1021 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
1022 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
1023 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
1024 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
1025 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
1026 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 18;
1027 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 11;
1028 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 11;
1029 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 11;
1030 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 13;
1031 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 13;
1032 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 13;
1033 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 15;
1034 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 15;
1035 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 15;
1036 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
1037 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
1038 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
1039
1040 p_rdo_atf = ®->rdo_b16_intra_atf;
1041 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1042 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
1043 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
1044 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1045 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1046 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1047 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1048 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1049 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1050 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1051 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1052 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
1053 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
1054 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
1055 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
1056 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
1057 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
1058 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
1059 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
1060 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
1061 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1062 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1063 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1064
1065 p_rdo_atf = ®->rdo_b16_inter_atf;
1066 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
1067 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
1068 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
1069 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1070 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1071 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1072 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1073 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1074 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1075 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1076 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1077 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1078 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
1079 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
1080 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
1081 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
1082 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
1083 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
1084 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
1085 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
1086 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1087 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1088 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1089
1090 p_rdo_atf_skip = ®->rdo_b16_skip_atf;
1091 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1092 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 24;
1093 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 48;
1094 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 96;
1095 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
1096 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
1097 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
1098 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
1099 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
1100 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
1101 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
1102 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
1103 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1104 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 16;
1105 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 16;
1106 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 16;
1107 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 16;
1108 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 16;
1109 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 16;
1110 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 16;
1111 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 16;
1112 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
1113 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
1114 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
1115 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
1116
1117 p_rdo_atf = ®->rdo_b8_intra_atf;
1118 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1119 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
1120 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
1121 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1122 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1123 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1124 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1125 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1126 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1127 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1128 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1129 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 26;
1130 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 25;
1131 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 25;
1132 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 25;
1133 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 24;
1134 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 23;
1135 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 21;
1136 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 19;
1137 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 18;
1138 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1139 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1140 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1141
1142 p_rdo_atf = ®->rdo_b8_inter_atf;
1143 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 32;
1144 p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 144;
1145 p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 300;
1146 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd00 = 31;
1147 p_rdo_atf->rdo_b_var_thd0.cu_rdo_var_thd01 = 400;
1148 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd10 = 31;
1149 p_rdo_atf->rdo_b_var_thd1.cu_rdo_var_thd11 = 400;
1150 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd20 = 31;
1151 p_rdo_atf->rdo_b_var_thd2.cu_rdo_var_thd21 = 400;
1152 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd30 = 31;
1153 p_rdo_atf->rdo_b_var_thd3.cu_rdo_var_thd31 = 400;
1154 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1155 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01 = 16;
1156 p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02 = 16;
1157 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10 = 16;
1158 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11 = 16;
1159 p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12 = 16;
1160 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20 = 16;
1161 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21 = 16;
1162 p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22 = 16;
1163 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30 = 16;
1164 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31 = 16;
1165 p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32 = 16;
1166
1167 p_rdo_atf_skip = ®->rdo_b8_skip_atf;
1168 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
1169 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 24;
1170 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 48;
1171 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 96;
1172 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd10 = 31;
1173 p_rdo_atf_skip->rdo_b_var_thd0.cu_rdo_var_thd11 = 400;
1174 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd20 = 31;
1175 p_rdo_atf_skip->rdo_b_var_thd1.cu_rdo_var_thd21 = 400;
1176 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd30 = 31;
1177 p_rdo_atf_skip->rdo_b_var_thd2.cu_rdo_var_thd31 = 400;
1178 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd40 = 31;
1179 p_rdo_atf_skip->rdo_b_var_thd3.cu_rdo_var_thd41 = 400;
1180 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00 = 16;
1181 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10 = 16;
1182 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11 = 16;
1183 p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12 = 16;
1184 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20 = 16;
1185 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21 = 16;
1186 p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22 = 16;
1187 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30 = 16;
1188 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31 = 16;
1189 p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32 = 16;
1190 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40 = 16;
1191 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41 = 16;
1192 p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42 = 16;
1193
1194 reg->rdo_segment_b64_thd0.rdo_segment_cu64_th0 = 160;
1195 reg->rdo_segment_b64_thd0.rdo_segment_cu64_th1 = 96;
1196 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th2 = 30;
1197 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th3 = 0;
1198 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th4 = 1;
1199 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th5_minus1 = 4;
1200 reg->rdo_segment_b64_thd1.rdo_segment_cu64_th6_minus1 = 11;
1201
1202 reg->rdo_segment_b32_thd0.rdo_segment_cu32_th0 = 160;
1203 reg->rdo_segment_b32_thd0.rdo_segment_cu32_th1 = 96;
1204 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th2 = 30;
1205 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th3 = 0;
1206 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th4 = 1;
1207 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th5_minus1 = 2;
1208 reg->rdo_segment_b32_thd1.rdo_segment_cu32_th6_minus1 = 3;
1209
1210 reg->rdo_segment_multi.rdo_segment_cu64_multi = 22;
1211 reg->rdo_segment_multi.rdo_segment_cu32_multi = 22;
1212 reg->rdo_segment_multi.rdo_smear_cu16_multi = 6;
1213
1214 reg->rdo_b16_smear_thd0.rdo_smear_cu16_cime_sad_th0 = 64;
1215 reg->rdo_b16_smear_thd0.rdo_smear_cu16_cime_sad_th1 = 32;
1216 reg->rdo_b16_smear_thd1.rdo_smear_cu16_cime_sad_th2 = 36;
1217 reg->rdo_b16_smear_thd1.rdo_smear_cu16_cime_sad_th3 = 64;
1218
1219
1220 reg->preintra_b32_cst_var_thd.pre_intra32_cst_var_th00 = 9;
1221 reg->preintra_b32_cst_var_thd.pre_intra32_cst_var_th01 = 4;
1222 reg->preintra_b32_cst_var_thd.pre_intra32_mode_th = 5;
1223
1224 reg->preintra_b32_cst_wgt.pre_intra32_cst_wgt00 = 31;
1225 reg->preintra_b32_cst_wgt.pre_intra32_cst_wgt01 = 25;
1226
1227 reg->preintra_b16_cst_var_thd.pre_intra16_cst_var_th00 = 9;
1228 reg->preintra_b16_cst_var_thd.pre_intra16_cst_var_th01 = 4;
1229 reg->preintra_b16_cst_var_thd.pre_intra16_mode_th = 5;
1230
1231 reg->preintra_b16_cst_wgt.pre_intra16_cst_wgt00 = 31;
1232 reg->preintra_b16_cst_wgt.pre_intra16_cst_wgt01 = 25;
1233 }
1234
vepu580_h265_scl_cfg(vepu580_rdo_cfg * reg)1235 static void vepu580_h265_scl_cfg(vepu580_rdo_cfg *reg)
1236 {
1237 static RK_U32 vepu580_h265_scl_tab[] = {
1238 /* 0x2200 */
1239 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1240 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1241 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1242 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1243 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1244 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1245 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1246 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1247 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x10001000, 0x0d790f0f, 0x0a3d0ba3,
1248 0x10001000, 0x0e390f0f, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x0c310e39, 0x097b0aab, 0x071c0842,
1249 0x0f0f0f0f, 0x0aab0ccd, 0x07500889, 0x0572063e, 0x0d790e39, 0x097b0ba3, 0x05d10750, 0x03f004be,
1250 0x0ba30c31, 0x08420a3d, 0x04be063e, 0x02e903a8, 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x023a02e9,
1251 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1252 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1253 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1254 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1255 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1256 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1257 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1258 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1259 0x10001000, 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x10001000, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab,
1260 0x10001000, 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x0f0f1000, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925,
1261 0x0e390f0f, 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x0ccd0e39, 0x0a3d0aab, 0x07c20925, 0x04be063e,
1262 0x0aab0ccd, 0x09250a3d, 0x063e07c2, 0x039b04be, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x02d0039b,
1263 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x18151211,
1264 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0aab0c31, 0x19161311,
1265 0x10001000, 0x0e390f0f, 0x10001000, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x10001000, 0x1d191614,
1266 0x10001000, 0x0c310e39, 0x0d790f0f, 0x15121010, 0x097b0aab, 0x071c0842, 0x0a3d0ba3, 0x241f1b18,
1267 0x0f0f0f0f, 0x0aab0ccd, 0x10001000, 0x18141111, 0x07500889, 0x0572063e, 0x0e390f0f, 0x2f29231e,
1268 0x0d790e39, 0x097b0ba3, 0x0ba30ccd, 0x1b161312, 0x05d10750, 0x03f004be, 0x08d40a3d, 0x41362c23,
1269 0x0ba30c31, 0x08420a3d, 0x10001000, 0x1f191615, 0x04be063e, 0x02e903a8, 0x0c310e39, 0x58463629,
1270 0x0a3d0aab, 0x071c08d4, 0x097b0aab, 0x241d1918, 0x03f00572, 0x023a02e9, 0x071c0842, 0x7358412f,
1271 0x10001000, 0x10001000, 0x0f0f0f0f, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x0aab0ccd, 0x18151211,
1272 0x10001000, 0x10001000, 0x07500889, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0572063e, 0x19161311,
1273 0x10001000, 0x0e390f0f, 0x0d790e39, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x097b0ba3, 0x1d191614,
1274 0x10001000, 0x0c310e39, 0x05d10750, 0x15121010, 0x097b0aab, 0x071c0842, 0x03f004be, 0x241f1b18,
1275 0x0f0f0f0f, 0x0aab0ccd, 0x0ba30c31, 0x18141111, 0x07500889, 0x0572063e, 0x08420a3d, 0x2f29231e,
1276 0x0d790e39, 0x097b0ba3, 0x04be063e, 0x1b161312, 0x05d10750, 0x03f004be, 0x02e903a8, 0x41362c23,
1277 0x0ba30c31, 0x08420a3d, 0x0a3d0aab, 0x1f191615, 0x04be063e, 0x02e903a8, 0x071c08d4, 0x58463629,
1278 0x0a3d0aab, 0x071c08d4, 0x03f00572, 0x241d1918, 0x03f00572, 0x023a02e9, 0x023a02e9, 0x7358412f,
1279 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x0e390f0f, 0x0aab0c31, 0x10001000, 0x18151211,
1280 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0d790f0f, 0x0a3d0ba3, 0x0aab0ccd, 0x19161311,
1281 0x10001000, 0x0e390f0f, 0x10001000, 0x12111010, 0x0ba30ccd, 0x08d40a3d, 0x0f0f1000, 0x1d191614,
1282 0x10001000, 0x0c310e39, 0x0ccd0e39, 0x15121010, 0x097b0aab, 0x071c0842, 0x0a3d0aab, 0x241f1b18,
1283 0x0f0f0f0f, 0x0aab0ccd, 0x10001000, 0x18141111, 0x07500889, 0x0572063e, 0x0e390f0f, 0x2f29231e,
1284 0x0d790e39, 0x097b0ba3, 0x0aab0ccd, 0x1b161312, 0x05d10750, 0x03f004be, 0x09250a3d, 0x41362c23,
1285 0x0ba30c31, 0x08420a3d, 0x0f0f1000, 0x1f191615, 0x04be063e, 0x02e903a8, 0x0ccd0e39, 0x58463629,
1286 0x0a3d0aab, 0x071c08d4, 0x0a3d0aab, 0x241d1918, 0x03f00572, 0x023a02e9, 0x07c20925, 0x7358412f,
1287 0x10001000, 0x10001000, 0x0e390f0f, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x0aab0ccd, 0x18141211,
1288 0x10001000, 0x0f0f1000, 0x09250a3d, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x063e07c2, 0x19181412,
1289 0x10001000, 0x0e390f0f, 0x0ccd0e39, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x0a3d0aab, 0x1c191814,
1290 0x0f0f1000, 0x0ccd0e39, 0x07c20925, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x211c1918,
1291 0x0e390f0f, 0x0aab0ccd, 0x0aab0ccd, 0x18141211, 0x09250a3d, 0x063e07c2, 0x09250a3d, 0x29211c19,
1292 0x0ccd0e39, 0x0a3d0aab, 0x063e07c2, 0x19181412, 0x07c20925, 0x04be063e, 0x039b04be, 0x3629211c,
1293 0x0aab0ccd, 0x09250a3d, 0x0a3d0aab, 0x1c191814, 0x063e07c2, 0x039b04be, 0x07c20925, 0x47362921,
1294 0x0a3d0aab, 0x07c20925, 0x04be063e, 0x211c1918, 0x04be063e, 0x02d0039b, 0x02d0039b, 0x5b473629,
1295 0x10001000, 0x10001000, 0x10101010, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x10101010, 0x18141211,
1296 0x10001000, 0x0f0f1000, 0x12111211, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x18141815, 0x19181412,
1297 0x10001000, 0x0e390f0f, 0x10101010, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x11101010, 0x1c191814,
1298 0x0f0f1000, 0x0ccd0e39, 0x14121311, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x19181916, 0x211c1918,
1299 0x0e390f0f, 0x0aab0ccd, 0x10101010, 0x18141211, 0x09250a3d, 0x063e07c2, 0x12111211, 0x29211c19,
1300 0x0ccd0e39, 0x0a3d0aab, 0x18141614, 0x19181412, 0x07c20925, 0x04be063e, 0x1c191d19, 0x3629211c,
1301 0x0aab0ccd, 0x09250a3d, 0x11101010, 0x1c191814, 0x063e07c2, 0x039b04be, 0x14121512, 0x47362921,
1302 0x0a3d0aab, 0x07c20925, 0x19181b18, 0x211c1918, 0x04be063e, 0x02d0039b, 0x211c241f, 0x5b473629,
1303 0x10001000, 0x10001000, 0x12111111, 0x10101010, 0x0e390f0f, 0x0aab0ccd, 0x18141814, 0x18141211,
1304 0x10001000, 0x0f0f1000, 0x1c19231e, 0x11101010, 0x0ccd0e39, 0x0a3d0aab, 0x29212f29, 0x19181412,
1305 0x10001000, 0x0e390f0f, 0x14121312, 0x12111010, 0x0aab0ccd, 0x09250a3d, 0x19181b16, 0x1c191814,
1306 0x0f0f1000, 0x0ccd0e39, 0x211c2c23, 0x14121110, 0x0a3d0aab, 0x07c20925, 0x36294136, 0x211c1918,
1307 0x0e390f0f, 0x0aab0ccd, 0x18141615, 0x18141211, 0x09250a3d, 0x063e07c2, 0x1c191f19, 0x29211c19,
1308 0x0ccd0e39, 0x0a3d0aab, 0x29213629, 0x19181412, 0x07c20925, 0x04be063e, 0x47365846, 0x3629211c,
1309 0x0aab0ccd, 0x09250a3d, 0x19181918, 0x1c191814, 0x063e07c2, 0x039b04be, 0x211c241d, 0x47362921,
1310 0x0a3d0aab, 0x07c20925, 0x3629412f, 0x211c1918, 0x04be063e, 0x02d0039b, 0x5b477358, 0x5b473629,
1311 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1312 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1313 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1314 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1315 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1316 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1317 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1318 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1319 0x10101010, 0x18151211, 0x10101010, 0x18141211, 0x10101010, 0x19161311, 0x11101010, 0x19181412,
1320 0x12111010, 0x1d191614, 0x12111010, 0x1c191814, 0x15121010, 0x241f1b18, 0x14121110, 0x211c1918,
1321 0x18141111, 0x2f29231e, 0x18141211, 0x29211c19, 0x1b161312, 0x41362c23, 0x19181412, 0x3629211c,
1322 0x1f191615, 0x58463629, 0x1c191814, 0x47362921, 0x241d1918, 0x7358412f, 0x211c1918, 0x5b473629,
1323 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10101010, 0x10101010,
1324 };
1325
1326 hal_h265e_dbg_func("enter\n");
1327
1328 memcpy(®->scaling_list_reg[0], vepu580_h265_scl_tab, sizeof(vepu580_h265_scl_tab));
1329
1330 hal_h265e_dbg_func("leave\n");
1331 }
vepu580_h265_global_cfg_set(H265eV580HalContext * ctx,H265eV580RegSet * regs)1332 static void vepu580_h265_global_cfg_set(H265eV580HalContext *ctx, H265eV580RegSet *regs)
1333 {
1334 MppEncHwCfg *hw = &ctx->cfg->hw;
1335 RK_U32 i;
1336 hevc_vepu580_rc_klut *rc_regs = ®s->reg_rc_klut;
1337 hevc_vepu580_wgt *reg_wgt = ®s->reg_wgt;
1338 vepu580_rdo_cfg *reg_rdo = ®s->reg_rdo;
1339
1340 vepu580_h265_sobel_cfg(reg_wgt);
1341 vepu580_h265_rdo_cfg(reg_rdo);
1342 vepu580_h265_rdo_bias_cfg(reg_rdo, hw);
1343 vepu580_h265_scl_cfg(reg_rdo);
1344
1345 memcpy(®_wgt->iprd_wgt_qp_hevc_0_51[0], lamd_satd_qp, sizeof(lamd_satd_qp));
1346
1347 if (ctx->frame_type == INTRA_FRAME) {
1348 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
1349 rc_regs->aq_tthd[i] = hw->aq_thrd_i[i];
1350 rc_regs->aq_step[i] = hw->aq_step_i[i] & 0x3f;
1351 }
1352 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));
1353 } else {
1354 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
1355 rc_regs->aq_tthd[i] = hw->aq_thrd_p[i];
1356 rc_regs->aq_step[i] = hw->aq_step_p[i] & 0x3f;
1357 }
1358 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));
1359 }
1360 //to be done
1361 rc_regs->madi_cfg.madi_mode = 0;
1362 rc_regs->madi_cfg.madi_thd = 25;
1363 rc_regs->md_sad_thd.md_sad_thd0 = 20;
1364 rc_regs->md_sad_thd.md_sad_thd1 = 30;
1365 rc_regs->md_sad_thd.md_sad_thd2 = 40;
1366 rc_regs->madi_thd.madi_thd0 = 25;
1367 rc_regs->madi_thd.madi_thd1 = 35;
1368 rc_regs->madi_thd.madi_thd2 = 45;
1369 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
1370 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
1371
1372 memcpy(®_wgt->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd));
1373 memcpy(®_wgt->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));
1374 memcpy(®_wgt->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));
1375 memcpy(®_wgt->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));
1376
1377 reg_wgt->cime_sqi_cfg.cime_sad_mod_sel = 0;
1378 reg_wgt->cime_sqi_cfg.cime_sad_use_big_block = 0;
1379 reg_wgt->cime_sqi_cfg.cime_pmv_set_zero = 1;
1380 reg_wgt->cime_sqi_cfg.cime_pmv_num = 3;
1381 reg_wgt->cime_sqi_thd.cime_mvd_th0 = 32;
1382 reg_wgt->cime_sqi_thd.cime_mvd_th1 = 80;
1383 reg_wgt->cime_sqi_thd.cime_mvd_th2 = 128;
1384 reg_wgt->cime_sqi_multi0.cime_multi0 = 16;
1385 reg_wgt->cime_sqi_multi0.cime_multi1 = 32;
1386 reg_wgt->cime_sqi_multi1.cime_multi2 = 96;
1387 reg_wgt->cime_sqi_multi1.cime_multi3 = 96;
1388 reg_wgt->rime_sqi_thd.cime_sad_th0 = 48;
1389 reg_wgt->rime_sqi_thd.rime_mvd_th0 = 3;
1390 reg_wgt->rime_sqi_thd.rime_mvd_th1 = 8;
1391 reg_wgt->rime_sqi_multi.rime_multi0 = 16;
1392 reg_wgt->rime_sqi_multi.rime_multi1 = 16;
1393 reg_wgt->rime_sqi_multi.rime_multi2 = 128;
1394 reg_wgt->fme_sqi_thd0.cime_sad_pu16_th = 16;
1395 reg_wgt->fme_sqi_thd0.cime_sad_pu32_th = 16;
1396 reg_wgt->fme_sqi_thd1.cime_sad_pu64_th = 16;
1397 reg_wgt->fme_sqi_thd1.move_lambda = 1;
1398 }
1399
hal_h265e_v580_deinit(void * hal)1400 MPP_RET hal_h265e_v580_deinit(void *hal)
1401 {
1402 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1403 RK_S32 i;
1404
1405 hal_h265e_enter();
1406
1407 for (i = 0; i < ctx->task_cnt; i++) {
1408 Vepu580H265eFrmCfg *frm = ctx->frms[i];
1409 RK_U32 j;
1410
1411 if (!frm)
1412 continue;
1413
1414 for (j = 0; j < MAX_TILE_NUM; j++) {
1415 MPP_FREE(frm->regs_set[j]);
1416 MPP_FREE(frm->regs_ret[j]);
1417 }
1418
1419 for (j = 0; j < MAX_TILE_NUM; j++) {
1420 if (frm->hw_tile_buf[j]) {
1421 mpp_buffer_put(frm->hw_tile_buf[j]);
1422 frm->hw_tile_buf[j] = NULL;
1423 }
1424 }
1425
1426 for (j = 0; j < MAX_TILE_NUM - 1; j++) {
1427 if (frm->hw_tile_stream[j]) {
1428 mpp_buffer_put(frm->hw_tile_stream[j]);
1429 frm->hw_tile_stream[j] = NULL;
1430 }
1431 }
1432
1433 if (frm->roi_base_cfg_buf) {
1434 mpp_buffer_put(frm->roi_base_cfg_buf);
1435 frm->roi_base_cfg_buf = NULL;
1436 frm->roi_base_buf_size = 0;
1437 }
1438
1439 MPP_FREE(frm->roi_base_cfg_sw_buf);
1440
1441 if (frm->reg_cfg) {
1442 mpp_dev_multi_offset_deinit(frm->reg_cfg);
1443 frm->reg_cfg = NULL;
1444 }
1445
1446 MPP_FREE(ctx->frms[i]);
1447 }
1448
1449 MPP_FREE(ctx->poll_cfgs);
1450 MPP_FREE(ctx->input_fmt);
1451 hal_bufs_deinit(ctx->dpb_bufs);
1452
1453 if (ctx->tile_grp) {
1454 mpp_buffer_group_put(ctx->tile_grp);
1455 ctx->tile_grp = NULL;
1456 }
1457
1458 if (ctx->roi_grp) {
1459 mpp_buffer_group_put(ctx->roi_grp);
1460 ctx->roi_grp = NULL;
1461 }
1462
1463 if (ctx->buf_pass1) {
1464 mpp_buffer_put(ctx->buf_pass1);
1465 ctx->buf_pass1 = NULL;
1466 }
1467
1468 if (ctx->dev) {
1469 mpp_dev_deinit(ctx->dev);
1470 ctx->dev = NULL;
1471 }
1472
1473 if (ctx->tune) {
1474 vepu580_h265e_tune_deinit(ctx->tune);
1475 ctx->tune = NULL;
1476 }
1477
1478 if (ctx->md_info_buf) {
1479 mpp_buffer_put(ctx->md_info_buf);
1480 ctx->md_info_buf = NULL;
1481 }
1482
1483 if (ctx->qpmap_base_cfg_buf) {
1484 mpp_buffer_put(ctx->qpmap_base_cfg_buf);
1485 ctx->qpmap_base_cfg_buf = NULL;
1486 }
1487
1488 if (ctx->qpmap_qp_cfg_buf) {
1489 mpp_buffer_put(ctx->qpmap_qp_cfg_buf);
1490 ctx->qpmap_qp_cfg_buf = NULL;
1491 }
1492
1493 if (ctx->md_flag_buf) {
1494 MPP_FREE(ctx->md_flag_buf);
1495 }
1496
1497 if (ctx->qpmap_grp) {
1498 mpp_buffer_group_put(ctx->qpmap_grp);
1499 ctx->qpmap_grp = NULL;
1500 }
1501
1502 hal_h265e_leave();
1503 return MPP_OK;
1504 }
1505
hal_h265e_v580_init(void * hal,MppEncHalCfg * cfg)1506 MPP_RET hal_h265e_v580_init(void *hal, MppEncHalCfg *cfg)
1507 {
1508 MPP_RET ret = MPP_OK;
1509 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1510 RK_S32 i = 0;
1511
1512 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
1513
1514 hal_h265e_enter();
1515
1516 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
1517 ctx->cfg = cfg->cfg;
1518 hal_bufs_init(&ctx->dpb_bufs);
1519
1520 ctx->frame_count = 0;
1521 ctx->enc_mode = RKV_ENC_MODE;
1522 cfg->type = VPU_CLIENT_RKVENC;
1523 ret = mpp_dev_init(&cfg->dev, cfg->type);
1524 if (ret) {
1525 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
1526 goto DONE;
1527 }
1528
1529 ctx->dev = cfg->dev;
1530 ctx->task_cnt = cfg->task_cnt;
1531 mpp_assert(ctx->task_cnt && ctx->task_cnt <= MAX_FRAME_TASK_NUM);
1532
1533 if (ctx->task_cnt > MAX_FRAME_TASK_NUM)
1534 ctx->task_cnt = MAX_FRAME_TASK_NUM;
1535
1536 for (i = 0; i < cfg->task_cnt; i++) {
1537 Vepu580H265eFrmCfg *frm_cfg = mpp_calloc(Vepu580H265eFrmCfg, 1);
1538
1539 frm_cfg->regs_set[0] = mpp_calloc(H265eV580RegSet, 1);
1540 frm_cfg->regs_ret[0] = mpp_calloc(H265eV580StatusElem, 1);
1541
1542 frm_cfg->osd_cfg.reg_base = &frm_cfg->regs_set[0]->reg_osd_cfg;
1543
1544 /* setup osd cfg */
1545 frm_cfg->osd_cfg.dev = ctx->dev;
1546 frm_cfg->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
1547 frm_cfg->osd_cfg.osd_data = NULL;
1548 frm_cfg->osd_cfg.osd_data2 = NULL;
1549 mpp_dev_multi_offset_init(&frm_cfg->reg_cfg, 24);
1550 frm_cfg->osd_cfg.reg_cfg = frm_cfg->reg_cfg;
1551
1552 frm_cfg->frame_type = INTRA_FRAME;
1553
1554 ctx->frms[i] = frm_cfg;
1555 }
1556
1557 { /* setup default hardware config */
1558 MppEncHwCfg *hw = &cfg->cfg->hw;
1559 RK_U32 j;
1560
1561 hw->qp_delta_row_i = 2;
1562 hw->qp_delta_row = 2;
1563 hw->qbias_i = 171;
1564 hw->qbias_p = 85;
1565 hw->qbias_en = 0;
1566
1567 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
1568 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
1569 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
1570 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
1571
1572 for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
1573 hw->mode_bias[j] = 8;
1574
1575 hw->skip_sad = 8;
1576 hw->skip_bias = 8;
1577 }
1578
1579 ctx->tune = vepu580_h265e_tune_init(ctx);
1580
1581 {
1582 // check parall tile ability
1583 const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap();
1584
1585 ctx->tile_parall_en = cap->send_cmd > MPP_CMD_SET_SESSION_FD;
1586 }
1587
1588 ctx->poll_slice_max = 8;
1589 ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
1590 ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
1591
1592 if (NULL == ctx->poll_cfgs) {
1593 ret = MPP_ERR_MALLOC;
1594 mpp_err_f("init poll cfg buffer failed\n");
1595 goto DONE;
1596 }
1597 ctx->output_cb = cfg->output_cb;
1598 cfg->cap_recn_out = 1;
1599 DONE:
1600 if (ret)
1601 hal_h265e_v580_deinit(hal);
1602
1603 hal_h265e_leave();
1604 return ret;
1605 }
hal_h265e_vepu580_prepare(void * hal)1606 static MPP_RET hal_h265e_vepu580_prepare(void *hal)
1607 {
1608 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
1609 MppEncPrepCfg *prep = &ctx->cfg->prep;
1610
1611 hal_h265e_dbg_func("enter %p\n", hal);
1612
1613 if (prep->change_res) {
1614 RK_S32 i;
1615
1616 // pre-alloc required buffers to reduce first frame delay
1617 vepu580_h265_setup_hal_bufs(ctx);
1618 for (i = 0; i < ctx->max_buf_cnt; i++)
1619 hal_bufs_get_buf(ctx->dpb_bufs, i);
1620
1621 prep->change_res = 0;
1622 }
1623
1624 hal_h265e_dbg_func("leave %p\n", hal);
1625
1626 return MPP_OK;
1627 }
1628
1629 static MPP_RET
vepu580_h265_set_patch_info(MppDevRegOffCfgs * cfgs,H265eSyntax_new * syn,VepuFmt input_fmt,HalEncTask * task)1630 vepu580_h265_set_patch_info(MppDevRegOffCfgs *cfgs, H265eSyntax_new *syn,
1631 VepuFmt input_fmt, HalEncTask *task)
1632 {
1633 MppFrameFormat fmt = mpp_frame_get_fmt(task->frame);
1634 RK_U32 hor_stride = syn->pp.hor_stride;
1635 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
1636 RK_U32 frame_size = hor_stride * ver_stride;
1637 RK_U32 u_offset = 0, v_offset = 0;
1638 MPP_RET ret = MPP_OK;
1639
1640 if (task->rc_task->frm.use_pass1)
1641 fmt = MPP_FMT_YUV420SP;
1642
1643 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1644 u_offset = mpp_frame_get_fbc_offset(task->frame);
1645 v_offset = 0;
1646 } else {
1647 switch (input_fmt) {
1648 case VEPU5xx_FMT_YUV420P: {
1649 u_offset = frame_size;
1650 v_offset = frame_size * 5 / 4;
1651 } break;
1652 case VEPU5xx_FMT_YUV420SP:
1653 case VEPU5xx_FMT_YUV422SP: {
1654 u_offset = frame_size;
1655 v_offset = frame_size;
1656 } break;
1657 case VEPU5xx_FMT_YUV422P: {
1658 u_offset = frame_size;
1659 v_offset = frame_size * 3 / 2;
1660 } break;
1661 case VEPU5xx_FMT_YUV400:
1662 case VEPU5xx_FMT_YUYV422:
1663 case VEPU5xx_FMT_UYVY422: {
1664 u_offset = 0;
1665 v_offset = 0;
1666 } break;
1667 case VEPU5xx_FMT_YUV444SP : {
1668 u_offset = hor_stride * ver_stride;
1669 v_offset = hor_stride * ver_stride;
1670 } break;
1671 case VEPU5xx_FMT_YUV444P : {
1672 u_offset = hor_stride * ver_stride;
1673 v_offset = hor_stride * ver_stride * 2;
1674 } break;
1675 case VEPU5xx_FMT_BGR565:
1676 case VEPU5xx_FMT_BGR888:
1677 case VEPU5xx_FMT_BGRA8888: {
1678 u_offset = 0;
1679 v_offset = 0;
1680 } break;
1681 default: {
1682 hal_h265e_err("unknown color space: %d\n", input_fmt);
1683 u_offset = frame_size;
1684 v_offset = frame_size * 5 / 4;
1685 }
1686 }
1687 }
1688
1689 /* input cb addr */
1690 ret = mpp_dev_multi_offset_update(cfgs, 161, u_offset);
1691 if (ret)
1692 mpp_err_f("set input cb addr offset failed %d\n", ret);
1693
1694 /* input cr addr */
1695 ret = mpp_dev_multi_offset_update(cfgs, 162, v_offset);
1696 if (ret)
1697 mpp_err_f("set input cr addr offset failed %d\n", ret);
1698
1699 return ret;
1700 }
1701
1702 typedef struct refresh_area {
1703 RK_S32 roi_ctu_x_sta;
1704 RK_S32 roi_ctu_y_sta;
1705 RK_S32 roi_ctu_x_end;
1706 RK_S32 roi_ctu_y_end;
1707 } RefreshArea;
1708
cal_refresh_area(RK_S32 ctu_w,RK_S32 ctu_h,RK_U32 refresh_idx,MppEncRcRefreshMode refresh_mode,RK_U32 refresh_num,RefreshArea * area)1709 static MPP_RET cal_refresh_area(RK_S32 ctu_w, RK_S32 ctu_h, RK_U32 refresh_idx,
1710 MppEncRcRefreshMode refresh_mode, RK_U32 refresh_num, RefreshArea *area)
1711 {
1712 MPP_RET ret = MPP_OK;
1713 RK_U32 refresh_ctu_h = 0;
1714
1715 if (refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
1716 area->roi_ctu_x_sta = 0;
1717 area->roi_ctu_x_end = ctu_w - 1;
1718
1719 if (refresh_idx > 0) {
1720 refresh_ctu_h = refresh_num + 1;
1721 area->roi_ctu_y_sta = refresh_num * refresh_idx - 1;
1722 } else {
1723 refresh_ctu_h = refresh_num;
1724 area->roi_ctu_y_sta = 0;
1725 }
1726
1727 area->roi_ctu_y_end = area->roi_ctu_y_sta + refresh_ctu_h - 1;
1728 } else {
1729 area->roi_ctu_y_sta = 0;
1730 area->roi_ctu_y_end = ctu_h - 1;
1731
1732 if (refresh_idx > 0) {
1733 refresh_ctu_h = refresh_num + 1;
1734 area->roi_ctu_x_sta = refresh_num * refresh_idx - 1;
1735 } else {
1736 refresh_ctu_h = refresh_num;
1737 area->roi_ctu_x_sta = 0;
1738 }
1739
1740 area->roi_ctu_x_end = area->roi_ctu_x_sta + refresh_ctu_h - 1;
1741 }
1742
1743 area->roi_ctu_x_end = MPP_MIN(area->roi_ctu_x_end, ctu_w - 1);
1744 area->roi_ctu_y_end = MPP_MIN(area->roi_ctu_y_end, ctu_h - 1);
1745 area->roi_ctu_x_sta = MPP_MAX(area->roi_ctu_x_sta, 0);
1746 area->roi_ctu_y_sta = MPP_MAX(area->roi_ctu_y_sta, 0);
1747
1748 hal_h265e_dbg_detail("size in ctu : %d x %d, refresh_num %d, refresh_idx %d, area x[%d, %d], y[%d, %d]",
1749 ctu_w, ctu_h, refresh_num, refresh_idx,
1750 area->roi_ctu_x_sta, area->roi_ctu_x_end,
1751 area->roi_ctu_y_sta, area->roi_ctu_y_end);
1752
1753 return ret;
1754 }
1755
setup_intra_refresh(H265eV580HalContext * ctx,RK_U32 refresh_idx)1756 static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
1757 {
1758 Vepu580H265eFrmCfg *frm = ctx->frm;
1759 H265eV580RegSet *regs = frm->regs_set[0];
1760 RK_U32 w = ctx->cfg->prep.width;
1761 RK_U32 h = ctx->cfg->prep.height;
1762 RK_S32 ctu_w = MPP_ALIGN(w, 64) / 64;
1763 RK_S32 ctu_h = MPP_ALIGN(h, 64) / 64;
1764 RK_S32 roi_base_cfg_buf_size = ctu_w * ctu_h * 64;
1765 MppEncROICfg2 *external_roi_cfg = (MppEncROICfg2 *)frm->roi_data;
1766 RK_U8 *roi_base_cfg_hw_ptr = NULL;
1767 RK_S32 roi_base_cfg_buf_fd = 0;
1768 RefreshArea cur_area;
1769 RK_S32 j, k;
1770 MPP_RET ret = MPP_OK;
1771
1772 hal_h265e_dbg_func("enter\n");
1773
1774 if (!ctx->cfg->rc.refresh_en) {
1775 ret = MPP_ERR_VALUE;
1776 goto __RET;
1777 }
1778
1779 if (frm->roi_data) {
1780 roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(external_roi_cfg->base_cfg_buf);
1781 roi_base_cfg_buf_fd = mpp_buffer_get_fd(external_roi_cfg->base_cfg_buf);
1782 } else {
1783 if (frm->roi_base_buf_size < roi_base_cfg_buf_size) {
1784 if (NULL == ctx->roi_grp)
1785 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
1786 if (frm->roi_base_cfg_buf)
1787 mpp_buffer_put(frm->roi_base_cfg_buf);
1788 MPP_FREE(frm->roi_base_cfg_sw_buf);
1789 frm->roi_base_cfg_sw_buf = mpp_malloc(RK_U8, roi_base_cfg_buf_size);
1790 mpp_buffer_get(ctx->roi_grp, &frm->roi_base_cfg_buf, roi_base_cfg_buf_size);
1791 }
1792 roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(frm->roi_base_cfg_buf);
1793 roi_base_cfg_buf_fd = mpp_buffer_get_fd(frm->roi_base_cfg_buf);
1794 }
1795
1796 frm->roi_base_buf_size = roi_base_cfg_buf_size;
1797
1798 memset(frm->roi_base_cfg_sw_buf, 0, roi_base_cfg_buf_size);
1799
1800 if (MPP_OK != cal_refresh_area(ctu_w, ctu_h, refresh_idx, ctx->cfg->rc.refresh_mode, ctx->cfg->rc.refresh_num, &cur_area)) {
1801 ret = MPP_ERR_VALUE;
1802 mpp_err_f("setting refresh area out of range");
1803 goto __RET;
1804 }
1805
1806 RK_U8 *ptr = frm->roi_base_cfg_sw_buf;
1807 for (j = 0; j < ctu_h; j++) {
1808 for (k = 0; k < ctu_w; k++) {
1809 if (j <= cur_area.roi_ctu_y_end && j >= cur_area.roi_ctu_y_sta &&
1810 k <= cur_area.roi_ctu_x_end && k >= cur_area.roi_ctu_x_sta) {
1811
1812 memset(ptr + 22, 0x55, 20); //176~336
1813 *(ptr + 21) = 0x54; //170~175
1814 *(ptr + 42) = 0x05; //336~339
1815 }
1816 ptr += 64;
1817 }
1818 }
1819
1820 memcpy(roi_base_cfg_hw_ptr, frm->roi_base_cfg_sw_buf, roi_base_cfg_buf_size);
1821
1822 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW)
1823 regs->reg_base.reg0220_me_rnge.cme_srch_v = 1;
1824 else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL)
1825 regs->reg_base.reg0220_me_rnge.cme_srch_h = 1;
1826
1827 regs->reg_base.reg0192_enc_pic.roi_en = 1;
1828 regs->reg_base.reg0178_roi_addr = roi_base_cfg_buf_fd;
1829 mpp_buffer_sync_end(frm->roi_base_cfg_buf);
1830
1831 __RET:
1832 hal_h265e_dbg_func("leave, ret %d\n", ret);
1833 return ret;
1834 }
1835
1836
vepu580_h265_set_roi_regs(H265eV580HalContext * ctx,hevc_vepu580_base * regs)1837 static MPP_RET vepu580_h265_set_roi_regs(H265eV580HalContext *ctx, hevc_vepu580_base *regs)
1838 {
1839 Vepu580H265eFrmCfg *frm = ctx->frm;
1840
1841 /* memset register on start so do not clear registers again here */
1842 if (frm->roi_data) {
1843 /* roi setup */
1844 RK_U32 ctu_w = MPP_ALIGN(ctx->cfg->prep.width, 64) / 64;
1845 RK_U32 ctu_h = MPP_ALIGN(ctx->cfg->prep.height, 64) / 64;
1846 RK_U32 base_cfg_size = ctu_w * ctu_h * 64;
1847 RK_U32 qp_cfg_size = ctu_w * ctu_h * 256;
1848 RK_U32 amv_cfg_size = ctu_w * ctu_h * 512;
1849 RK_U32 mv_cfg_size = ctu_w * ctu_h * 4;
1850 MppEncROICfg2 *cfg = (MppEncROICfg2 *)frm->roi_data;
1851
1852 if (mpp_buffer_get_size(cfg->base_cfg_buf) >= base_cfg_size) {
1853 regs->reg0192_enc_pic.roi_en = 1;
1854 regs->reg0178_roi_addr = mpp_buffer_get_fd(cfg->base_cfg_buf);
1855 } else {
1856 mpp_err("roi base cfg buf not enough, roi is invalid");
1857 }
1858
1859 if (cfg->roi_qp_en) {
1860 if (mpp_buffer_get_size(cfg->qp_cfg_buf) >= qp_cfg_size) {
1861 regs->reg0179_roi_qp_addr = mpp_buffer_get_fd(cfg->qp_cfg_buf);
1862 regs->reg0228_roi_en.roi_qp_en = 1;
1863 } else {
1864 mpp_err("roi qp cfg buf not enough, roi is invalid");
1865 }
1866 }
1867
1868 if (cfg->roi_amv_en) {
1869 if (mpp_buffer_get_size(cfg->amv_cfg_buf) >= amv_cfg_size) {
1870 regs->reg0180_roi_amv_addr = mpp_buffer_get_fd(cfg->amv_cfg_buf);
1871 regs->reg0228_roi_en.roi_amv_en = 1;
1872 } else {
1873 mpp_err("roi amv cfg buf not enough, roi is invalid");
1874 }
1875 }
1876
1877 if (cfg->roi_mv_en) {
1878 if (mpp_buffer_get_size(cfg->mv_cfg_buf) >= mv_cfg_size) {
1879 regs->reg0181_roi_mv_addr = mpp_buffer_get_fd(cfg->mv_cfg_buf);
1880 regs->reg0228_roi_en.roi_mv_en = 1;
1881 } else {
1882 mpp_err("roi mv cfg buf not enough, roi is invalid");
1883 }
1884 }
1885 }
1886
1887 return MPP_OK;
1888 }
1889
vepu580_h265_set_rc_regs(H265eV580HalContext * ctx,H265eV580RegSet * regs,HalEncTask * task)1890 static MPP_RET vepu580_h265_set_rc_regs(H265eV580HalContext *ctx, H265eV580RegSet *regs, HalEncTask *task)
1891 {
1892 H265eSyntax_new *syn = ctx->syn;
1893 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
1894 hevc_vepu580_base *reg_base = ®s->reg_base;
1895 hevc_vepu580_rc_klut *reg_rc = ®s->reg_rc_klut;
1896 MppEncCfgSet *cfg = ctx->cfg;
1897 MppEncRcCfg *rc = &cfg->rc;
1898 MppEncHwCfg *hw = &cfg->hw;
1899 MppEncH265Cfg *h265 = &cfg->h265;
1900 RK_S32 mb_wd64, mb_h64;
1901 mb_wd64 = (syn->pp.pic_width + 63) / 64;
1902 mb_h64 = (syn->pp.pic_height + 63) / 64;
1903
1904 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd64 * mb_h64);
1905 RK_U32 ctu_target_bits;
1906 RK_S32 negative_bits_thd, positive_bits_thd;
1907
1908 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1909 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
1910 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
1911
1912 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target;
1913 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target;
1914 } else {
1915 if (ctu_target_bits_mul_16 >= 0x100000) {
1916 ctu_target_bits_mul_16 = 0x50000;
1917 }
1918 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd64) >> 4;
1919 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
1920 positive_bits_thd = 5 * ctu_target_bits / 16;
1921
1922 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
1923 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
1924 reg_base->reg212_rc_cfg.rc_en = 1;
1925 reg_base->reg212_rc_cfg.aq_en = 1;
1926 reg_base->reg212_rc_cfg.aq_mode = 1;
1927 reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd64;
1928 reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1929 hw->qp_delta_row_i : hw->qp_delta_row;
1930 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max;
1931 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min;
1932 reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
1933
1934 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
1935 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
1936 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
1937 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
1938 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
1939 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
1940 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
1941 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
1942 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
1943
1944 reg_rc->rc_adj0.qp_adj0 = -2;
1945 reg_rc->rc_adj0.qp_adj1 = -1;
1946 reg_rc->rc_adj0.qp_adj2 = 0;
1947 reg_rc->rc_adj0.qp_adj3 = 1;
1948 reg_rc->rc_adj0.qp_adj4 = 2;
1949 reg_rc->rc_adj1.qp_adj5 = 0;
1950 reg_rc->rc_adj1.qp_adj6 = 0;
1951 reg_rc->rc_adj1.qp_adj7 = 0;
1952 reg_rc->rc_adj1.qp_adj8 = 0;
1953
1954 if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
1955 reg_base->reg213_rc_qp.rc_qp_range = 0;
1956 }
1957 }
1958
1959 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1960 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1961 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1962 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1963 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
1964 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1965 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
1966 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1967 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
1968 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1969 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
1970 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1971 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
1972 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1973 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
1974 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1975 reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode;
1976
1977 return MPP_OK;
1978 }
1979
vepu580_h265_set_pp_regs(H265eV580RegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg,HalEncTask * task)1980 static MPP_RET vepu580_h265_set_pp_regs(H265eV580RegSet *regs, VepuFmtCfg *fmt,
1981 MppEncPrepCfg *prep_cfg, HalEncTask *task)
1982 {
1983 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
1984 hevc_vepu580_base *reg_base = ®s->reg_base;
1985 RK_S32 stridey = 0;
1986 RK_S32 stridec = 0;
1987
1988 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
1989 reg_base->reg0198_src_fmt.src_cfmt = fmt->format;
1990 reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap;
1991 reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap;
1992 reg_base->reg0198_src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1;
1993 reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0;
1994 reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation;
1995
1996 if (MPP_FRAME_FMT_IS_YUV(prep_cfg->format))
1997 reg_base->reg0198_src_fmt.src_range = 1;
1998 else
1999 reg_base->reg0198_src_fmt.src_range = (prep_cfg->range == MPP_FRAME_RANGE_JPEG) ? 1 : 0;
2000
2001 if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
2002 stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
2003 if (!stridey)
2004 stridey = MPP_ALIGN(prep_cfg->width, 16);
2005 } else if (prep_cfg->hor_stride) {
2006 stridey = prep_cfg->hor_stride;
2007 } else {
2008 if (fmt->format == VEPU5xx_FMT_BGRA8888 )
2009 stridey = prep_cfg->width * 4;
2010 else if (fmt->format == VEPU5xx_FMT_BGR888 )
2011 stridey = prep_cfg->width * 3;
2012 else if (fmt->format == VEPU5xx_FMT_BGR565 ||
2013 fmt->format == VEPU5xx_FMT_YUYV422 ||
2014 fmt->format == VEPU5xx_FMT_UYVY422)
2015 stridey = prep_cfg->width * 2;
2016 else
2017 stridey = prep_cfg->width;
2018 }
2019
2020 switch (fmt->format) {
2021 case VEPU5xx_FMT_YUV444SP : {
2022 stridec = stridey * 2;
2023 } break;
2024 case VEPU5xx_FMT_YUV422SP :
2025 case VEPU5xx_FMT_YUV420SP :
2026 case VEPU5xx_FMT_YUV444P : {
2027 stridec = stridey;
2028 } break;
2029 default : {
2030 stridec = stridey / 2;
2031 } break;
2032 }
2033
2034 if (reg_base->reg0198_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
2035 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
2036
2037 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
2038
2039 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
2040 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
2041 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
2042
2043 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
2044 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
2045 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
2046
2047 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
2048 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
2049 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
2050
2051 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
2052 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
2053 reg_base->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
2054
2055 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
2056 }
2057
2058 reg_base->reg0205_src_strd0.src_strd0 = stridey;
2059 reg_base->reg0206_src_strd1.src_strd1 = stridec;
2060
2061 return MPP_OK;
2062 }
2063
vepu580_h265_set_slice_regs(H265eSyntax_new * syn,hevc_vepu580_base * regs)2064 static void vepu580_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)
2065 {
2066 regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->m_bUseSAO;
2067 regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
2068 regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
2069 regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
2070 regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
2071 regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
2072 regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
2073
2074 regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
2075 regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
2076 regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
2077 regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
2078 regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
2079 regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
2080 regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
2081 regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
2082 regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
2083 regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
2084 regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
2085 regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
2086 regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
2087 regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
2088
2089 regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
2090 regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
2091 regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag;
2092 regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag;
2093 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
2094
2095 regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
2096 regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
2097
2098 regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
2099
2100 regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
2101 regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
2102 regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
2103 regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num;
2104
2105 regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
2106 regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type;
2107 regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
2108 regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
2109 regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
2110 regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
2111
2112
2113 regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;
2114 regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
2115 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
2116 regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
2117 regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
2118 regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
2119 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
2120 regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
2121
2122 regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
2123 regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
2124 regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
2125 regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
2126
2127 }
2128
vepu580_h265_set_ref_regs(H265eSyntax_new * syn,hevc_vepu580_base * regs)2129 static void vepu580_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu580_base *regs)
2130 {
2131 regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
2132 regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
2133 regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
2134
2135 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
2136 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
2137 regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
2138 regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
2139 regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
2140 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
2141 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
2142 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
2143 regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
2144 regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
2145
2146 regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
2147 regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
2148 regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
2149 regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
2150 regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
2151
2152 regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
2153 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
2154 regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
2155 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
2156 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
2157 regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
2158 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
2159
2160 return;
2161 }
2162
hal_h265e_v580_send_regs(MppDev dev,H265eV580RegSet * hw_regs,H265eV580StatusElem * reg_out)2163 static MPP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *reg_out)
2164 {
2165 RK_U32 *regs = (RK_U32*)hw_regs;
2166 MppDevRegWrCfg cfg;
2167 MppDevRegRdCfg cfg1;
2168 MPP_RET ret = MPP_OK;
2169 RK_U32 i;
2170
2171 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
2172 cfg.size = sizeof(hevc_vepu580_control_cfg);
2173 cfg.offset = VEPU580_CTL_OFFSET;
2174
2175 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2176 if (ret) {
2177 mpp_err_f("set register write failed %d\n", ret);
2178 goto FAILE;
2179 }
2180
2181 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
2182 regs = (RK_U32*)&hw_regs->reg_ctl;
2183 for (i = 0; i < sizeof(hevc_vepu580_control_cfg) / 4; i++) {
2184 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
2185 }
2186 }
2187
2188 cfg.reg = &hw_regs->reg_base;
2189 cfg.size = sizeof(hevc_vepu580_base);
2190 cfg.offset = VEPU580_BASE_OFFSET;
2191
2192 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2193 if (ret) {
2194 mpp_err_f("set register write failed %d\n", ret);
2195 goto FAILE;
2196 }
2197
2198 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
2199 regs = (RK_U32*)(&hw_regs->reg_base);
2200 for (i = 0; i < 32; i++) {
2201 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
2202 }
2203 regs += 32;
2204 for (i = 0; i < (sizeof(hevc_vepu580_base) - 128) / 4; i++) {
2205 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2206 }
2207 }
2208
2209 cfg.reg = &hw_regs->reg_rc_klut;
2210 cfg.size = sizeof(hevc_vepu580_rc_klut);
2211 cfg.offset = VEPU580_RCKULT_OFFSET;
2212
2213 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2214
2215 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
2216 regs = (RK_U32*)&hw_regs->reg_rc_klut;
2217 for (i = 0; i < sizeof(hevc_vepu580_rc_klut) / 4; i++) {
2218 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2219 }
2220 }
2221
2222 if (ret) {
2223 mpp_err_f("set rc kult write failed %d\n", ret);
2224 goto FAILE;
2225 }
2226
2227 cfg.reg = &hw_regs->reg_wgt;
2228 cfg.size = sizeof(hevc_vepu580_wgt);
2229 cfg.offset = VEPU580_WEG_OFFSET;
2230
2231 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2232 if (ret) {
2233 mpp_err_f("set register write failed %d\n", ret);
2234 goto FAILE;
2235 }
2236
2237 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2238 regs = (RK_U32*)&hw_regs->reg_wgt;
2239 for (i = 0; i < sizeof(hevc_vepu580_wgt) / 4; i++) {
2240 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2241 }
2242 }
2243
2244 cfg.reg = &hw_regs->reg_rdo;
2245 cfg.size = sizeof(vepu580_rdo_cfg);
2246 cfg.offset = VEPU580_RDOCFG_OFFSET;
2247
2248 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2249 if (ret) {
2250 mpp_err_f("set register write failed %d\n", ret);
2251 goto FAILE;
2252 }
2253
2254 cfg.reg = &hw_regs->reg_osd_cfg;
2255 cfg.size = sizeof(vepu580_osd_cfg);
2256 cfg.offset = VEPU580_OSD_OFFSET;
2257
2258 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &cfg);
2259 if (ret) {
2260 mpp_err_f("set register write failed %d\n", ret);
2261 goto FAILE;
2262 }
2263
2264 cfg1.reg = ®_out->hw_status;
2265 cfg1.size = sizeof(RK_U32);
2266 cfg1.offset = VEPU580_REG_BASE_HW_STATUS;
2267
2268 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1);
2269 if (ret) {
2270 mpp_err_f("set register read failed %d\n", ret);
2271 goto FAILE;
2272 }
2273
2274 cfg1.reg = ®_out->st;
2275 cfg1.size = sizeof(H265eV580StatusElem) - 4;
2276 cfg1.offset = VEPU580_STATUS_OFFSET;
2277
2278 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1);
2279 if (ret) {
2280 mpp_err_f("set register read failed %d\n", ret);
2281 goto FAILE;
2282 }
2283 FAILE:
2284 return ret;
2285 }
2286
setup_vepu580_dual_core(H265eV580HalContext * ctx)2287 static MPP_RET setup_vepu580_dual_core(H265eV580HalContext *ctx)
2288 {
2289 Vepu580H265eFrmCfg *frm = ctx->frm;
2290 H265eV580RegSet *regs = frm->regs_set[0];
2291 hevc_vepu580_base *reg_base = ®s->reg_base;
2292 RK_U32 dchs_ofst = 9;
2293 RK_U32 dchs_rxe = 1;
2294
2295 if (frm->frame_type == INTRA_FRAME) {
2296 ctx->curr_idx = 0;
2297 ctx->prev_idx = 0;
2298 dchs_rxe = 0;
2299 }
2300
2301 reg_base->reg0193_dual_core.dchs_txid = ctx->curr_idx;
2302 reg_base->reg0193_dual_core.dchs_rxid = ctx->prev_idx;
2303 reg_base->reg0193_dual_core.dchs_txe = 1;
2304 reg_base->reg0193_dual_core.dchs_rxe = dchs_rxe;
2305 reg_base->reg0193_dual_core.dchs_ofst = dchs_ofst;
2306
2307 ctx->prev_idx = ctx->curr_idx++;
2308 if (ctx->curr_idx > 3)
2309 ctx->curr_idx = 0;
2310
2311 return MPP_OK;
2312 }
2313
vepu580_h265_set_me_regs(H265eV580HalContext * ctx,H265eSyntax_new * syn,hevc_vepu580_base * regs)2314 static void vepu580_h265_set_me_regs(H265eV580HalContext *ctx, H265eSyntax_new *syn, hevc_vepu580_base *regs)
2315 {
2316
2317 RK_U32 cime_w = 11, cime_h = 7;
2318 RK_S32 merangx = (cime_w + 1) * 32;
2319 RK_S32 merangy = (cime_h + 1) * 32;
2320 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
2321
2322 if (merangx > 384) {
2323 merangx = 384;
2324 }
2325 if (merangy > 320) {
2326 merangy = 320;
2327 }
2328
2329 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) {
2330 if (merangx > syn->pp.pic_width ) {
2331 merangx = syn->pp.pic_width;
2332 }
2333 merangx = merangx / 4 * 2;
2334 }
2335
2336 if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) {
2337 if (merangy > syn->pp.pic_height) {
2338 merangy = syn->pp.pic_height;
2339 }
2340 merangy = merangy / 4 * 2;
2341 }
2342
2343 {
2344 RK_S32 merange_x = merangx / 2;
2345 RK_S32 merange_y = merangy / 2;
2346 RK_S32 mxneg = ((-(merange_x << 2)) >> 2) / 4;
2347 RK_S32 myneg = ((-(merange_y << 2)) >> 2) / 4;
2348 RK_S32 mxpos = (((merange_x << 2) - 4) >> 2) / 4;
2349 RK_S32 mypos = (((merange_y << 2) - 4) >> 2) / 4;
2350
2351 mxneg = MPP_MIN(abs(mxneg), mxpos) * 4;
2352 myneg = MPP_MIN(abs(myneg), mypos) * 4;
2353
2354 merangx = mxneg * 2;
2355 merangy = myneg * 2;
2356 }
2357 regs->reg0220_me_rnge.cme_srch_h = merangx / 32;
2358 regs->reg0220_me_rnge.cme_srch_v = merangy / 32;
2359
2360 regs->reg0220_me_rnge.rme_srch_h = 7;
2361 regs->reg0220_me_rnge.rme_srch_v = 5;
2362 regs->reg0220_me_rnge.dlt_frm_num = 0x1;
2363
2364 regs->reg0221_me_cfg.pmv_mdst_h = 5;
2365 regs->reg0221_me_cfg.pmv_mdst_v = 5;
2366 regs->reg0221_me_cfg.mv_limit = 0;
2367 regs->reg0221_me_cfg.pmv_num = 2;
2368
2369 //regs->reg0221_me_cfg.rme_dis = 0;
2370 // regs->reg0221_me_cfg.rme_dis = 2;
2371
2372
2373
2374 if (syn->pp.sps_temporal_mvp_enabled_flag &&
2375 (ctx->frame_type != INTRA_FRAME)) {
2376 if (ctx->last_frame_type == INTRA_FRAME) {
2377 regs->reg0221_me_cfg.colmv_load = 0;
2378 } else {
2379 regs->reg0221_me_cfg.colmv_load = 1;
2380 }
2381 regs->reg0221_me_cfg.colmv_stor = 1;
2382 }
2383
2384 if (syn->pp.pic_width > 2688) {
2385 regs->reg0222_me_cach.cme_rama_h = 12;
2386 } else if (syn->pp.pic_width > 2048) {
2387 regs->reg0222_me_cach.cme_rama_h = 16;
2388 } else {
2389 regs->reg0222_me_cach.cme_rama_h = 20;
2390 }
2391
2392 {
2393 RK_S32 swin_scope_wd16 = (regs->reg0220_me_rnge.cme_srch_h + 3 + 1) / 4 * 2 + 1;
2394 RK_S32 tmpMin = (regs->reg0220_me_rnge.cme_srch_v + 3) / 4 * 2 + 1;
2395 if (regs->reg0222_me_cach.cme_rama_h / 4 < tmpMin) {
2396 tmpMin = regs->reg0222_me_cach.cme_rama_h / 4;
2397 }
2398 regs->reg0222_me_cach.cme_rama_max =
2399 (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
2400 }
2401 regs->reg0222_me_cach.cach_l2_tag = 0x0;
2402
2403 pic_wd64 = pic_wd64 << 6;
2404
2405 if (pic_wd64 <= 512)
2406 regs->reg0222_me_cach.cach_l2_tag = 0x0;
2407 else if (pic_wd64 <= 1024)
2408 regs->reg0222_me_cach.cach_l2_tag = 0x1;
2409 else if (pic_wd64 <= 2048)
2410 regs->reg0222_me_cach.cach_l2_tag = 0x2;
2411 else if (pic_wd64 <= 4096)
2412 regs->reg0222_me_cach.cach_l2_tag = 0x3;
2413
2414 }
2415
vepu580_h265_get_md_info_buf(H265eV580HalContext * ctx)2416 static MppBuffer vepu580_h265_get_md_info_buf(H265eV580HalContext *ctx)
2417 {
2418 RK_S32 w = ctx->cfg->prep.width;
2419 RK_S32 h = ctx->cfg->prep.height;
2420 RK_S32 buf_size = (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 64) >> 6) * 32;
2421
2422 /* prepare md info internal buffer when deblur is enabled */
2423 if (ctx->cfg->tune.deblur_en && (buf_size > ctx->md_info_buf_size)) {
2424 if (ctx->md_info_buf) {
2425 mpp_buffer_put(ctx->md_info_buf);
2426 ctx->md_info_buf = NULL;
2427 }
2428
2429 if (!ctx->qpmap_grp)
2430 mpp_buffer_group_get_internal(&ctx->qpmap_grp, MPP_BUFFER_TYPE_ION);
2431
2432 mpp_buffer_get(ctx->qpmap_grp, &ctx->md_info_buf, buf_size);
2433 if (!ctx->md_info_buf)
2434 mpp_err_f("failed to get md info buffer\n");
2435 else {
2436 hal_h265e_dbg_flow("get md info internal buffer %p size %d %d\n",
2437 ctx->md_info_buf, buf_size, ctx->md_info_buf_size);
2438 ctx->md_info_buf_size = buf_size;
2439 }
2440 }
2441
2442 return ctx->md_info_buf;
2443 }
2444
vepu580_h265_set_hw_address(H265eV580HalContext * ctx,HalEncTask * task)2445 void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, HalEncTask *task)
2446 {
2447 Vepu580H265eFrmCfg *frm = ctx->frm;
2448 hevc_vepu580_base *regs = &frm->regs_set[0]->reg_base;
2449 HalEncTask *enc_task = task;
2450 HalBuf *recon_buf, *ref_buf;
2451 H265eSyntax_new *syn = ctx->syn;
2452
2453 hal_h265e_enter();
2454
2455 regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input);
2456 regs->reg0161_adr_src1 = regs->reg0160_adr_src0;
2457 regs->reg0162_adr_src2 = regs->reg0160_adr_src0;
2458
2459 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx);
2460 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx);
2461
2462 if (!syn->sp.non_reference_flag) {
2463 regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
2464 regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr;
2465
2466 mpp_dev_multi_offset_update(frm->reg_cfg, 164, ctx->fbc_header_len);
2467 }
2468 regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
2469 regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr;
2470 regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
2471 regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
2472 regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
2473 regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
2474
2475 mpp_dev_multi_offset_update(frm->reg_cfg, 166, ctx->fbc_header_len);
2476
2477 if (syn->pp.tiles_enabled_flag) {
2478 RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
2479 RK_U32 i = 0;
2480 RK_U32 max_tile_buf_size = MPP_ALIGN(((MPP_ALIGN(syn->pp.pic_height, 64) + 64) << 5), 256);
2481
2482 if (NULL == ctx->tile_grp)
2483 mpp_buffer_group_get_internal(&ctx->tile_grp, MPP_BUFFER_TYPE_ION);
2484
2485 mpp_assert(ctx->tile_grp);
2486
2487 for (i = 0; i < MAX_TILE_NUM; i++) {
2488 if (NULL == frm->hw_tile_buf[i]) {
2489 mpp_buffer_get(ctx->tile_grp, &frm->hw_tile_buf[i], max_tile_buf_size);
2490 }
2491 }
2492
2493 if (NULL == frm->hw_tile_stream[0]) {
2494 mpp_buffer_get(ctx->tile_grp, &frm->hw_tile_stream[0], ctx->frame_size / tile_num);
2495 }
2496
2497 if (tile_num > 2) {
2498 if (NULL == frm->hw_tile_stream[1]) {
2499 mpp_buffer_get(ctx->tile_grp, &frm->hw_tile_stream[1], ctx->frame_size / tile_num);
2500 }
2501 if (NULL == frm->hw_tile_stream[2]) {
2502 mpp_buffer_get(ctx->tile_grp, &frm->hw_tile_stream[2], ctx->frame_size / tile_num);
2503 }
2504 }
2505
2506 regs->reg0176_lpfw_addr = mpp_buffer_get_fd(frm->hw_tile_buf[0]);
2507 regs->reg0177_lpfr_addr = mpp_buffer_get_fd(frm->hw_tile_buf[1]);
2508 }
2509
2510 {
2511 if (!enc_task->md_info)
2512 enc_task->md_info = vepu580_h265_get_md_info_buf(ctx);
2513
2514 if (enc_task->md_info) {
2515 regs->reg0192_enc_pic.mei_stor = 1;
2516 regs->reg0171_meiw_addr = mpp_buffer_get_fd(enc_task->md_info);
2517 } else {
2518 regs->reg0192_enc_pic.mei_stor = 0;
2519 regs->reg0171_meiw_addr = 0;
2520 }
2521 }
2522
2523 regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
2524 /* TODO: stream size relative with syntax */
2525 regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr;
2526 regs->reg0174_bsbr_addr = regs->reg0172_bsbt_addr;
2527 regs->reg0175_adr_bsbs = regs->reg0172_bsbt_addr;
2528
2529 mpp_dev_multi_offset_update(frm->reg_cfg, 175, mpp_packet_get_length(task->packet));
2530 mpp_dev_multi_offset_update(frm->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
2531
2532 regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
2533 regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
2534 }
2535
vepu580_h265e_save_pass1_patch(H265eV580RegSet * regs,H265eV580HalContext * ctx,RK_S32 tiles_enabled_flag)2536 static MPP_RET vepu580_h265e_save_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx,
2537 RK_S32 tiles_enabled_flag)
2538 {
2539 Vepu580H265eFrmCfg *frm = ctx->frm;
2540 hevc_vepu580_base *reg_base = ®s->reg_base;
2541 RK_S32 width = ctx->cfg->prep.width;
2542 RK_S32 height = ctx->cfg->prep.height;
2543 RK_S32 width_align = MPP_ALIGN(width, 64);
2544 RK_S32 height_align = MPP_ALIGN(height, 16);
2545
2546 if (NULL == ctx->buf_pass1) {
2547 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
2548 if (!ctx->buf_pass1) {
2549 mpp_err("buf_pass1 malloc fail, debreath invaild");
2550 return MPP_NOK;
2551 }
2552 }
2553
2554 reg_base->reg0192_enc_pic.cur_frm_ref = 1;
2555 reg_base->reg0163_rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
2556 reg_base->reg0164_rfpw_b_addr = reg_base->reg0163_rfpw_h_addr;
2557 reg_base->reg0192_enc_pic.rec_fbc_dis = 1;
2558
2559 if (tiles_enabled_flag)
2560 reg_base->reg0238_synt_pps.lpf_fltr_acrs_til = 0;
2561
2562 mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height_align);
2563
2564 /* NOTE: disable split to avoid lowdelay slice output */
2565 regs->reg_base.reg0216_sli_splt.sli_splt = 0;
2566 regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
2567
2568 return MPP_OK;
2569 }
2570
vepu580_h265e_use_pass1_patch(H265eV580RegSet * regs,H265eV580HalContext * ctx)2571 static MPP_RET vepu580_h265e_use_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx)
2572 {
2573 Vepu580H265eFrmCfg *frm = ctx->frm;
2574 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
2575 hevc_vepu580_base *reg_base = ®s->reg_base;
2576 RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 64);
2577 RK_U32 ver_stride = MPP_ALIGN(ctx->cfg->prep.height, 16);
2578 RK_U32 frame_size = hor_stride * ver_stride;
2579 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2580 MPP_RET ret = MPP_OK;
2581
2582 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
2583 reg_base->reg0198_src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP;
2584 reg_base->reg0198_src_fmt.alpha_swap = 0;
2585 reg_base->reg0198_src_fmt.rbuv_swap = 0;
2586 reg_base->reg0198_src_fmt.out_fmt = 1;
2587 reg_base->reg0203_src_proc.afbcd_en = 0;
2588 reg_base->reg0205_src_strd0.src_strd0 = hor_stride;
2589 reg_base->reg0206_src_strd1.src_strd1 = hor_stride;
2590 reg_base->reg0203_src_proc.src_mirr = 0;
2591 reg_base->reg0203_src_proc.src_rot = 0;
2592 reg_base->reg0204_pic_ofst.pic_ofst_x = 0;
2593 reg_base->reg0204_pic_ofst.pic_ofst_y = 0;
2594 reg_base->reg0160_adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
2595 reg_base->reg0161_adr_src1 = reg_base->reg0160_adr_src0;
2596 reg_base->reg0162_adr_src2 = reg_base->reg0160_adr_src0;
2597
2598 /* input cb addr */
2599 ret = mpp_dev_multi_offset_update(frm->reg_cfg, 161, frame_size);
2600 if (ret)
2601 mpp_err_f("set input cb addr offset failed %d\n", ret);
2602
2603 /* input cr addr */
2604 ret = mpp_dev_multi_offset_update(frm->reg_cfg, 162, frame_size);
2605 if (ret)
2606 mpp_err_f("set input cr addr offset failed %d\n", ret);
2607
2608 return MPP_OK;
2609 }
2610
vepu580_setup_split(H265eV580RegSet * regs,MppEncCfgSet * enc_cfg,RK_U32 title_en)2611 static void vepu580_setup_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
2612 {
2613 MppEncSliceSplit *cfg = &enc_cfg->split;
2614
2615 hal_h265e_dbg_func("enter\n");
2616
2617 switch (cfg->split_mode) {
2618 case MPP_ENC_SPLIT_NONE : {
2619 regs->reg_base.reg0216_sli_splt.sli_splt = 0;
2620 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
2621 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2622 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0;
2623 regs->reg_base.reg0216_sli_splt.sli_flsh = 0;
2624 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
2625
2626 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
2627 regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
2628 } break;
2629 case MPP_ENC_SPLIT_BY_BYTE : {
2630 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
2631 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
2632 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2633 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
2634 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
2635 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
2636
2637 regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;
2638 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
2639 regs->reg_ctl.reg0008_int_en.slc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;
2640 } break;
2641 case MPP_ENC_SPLIT_BY_CTU : {
2642 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;
2643 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64;
2644 RK_U32 slice_num = 0;
2645
2646 if (title_en)
2647 mb_w = mb_w / 2;
2648
2649 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
2650
2651 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
2652 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1;
2653 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
2654 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
2655 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
2656 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
2657
2658 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
2659 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
2660
2661 if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
2662 (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN)))
2663 regs->reg_ctl.reg0008_int_en.slc_done_en = 1 ;
2664 } break;
2665 default : {
2666 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
2667 } break;
2668 }
2669
2670 hal_h265e_dbg_func("leave\n");
2671 }
2672
hal_h265e_v580_gen_regs(void * hal,HalEncTask * task)2673 MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
2674 {
2675 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
2676 HalEncTask *enc_task = task;
2677 EncRcTask *rc_task = enc_task->rc_task;
2678 EncFrmStatus *frm = &rc_task->frm;
2679 H265eSyntax_new *syn = ctx->syn;
2680 Vepu580H265eFrmCfg *frm_cfg = ctx->frm;
2681 H265eV580RegSet *regs = frm_cfg->regs_set[0];
2682 RK_U32 pic_width_align8, pic_height_align8;
2683 RK_S32 pic_wd64, pic_h64;
2684 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2685 hevc_vepu580_control_cfg *reg_ctl = ®s->reg_ctl;
2686 hevc_vepu580_base *reg_base = ®s->reg_base;
2687 hevc_vepu580_rc_klut *reg_klut = ®s->reg_rc_klut;
2688 MppEncCfgSet *cfg = ctx->cfg;
2689
2690 hal_h265e_enter();
2691 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
2692 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
2693 pic_wd64 = (syn->pp.pic_width + 63) / 64;
2694 pic_h64 = (syn->pp.pic_height + 63) / 64;
2695
2696 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
2697 frm_cfg->frame_count, ctx->frame_type);
2698
2699 memset(regs, 0, sizeof(H265eV580RegSet));
2700
2701 if (ctx->task_cnt > 1)
2702 setup_vepu580_dual_core(ctx);
2703
2704 reg_ctl->reg0004_enc_strt.lkt_num = 0;
2705 reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode;
2706 reg_ctl->reg0005_enc_clr.safe_clr = 0x0;
2707 reg_ctl->reg0005_enc_clr.force_clr = 0x0;
2708
2709 reg_ctl->reg0008_int_en.enc_done_en = 1;
2710 reg_ctl->reg0008_int_en.lkt_node_done_en = 1;
2711 reg_ctl->reg0008_int_en.sclr_done_en = 1;
2712 reg_ctl->reg0008_int_en.slc_done_en = 0;
2713 reg_ctl->reg0008_int_en.bsf_oflw_en = 1;
2714 reg_ctl->reg0008_int_en.brsp_otsd_en = 1;
2715 reg_ctl->reg0008_int_en.wbus_err_en = 1;
2716 reg_ctl->reg0008_int_en.rbus_err_en = 1;
2717 reg_ctl->reg0008_int_en.wdg_en = 1;
2718 reg_ctl->reg0008_int_en.lkt_err_int_en = 0;
2719
2720 reg_ctl->reg0012_dtrns_map.lpfw_bus_ordr = 0x0;
2721 reg_ctl->reg0012_dtrns_map.cmvw_bus_ordr = 0x0;
2722 reg_ctl->reg0012_dtrns_map.dspw_bus_ordr = 0x0;
2723 reg_ctl->reg0012_dtrns_map.rfpw_bus_ordr = 0x0;
2724 reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0;
2725 reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0;
2726 reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7;
2727 reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0;
2728 reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0;
2729 reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0;
2730 reg_ctl->reg0012_dtrns_map.afbc_bsize = 0x1;
2731 reg_ctl->reg0012_dtrns_map.ebufw_bus_ordr = 0x0;
2732
2733 reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
2734 reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
2735 reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
2736 reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
2737
2738 reg_ctl->reg0021_func_en.cke = 1;
2739 reg_ctl->reg0021_func_en.resetn_hw_en = 1;
2740 reg_ctl->reg0021_func_en.enc_done_tmvp_en = 1;
2741
2742 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
2743 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
2744 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
2745 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
2746 reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
2747 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
2748
2749 reg_base->reg0192_enc_pic.enc_stnd = 1; //H265
2750 reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
2751 reg_base->reg0192_enc_pic.bs_scp = 1;
2752 reg_base->reg0192_enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64));
2753
2754 reg_base->reg0203_src_proc.src_mirr = 0;
2755 reg_base->reg0203_src_proc.src_rot = 0;
2756 reg_base->reg0203_src_proc.txa_en = 1;
2757 reg_base->reg0203_src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;
2758
2759 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3;
2760 memcpy(®_klut->klut_wgt0, &klut_weight[0], sizeof(klut_weight));
2761
2762 vepu580_h265_set_me_regs(ctx, syn, reg_base);
2763
2764 reg_base->reg0232_rdo_cfg.chrm_spcl = 1;
2765 reg_base->reg0232_rdo_cfg.cu_inter_e = 0x06db;
2766 reg_base->reg0232_rdo_cfg.cu_intra_e = 0xf;
2767
2768 if (syn->pp.num_long_term_ref_pics_sps) {
2769 reg_base->reg0232_rdo_cfg.ltm_col = 0;
2770 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1;
2771 } else {
2772 reg_base->reg0232_rdo_cfg.ltm_col = 0;
2773 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0;
2774 }
2775
2776 reg_base->reg0232_rdo_cfg.ccwa_e = 1;
2777 reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
2778 reg_base->reg0236_synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);
2779
2780 vepu580_h265_set_hw_address(ctx, task);
2781 vepu580_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
2782 vepu580_h265_set_rc_regs(ctx, regs, task);
2783 vepu580_h265_set_slice_regs(syn, reg_base);
2784 vepu580_h265_set_ref_regs(syn, reg_base);
2785
2786 vepu580_set_osd(&ctx->frm->osd_cfg);
2787 /* ROI configure */
2788 vepu580_h265_set_roi_regs(ctx, reg_base);
2789 if (frm->is_i_refresh)
2790 setup_intra_refresh(ctx, frm->seq_idx % ctx->cfg->rc.gop);
2791
2792 if (cfg->tune.deblur_en && (!rc_task->info.complex_scene) &&
2793 cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC && task->md_info &&
2794 cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
2795 if (MPP_OK != vepu580_setup_qpmap_buf(ctx))
2796 mpp_err("qpmap malloc buffer failed!\n");
2797 }
2798
2799 /*paramet cfg*/
2800 vepu580_h265_global_cfg_set(ctx, regs);
2801
2802 vepu580_h265e_tune_reg_patch(ctx->tune);
2803
2804 vepu580_setup_split(regs, cfg, syn->pp.tiles_enabled_flag);
2805
2806 hal_h265e_leave();
2807 return MPP_OK;
2808 }
2809
hal_h265e_v580_set_uniform_tile(hevc_vepu580_base * regs,H265eSyntax_new * syn,RK_U32 index,RK_S32 tile_start_x)2810 void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *syn,
2811 RK_U32 index, RK_S32 tile_start_x)
2812 {
2813 if (syn->pp.tiles_enabled_flag) {
2814 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
2815 RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1;
2816
2817 if (!regs->reg0192_enc_pic.cur_frm_ref &&
2818 !(regs->reg0238_synt_pps.lpf_fltr_acrs_til &&
2819 regs->reg0238_synt_pps.lp_fltr_acrs_sli &&
2820 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli &&
2821 regs->reg0237_synt_sps.smpl_adpt_ofst_e &&
2822 (regs->reg0239_synt_sli0.sli_sao_luma_flg ||
2823 (regs->reg0239_synt_sli0.sli_sao_chrm_flg && regs->reg0198_src_fmt.out_fmt)))) {
2824 regs->reg0193_dual_core.dchs_txe = 0;
2825 regs->reg0193_dual_core.dchs_rxe = 0;
2826 } else if (index > 0) {
2827 regs->reg0193_dual_core.dchs_txid = index;
2828 regs->reg0193_dual_core.dchs_rxid = index - 1;
2829 regs->reg0193_dual_core.dchs_txe = 1;
2830 regs->reg0193_dual_core.dchs_rxe = 1;
2831 } else {
2832 regs->reg0193_dual_core.dchs_txid = index;
2833 regs->reg0193_dual_core.dchs_rxid = 0;
2834 regs->reg0193_dual_core.dchs_txe = 1;
2835 regs->reg0193_dual_core.dchs_rxe = 0;
2836 }
2837 /* dual core runtime offset should set to 2 to avoid data access conflict */
2838 regs->reg0193_dual_core.dchs_ofst = 2;
2839
2840 if (index == syn->pp.num_tile_columns_minus1) {
2841 regs->reg0193_dual_core.dchs_txid = 0;
2842 regs->reg0193_dual_core.dchs_txe = 0;
2843 }
2844 regs->reg0252_tile_cfg.tile_w_m1 = tile_width - 1;
2845 regs->reg0252_tile_cfg.tile_h_m1 = mb_h - 1;
2846 regs->reg212_rc_cfg.rc_ctu_num = tile_width;
2847 regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
2848 regs->reg0253_tile_pos.tile_x = tile_start_x;
2849 regs->reg0253_tile_pos.tile_y = 0;
2850
2851 hal_h265e_dbg_detail("tile_x %d, rc_ctu_num %d, tile_width_m1 %d",
2852 regs->reg0253_tile_pos.tile_x, regs->reg212_rc_cfg.rc_ctu_num,
2853 regs->reg0252_tile_cfg.tile_w_m1);
2854 }
2855 }
2856
hal_h265e_v580_start(void * hal,HalEncTask * enc_task)2857 MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
2858 {
2859 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
2860 H265eSyntax_new *syn = ctx->syn;
2861 RK_U32 tile_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
2862 RK_U32 stream_len = 0;
2863 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2864 Vepu580H265eFrmCfg *frm = ctx->frm;
2865 RK_U32 k = 0;
2866 MPP_RET ret = MPP_OK;
2867 RK_S32 tile_start_x = 0;
2868
2869 hal_h265e_enter();
2870
2871 ctx->tile_num = tile_num;
2872
2873 if (enc_task->flags.err) {
2874 hal_h265e_err("enc_task->flags.err %08x, return e arly",
2875 enc_task->flags.err);
2876 return MPP_NOK;
2877 }
2878
2879 if (tile_num > MAX_TILE_NUM) {
2880 mpp_log("tile_num big then support %d, max %d", tile_num, MAX_TILE_NUM);
2881 return MPP_NOK;
2882 }
2883
2884 for (k = 0; k < tile_num; k++) {
2885 H265eV580RegSet *hw_regs = frm->regs_set[k];
2886 hevc_vepu580_base *reg_base = NULL;
2887 H265eV580StatusElem *reg_out = frm->regs_ret[k];
2888
2889 if (!hw_regs) {
2890 hw_regs = mpp_malloc(H265eV580RegSet, 1);
2891 frm->regs_set[k] = hw_regs;
2892 }
2893 if (!reg_out) {
2894 reg_out = mpp_malloc(H265eV580StatusElem, 1);
2895 frm->regs_ret[k] = reg_out;
2896 }
2897
2898 reg_base = &hw_regs->reg_base;
2899
2900 if (k)
2901 memcpy(hw_regs, frm->regs_set[0], sizeof(*hw_regs));
2902
2903 vepu580_h265_set_me_ram(syn, reg_base, k, tile_start_x);
2904
2905 /* set input info */
2906 vepu580_h265_set_patch_info(frm->reg_cfg, syn, (VepuFmt)fmt->format, enc_task);
2907 if (tile_num > 1)
2908 hal_h265e_v580_set_uniform_tile(reg_base, syn, k, tile_start_x);
2909
2910 if (k) {
2911 RK_U32 offset = 0;
2912
2913 reg_base->reg0176_lpfw_addr = mpp_buffer_get_fd(frm->hw_tile_buf[k]);
2914 reg_base->reg0177_lpfr_addr = mpp_buffer_get_fd(frm->hw_tile_buf[k - 1]);
2915
2916 if (!ctx->tile_parall_en) {
2917 offset = mpp_packet_get_length(enc_task->packet);
2918 offset += stream_len;
2919
2920 reg_base->reg0173_bsbb_addr = mpp_buffer_get_fd(enc_task->output);
2921
2922 mpp_dev_multi_offset_update(frm->reg_cfg, 175, offset);
2923 mpp_dev_multi_offset_update(frm->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
2924 } else {
2925 reg_base->reg0172_bsbt_addr = mpp_buffer_get_fd(frm->hw_tile_stream[k - 1]);
2926 /* TODO: stream size relative with syntax */
2927 reg_base->reg0173_bsbb_addr = reg_base->reg0172_bsbt_addr;
2928 reg_base->reg0174_bsbr_addr = reg_base->reg0172_bsbt_addr;
2929 reg_base->reg0175_adr_bsbs = reg_base->reg0172_bsbt_addr;
2930
2931 mpp_dev_multi_offset_update(frm->reg_cfg, 175, 0);
2932 mpp_dev_multi_offset_update(frm->reg_cfg, 172, mpp_buffer_get_size(frm->hw_tile_stream[k - 1]));
2933 }
2934
2935 offset = ctx->fbc_header_len;
2936
2937 mpp_dev_multi_offset_update(frm->reg_cfg, 166, offset);
2938 mpp_dev_multi_offset_update(frm->reg_cfg, 164, offset);
2939 }
2940
2941 if (enc_task->rc_task->frm.save_pass1)
2942 vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag);
2943
2944 if (enc_task->rc_task->frm.use_pass1)
2945 vepu580_h265e_use_pass1_patch(hw_regs, ctx);
2946
2947 hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out);
2948
2949 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, frm->reg_cfg);
2950
2951 if (k < tile_num - 1) {
2952 if (!ctx->tile_parall_en) {
2953 Vepu580H265Fbk *fb = &frm->feedback;
2954
2955 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2956 if (ret) {
2957 mpp_err_f("send cmd failed %d\n", ret);
2958 }
2959
2960 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2961 if (ret) {
2962 mpp_err_f("poll cmd failed %d\n", ret);
2963 ret = MPP_ERR_VPUHW;
2964 }
2965 stream_len += reg_out->st.bs_lgth_l32;
2966 fb->qp_sum += reg_out->st.qp_sum;
2967 fb->out_strm_size += reg_out->st.bs_lgth_l32;
2968 fb->sse_sum += (RK_S64)(reg_out->st.sse_h32 << 16) +
2969 (reg_out->st.st_sse_bsl.sse_l16 & 0xffff);
2970 fb->st_madi += reg_out->st.madi;
2971 fb->st_madp += reg_out->st.madp;
2972 fb->st_mb_num += reg_out->st.st_bnum_b16.num_b16;
2973 fb->st_ctu_num += reg_out->st.st_bnum_cme.num_ctu;
2974 } else
2975 mpp_dev_ioctl(ctx->dev, MPP_DEV_DELIMIT, NULL);
2976 }
2977 tile_start_x += (syn->pp.column_width_minus1[k] + 1);
2978 }
2979
2980 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2981 if (ret) {
2982 mpp_err_f("send cmd failed %d\n", ret);
2983 }
2984 hal_h265e_leave();
2985 return ret;
2986 }
2987
vepu580_h265_set_feedback(H265eV580HalContext * ctx,HalEncTask * enc_task,RK_U32 index)2988 static MPP_RET vepu580_h265_set_feedback(H265eV580HalContext *ctx, HalEncTask *enc_task, RK_U32 index)
2989 {
2990 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
2991 Vepu580H265eFrmCfg *frm = ctx->frms[enc_task->flags.reg_idx];
2992 Vepu580H265Fbk *fb = &frm->feedback;
2993 MppEncCfgSet *cfg = ctx->cfg;
2994 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
2995 RK_S32 mb8_num = (mb64_num << 6);
2996 RK_S32 mb4_num = (mb8_num << 2);
2997
2998 hal_h265e_enter();
2999 H265eV580StatusElem *elem = frm->regs_ret[index];
3000 RK_U32 hw_status = elem->hw_status;
3001
3002 fb->qp_sum += elem->st.qp_sum;
3003
3004 fb->out_strm_size += elem->st.bs_lgth_l32;
3005
3006 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
3007 (elem->st.st_sse_bsl.sse_l16 & 0xffff);
3008
3009 fb->hw_status = hw_status;
3010 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
3011 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
3012 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
3013
3014 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
3015 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
3016
3017 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
3018 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
3019
3020 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
3021 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
3022
3023 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
3024 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
3025
3026 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
3027 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
3028
3029 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
3030 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
3031
3032 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
3033 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
3034
3035 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
3036 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
3037
3038 fb->st_madi += elem->st.madi;
3039 fb->st_madp += elem->st.madp;
3040 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
3041 fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu;
3042
3043 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
3044 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
3045 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
3046 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
3047 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
3048 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
3049 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
3050 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
3051 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp0, 52 * sizeof(RK_U32));
3052
3053 if (index == (ctx->tile_num - 1)) {
3054 hal_rc_ret->bit_real += fb->out_strm_size * 8;
3055
3056 if (fb->st_mb_num) {
3057 fb->st_madi = fb->st_madi / fb->st_mb_num;
3058 } else {
3059 fb->st_madi = 0;
3060 }
3061 if (fb->st_ctu_num) {
3062 fb->st_madp = fb->st_madp / fb->st_ctu_num;
3063 } else {
3064 fb->st_madp = 0;
3065 }
3066
3067 if (mb4_num > 0)
3068 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
3069 (fb->st_lvl16_intra_num << 4) +
3070 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
3071
3072 if (mb64_num > 0) {
3073 /*
3074 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
3075 (fb->st_lvl32_inter_num << 4) +
3076 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
3077
3078 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
3079 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
3080 }
3081
3082 hal_rc_ret->madi += fb->st_madi;
3083 hal_rc_ret->madp += fb->st_madp;
3084 }
3085 hal_h265e_leave();
3086 return MPP_OK;
3087 }
3088
save_to_file(char * name,void * ptr,size_t size)3089 void save_to_file(char *name, void *ptr, size_t size)
3090 {
3091 FILE *fp = fopen(name, "w+b");
3092 if (fp) {
3093 fwrite(ptr, 1, size, fp);
3094 fclose(fp);
3095 } else
3096 mpp_err("create file %s failed\n", name);
3097 }
3098
dump_files(H265eV580HalContext * ctx,HalEncTask * enc_task)3099 void dump_files(H265eV580HalContext *ctx, HalEncTask *enc_task)
3100 {
3101 H265eSyntax_new *syn = ctx->syn;
3102 HalBuf *hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
3103 size_t buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
3104 size_t dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
3105 void *ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
3106 void *dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
3107 RK_U32 frm_num = ctx->frms[enc_task->flags.reg_idx]->frame_count;
3108 RK_S32 pid = getpid();
3109 char name[128];
3110 size_t name_len = sizeof(name) - 1;
3111
3112 snprintf(name, name_len, "/data/refr_fbd_%d_frm%d.bin", pid, frm_num);
3113 save_to_file(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
3114
3115 snprintf(name, name_len, "/data/refr_fbh_%d_frm%d.bin", pid, frm_num);
3116 save_to_file(name, ptr, ctx->fbc_header_len);
3117
3118 snprintf(name, name_len, "/data/refr_dsp_%d_frm%d.bin", pid, frm_num);
3119 save_to_file(name, dws_ptr, dws_size);
3120
3121 hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
3122 buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
3123 dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
3124 ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
3125 dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
3126
3127 snprintf(name, name_len, "/data/recn_fbd_%d_frm%d.bin", pid, frm_num);
3128 save_to_file(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
3129
3130 snprintf(name, name_len, "/data/recn_fbh_%d_frm%d.bin", pid, frm_num);
3131 save_to_file(name, ptr, ctx->fbc_header_len);
3132
3133 snprintf(name, name_len, "/data/recn_dsp_%d_frm%d.bin", pid, frm_num);
3134 save_to_file(name, dws_ptr, dws_size);
3135 }
3136
hal_h265e_vepu580_status_check(RK_U32 hw_status)3137 static MPP_RET hal_h265e_vepu580_status_check(RK_U32 hw_status)
3138 {
3139 MPP_RET ret = MPP_OK;
3140
3141 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
3142 hal_h265e_dbg_detail("RKV_ENC_INT_LINKTABLE_FINISH");
3143
3144 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
3145 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
3146
3147 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
3148 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
3149
3150 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
3151 hal_h265e_dbg_detail("RKV_ENC_INT_SAFE_CLEAR_FINISH");
3152
3153 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
3154 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
3155
3156 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL) {
3157 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
3158 ret = MPP_NOK;
3159 }
3160
3161 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR) {
3162 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
3163 ret = MPP_NOK;
3164 }
3165
3166 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR) {
3167 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
3168 ret = MPP_NOK;
3169 }
3170
3171 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR) {
3172 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
3173 ret = MPP_NOK;
3174 }
3175
3176 return ret;
3177 }
3178
hal_h265e_v580_wait(void * hal,HalEncTask * task)3179 MPP_RET hal_h265e_v580_wait(void *hal, HalEncTask *task)
3180 {
3181 MPP_RET ret = MPP_OK;
3182 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3183 HalEncTask *enc_task = task;
3184 RK_U32 split_out = ctx->cfg->split.split_out;
3185 RK_S32 task_idx = task->flags.reg_idx;
3186 Vepu580H265eFrmCfg *frm = ctx->frms[task_idx];
3187
3188 hal_h265e_enter();
3189
3190 if (enc_task->flags.err) {
3191 hal_h265e_err("enc_task->flags.err %08x, return early",
3192 enc_task->flags.err);
3193 return MPP_NOK;
3194 }
3195
3196 /* if pass1 mode, it will disable split mode and the split out need to be disable */
3197 if (enc_task->rc_task->frm.save_pass1)
3198 split_out = 0;
3199
3200 if (split_out) {
3201 EncOutParam param;
3202 RK_U32 slice_len = 0;
3203 RK_U32 slice_last = 0;
3204 RK_U32 finish_cnt = 0;
3205 RK_U32 tile1_offset = 0;
3206 MppPacket pkt = enc_task->packet;
3207 RK_U32 offset = mpp_packet_get_length(pkt);
3208 RK_U32 seg_offset = offset;
3209 void* ptr = mpp_packet_get_pos(pkt);
3210 H265eV580RegSet *regs = frm->regs_set[0];
3211 hevc_vepu580_base *reg_base = ®s->reg_base;
3212 RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;
3213 MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
3214
3215 param.task = task;
3216 param.base = mpp_packet_get_data(task->packet);
3217
3218 do {
3219 RK_S32 i = 0;
3220 poll_cfg->poll_type = 0;
3221 poll_cfg->poll_ret = 0;
3222 poll_cfg->count_max = split_out & MPP_ENC_SPLIT_OUT_LOWDELAY ? 1 : ctx->poll_slice_max;
3223 poll_cfg->count_ret = 0;
3224
3225 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
3226
3227 for (i = 0; i < poll_cfg->count_ret; i++) {
3228 slice_last = poll_cfg->slice_info[i].last;
3229 slice_len = poll_cfg->slice_info[i].length;
3230 param.length = slice_len;
3231
3232 if (finish_cnt > 0) {
3233 MppBuffer buf = frm->hw_tile_stream[finish_cnt - 1];
3234 void *tile1_ptr = mpp_buffer_get_ptr(buf);
3235
3236 mpp_buffer_sync_ro_partial_begin(buf, tile1_offset, slice_len);
3237 memcpy(ptr + seg_offset, tile1_ptr + tile1_offset, slice_len);
3238 tile1_offset += slice_len;
3239 } else {
3240 MppBuffer buf = enc_task->output;
3241
3242 mpp_buffer_sync_ro_partial_begin(buf, offset, slice_len);
3243 }
3244
3245 ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
3246 if (slice_last) {
3247 finish_cnt++;
3248 tile1_offset = 0;
3249 if (ctx->tile_parall_en) {
3250 if (finish_cnt + 1 > ctx->tile_num) {
3251 ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
3252 }
3253 }
3254 }
3255
3256 mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
3257
3258 if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY)
3259 mpp_callback(ctx->output_cb, ¶m);
3260
3261 seg_offset += slice_len;
3262 }
3263
3264 if (ctx->tile_parall_en) {
3265 if (finish_cnt + 1 > ctx->tile_num) {
3266 break;
3267 }
3268 } else if (slice_last) {
3269 break;
3270 }
3271 } while (1);
3272 } else {
3273 H265eV580StatusElem *elem = frm->regs_ret[0];
3274 H265eV580RegSet *regs = frm->regs_set[0];
3275 hevc_vepu580_base *reg_base = ®s->reg_base;
3276 RK_U32 type = reg_base->reg0236_synt_nal.nal_unit_type;
3277 MppPacket pkt = enc_task->packet;
3278 RK_U32 offset = mpp_packet_get_length(pkt);
3279 RK_U32 i = 0;
3280
3281 if (ctx->tile_parall_en) {
3282 for (i = 0; i < ctx->tile_num; i ++)
3283 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
3284 } else {
3285 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
3286 }
3287
3288 for (i = 0; i < ctx->tile_num; i++) {
3289 H265eV580StatusElem *elem_ret = frm->regs_ret[i];
3290 RK_U32 hw_status = elem_ret->hw_status;
3291 RK_U32 tile_size = elem_ret->st.bs_lgth_l32;
3292
3293 ret = hal_h265e_vepu580_status_check(hw_status);
3294 if (ret)
3295 break;
3296 mpp_packet_add_segment_info(pkt, type, offset, tile_size);
3297 offset += tile_size;
3298
3299 if (ctx->tile_dump_err &&
3300 (hw_status & (RKV_ENC_INT_BUS_WRITE_ERROR | RKV_ENC_INT_BUS_READ_ERROR))) {
3301 dump_files(ctx, enc_task);
3302 break;
3303 }
3304 }
3305
3306 if (ret)
3307 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
3308 }
3309
3310 hal_h265e_leave();
3311
3312 return ret;
3313 }
3314
hal_h265e_v580_get_task(void * hal,HalEncTask * task)3315 MPP_RET hal_h265e_v580_get_task(void *hal, HalEncTask *task)
3316 {
3317 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3318 Vepu580H265eFrmCfg *frm_cfg = NULL;
3319 EncFrmStatus *frm_status = &task->rc_task->frm;
3320 MppFrame frame = task->frame;
3321 RK_S32 task_idx = ctx->task_idx;
3322
3323 hal_h265e_enter();
3324
3325 task->part_first = 1;
3326 task->part_last = 0;
3327 task->flags.reg_idx = task_idx;
3328
3329 if (!frm_status->reencode) {
3330 ctx->syn = (H265eSyntax_new *)task->syntax.data;
3331 ctx->dpb = (H265eDpb*)ctx->syn->dpb;
3332
3333 if (vepu580_h265_setup_hal_bufs(ctx)) {
3334 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
3335 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
3336 return MPP_ERR_MALLOC;
3337 }
3338
3339 ctx->last_frame_type = ctx->frame_type;
3340
3341 frm_cfg = ctx->frms[task_idx];
3342 ctx->frm = frm_cfg;
3343
3344 if (mpp_frame_has_meta(task->frame)) {
3345 MppMeta meta = mpp_frame_get_meta(frame);
3346
3347 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA2, (void **)&frm_cfg->roi_data, NULL);
3348 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA, (void **)&frm_cfg->osd_cfg.osd_data, NULL);
3349 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA2, (void **)&frm_cfg->osd_cfg.osd_data2, NULL);
3350 } else {
3351 frm_cfg->roi_data = NULL;
3352 frm_cfg->osd_cfg.osd_data = NULL;
3353 frm_cfg->osd_cfg.osd_data2 = NULL;
3354 }
3355
3356 frm_cfg->frame_count = ctx->frame_count++;
3357
3358 ctx->task_idx++;
3359 if (ctx->task_idx >= ctx->task_cnt)
3360 ctx->task_idx = 0;
3361
3362 frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
3363 frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
3364 } else {
3365 /* reencode path may change the frame type */
3366 frm_cfg = ctx->frm;
3367 }
3368
3369 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
3370 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
3371
3372 ctx->frame_type = (frm_status->is_intra) ? INTRA_FRAME : INTER_P_FRAME;
3373 frm_cfg->frame_type = ctx->frame_type;
3374 mpp_dev_multi_offset_reset(frm_cfg->reg_cfg);
3375 memset(&frm_cfg->feedback, 0, sizeof(frm_cfg->feedback));
3376
3377 hal_h265e_leave();
3378 return MPP_OK;
3379 }
3380
hal_h265e_v580_ret_task(void * hal,HalEncTask * task)3381 MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
3382 {
3383 H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
3384 EncRcTaskInfo *rc_info = &task->rc_task->info;
3385 HalEncTask *enc_task = task;
3386 RK_S32 task_idx = task->flags.reg_idx;
3387 Vepu580H265eFrmCfg *frm = ctx->frms[task_idx];
3388 Vepu580H265Fbk *fb = &frm->feedback;
3389 H265eSyntax_new *syn = (H265eSyntax_new *) enc_task->syntax.data;
3390 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
3391
3392 hal_h265e_enter();
3393
3394 if (ctx->tile_parall_en) {
3395 RK_U32 i = 0, stream_len = 0;
3396 void* ptr = mpp_packet_get_pos(enc_task->packet);
3397
3398 for (i = 0; i < ctx->tile_num; i ++) {
3399 vepu580_h265_set_feedback(ctx, enc_task, i);
3400 if (!ctx->cfg->split.split_out) {
3401 if (i) { //copy tile 1 stream
3402 RK_U32 len = fb->out_strm_size - stream_len;
3403 MppBuffer buf = frm->hw_tile_stream[i - 1];
3404 RK_U8 *tile1_ptr = mpp_buffer_get_ptr(buf);
3405
3406 mpp_buffer_sync_partial_begin(buf, 0, len);
3407
3408 if (syn->sp.temporal_id && len > 5)
3409 tile1_ptr[5] = (tile1_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
3410
3411 memcpy(ptr + stream_len + offset, tile1_ptr, len);
3412 } else {
3413 MppBuffer buf = enc_task->output;
3414 RK_U32 len = fb->out_strm_size;
3415 RK_U8 *stream_ptr = (RK_U8 *) ptr;
3416
3417 mpp_buffer_sync_partial_begin(buf, offset, len);
3418
3419 if (syn->sp.temporal_id) {
3420 stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
3421 }
3422 }
3423 stream_len = fb->out_strm_size;
3424 }
3425 }
3426 } else {
3427 vepu580_h265_set_feedback(ctx, enc_task, ctx->tile_num - 1);
3428 mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
3429 hal_h265e_amend_temporal_id(task, fb->out_strm_size);
3430 }
3431
3432 rc_info->sse = fb->sse_sum;
3433 rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
3434 rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
3435 rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
3436 rc_info->lvl8_inter_num = fb->st_lvl8_inter_num;
3437 rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
3438 rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
3439 rc_info->lvl8_intra_num = fb->st_lvl8_intra_num;
3440 rc_info->lvl4_intra_num = fb->st_lvl4_intra_num;
3441
3442 enc_task->hw_length = fb->out_strm_size;
3443 enc_task->length += fb->out_strm_size;
3444
3445 vepu580_h265e_tune_stat_update(ctx->tune, rc_info);
3446
3447 h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
3448 h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
3449
3450 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
3451
3452 hal_h265e_leave();
3453 return MPP_OK;
3454 }
3455
3456 const MppEncHalApi hal_h265e_vepu580 = {
3457 "hal_h265e_v580",
3458 MPP_VIDEO_CodingHEVC,
3459 sizeof(H265eV580HalContext),
3460 0,
3461 hal_h265e_v580_init,
3462 hal_h265e_v580_deinit,
3463 hal_h265e_vepu580_prepare,
3464 hal_h265e_v580_get_task,
3465 hal_h265e_v580_gen_regs,
3466 hal_h265e_v580_start,
3467 hal_h265e_v580_wait,
3468 NULL,
3469 NULL,
3470 hal_h265e_v580_ret_task,
3471 };
3472