1 /*
2 * Copyright 2020 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp9d_rkv"
18
19 #include <stdio.h>
20 #include <string.h>
21
22 #include "mpp_env.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25
26 #include "hal_vp9d_debug.h"
27 #include "hal_vp9d_ctx.h"
28 #include "hal_vp9d_com.h"
29 #include "hal_vp9d_rkv.h"
30 #include "hal_vp9d_rkv_reg.h"
31 #include "vp9d_syntax.h"
32
33
34 typedef struct Vp9dRkvCtx_t {
35 Vp9dRegBuf g_buf[MAX_GEN_REG];
36 MppBuffer probe_base;
37 MppBuffer count_base;
38 MppBuffer segid_cur_base;
39 MppBuffer segid_last_base;
40 void* hw_regs;
41 RK_S32 mv_base_addr;
42 RK_U32 mv_base_offset;
43 RK_S32 pre_mv_base_addr;
44 RK_U32 pre_mv_base_offset;
45 Vp9dLastInfo ls_info;
46 /*
47 * swap between segid_cur_base & segid_last_base
48 * 0 used segid_cur_base as last
49 * 1 used segid_last_base as
50 */
51 RK_U32 last_segid_flag;
52 } Vp9dRkvCtx;
53
hal_vp9d_alloc_res(HalVp9dCtx * hal)54 static MPP_RET hal_vp9d_alloc_res(HalVp9dCtx *hal)
55 {
56 RK_S32 i = 0;
57 RK_S32 ret = 0;
58 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
59 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
60
61 if (p_hal->fast_mode) {
62 for (i = 0; i < MAX_GEN_REG; i++) {
63 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS));
64 ret = mpp_buffer_get(p_hal->group,
65 &hw_ctx->g_buf[i].probe_base, PROB_SIZE);
66 if (ret) {
67 mpp_err("vp9 probe_base get buffer failed\n");
68 return ret;
69 }
70 ret = mpp_buffer_get(p_hal->group,
71 &hw_ctx->g_buf[i].count_base, COUNT_SIZE);
72 if (ret) {
73 mpp_err("vp9 count_base get buffer failed\n");
74 return ret;
75 }
76 ret = mpp_buffer_get(p_hal->group,
77 &hw_ctx->g_buf[i].segid_cur_base, MAX_SEGMAP_SIZE);
78 if (ret) {
79 mpp_err("vp9 segid_cur_base get buffer failed\n");
80 return ret;
81 }
82 ret = mpp_buffer_get(p_hal->group,
83 &hw_ctx->g_buf[i].segid_last_base, MAX_SEGMAP_SIZE);
84 if (ret) {
85 mpp_err("vp9 segid_last_base get buffer failed\n");
86 return ret;
87 }
88 }
89 } else {
90 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(VP9_REGS));
91 ret = mpp_buffer_get(p_hal->group, &hw_ctx->probe_base, PROB_SIZE);
92 if (ret) {
93 mpp_err("vp9 probe_base get buffer failed\n");
94 return ret;
95 }
96 ret = mpp_buffer_get(p_hal->group, &hw_ctx->count_base, COUNT_SIZE);
97 if (ret) {
98 mpp_err("vp9 count_base get buffer failed\n");
99 return ret;
100 }
101 ret = mpp_buffer_get(p_hal->group, &hw_ctx->segid_cur_base, MAX_SEGMAP_SIZE);
102 if (ret) {
103 mpp_err("vp9 segid_cur_base get buffer failed\n");
104 return ret;
105 }
106 ret = mpp_buffer_get(p_hal->group, &hw_ctx->segid_last_base, MAX_SEGMAP_SIZE);
107 if (ret) {
108 mpp_err("vp9 segid_last_base get buffer failed\n");
109 return ret;
110 }
111 }
112 return MPP_OK;
113 }
114
hal_vp9d_release_res(HalVp9dCtx * hal)115 static MPP_RET hal_vp9d_release_res(HalVp9dCtx *hal)
116 {
117 RK_S32 i = 0;
118 RK_S32 ret = 0;
119 HalVp9dCtx *p_hal = hal;
120 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
121
122 if (p_hal->fast_mode) {
123 for (i = 0; i < MAX_GEN_REG; i++) {
124 if (hw_ctx->g_buf[i].probe_base) {
125 ret = mpp_buffer_put(hw_ctx->g_buf[i].probe_base);
126 if (ret) {
127 mpp_err("vp9 probe_base put buffer failed\n");
128 return ret;
129 }
130 }
131 if (hw_ctx->g_buf[i].count_base) {
132 ret = mpp_buffer_put(hw_ctx->g_buf[i].count_base);
133 if (ret) {
134 mpp_err("vp9 count_base put buffer failed\n");
135 return ret;
136 }
137 }
138 if (hw_ctx->g_buf[i].segid_cur_base) {
139 ret = mpp_buffer_put(hw_ctx->g_buf[i].segid_cur_base);
140 if (ret) {
141 mpp_err("vp9 segid_cur_base put buffer failed\n");
142 return ret;
143 }
144 }
145 if (hw_ctx->g_buf[i].segid_last_base) {
146 ret = mpp_buffer_put(hw_ctx->g_buf[i].segid_last_base);
147 if (ret) {
148 mpp_err("vp9 segid_last_base put buffer failed\n");
149 return ret;
150 }
151 }
152 if (hw_ctx->g_buf[i].hw_regs) {
153 mpp_free(hw_ctx->g_buf[i].hw_regs);
154 hw_ctx->g_buf[i].hw_regs = NULL;
155 }
156 }
157 } else {
158 if (hw_ctx->probe_base) {
159 ret = mpp_buffer_put(hw_ctx->probe_base);
160 if (ret) {
161 mpp_err("vp9 probe_base get buffer failed\n");
162 return ret;
163 }
164 }
165 if (hw_ctx->count_base) {
166 ret = mpp_buffer_put(hw_ctx->count_base);
167 if (ret) {
168 mpp_err("vp9 count_base put buffer failed\n");
169 return ret;
170 }
171 }
172 if (hw_ctx->segid_cur_base) {
173 ret = mpp_buffer_put(hw_ctx->segid_cur_base);
174 if (ret) {
175 mpp_err("vp9 segid_cur_base put buffer failed\n");
176 return ret;
177 }
178 }
179 if (hw_ctx->segid_last_base) {
180 ret = mpp_buffer_put(hw_ctx->segid_last_base);
181 if (ret) {
182 mpp_err("vp9 segid_last_base put buffer failed\n");
183 return ret;
184 }
185 }
186 if (hw_ctx->hw_regs) {
187 mpp_free(hw_ctx->hw_regs);
188 hw_ctx->hw_regs = NULL;
189 }
190 }
191 return MPP_OK;
192 }
193
hal_vp9d_rkv_init(void * hal,MppHalCfg * cfg)194 MPP_RET hal_vp9d_rkv_init(void *hal, MppHalCfg *cfg)
195 {
196 MPP_RET ret = MPP_OK;
197 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
198 MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vp9dRkvCtx)));
199 Vp9dRkvCtx *ctx = (Vp9dRkvCtx *)p_hal->hw_ctx;
200
201 mpp_log("hal_vp9d_rkv_init in");
202 ctx->mv_base_addr = -1;
203 ctx->pre_mv_base_addr = -1;
204 mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
205 mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, vp9_ver_align);
206
207 if (p_hal->group == NULL) {
208 ret = mpp_buffer_group_get_internal(&p_hal->group, MPP_BUFFER_TYPE_ION);
209 if (ret) {
210 mpp_err("vp9 mpp_buffer_group_get failed\n");
211 return ret;
212 }
213 }
214
215 ret = hal_vp9d_alloc_res(p_hal);
216 if (ret) {
217 mpp_err("hal_vp9d_alloc_res failed\n");
218 return ret;
219 }
220
221 ctx->last_segid_flag = 1;
222
223 (void) cfg;
224 return ret = MPP_OK;
225 __FAILED:
226 return ret = MPP_NOK;
227 }
228
hal_vp9d_rkv_deinit(void * hal)229 MPP_RET hal_vp9d_rkv_deinit(void *hal)
230 {
231 MPP_RET ret = MPP_OK;
232 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
233
234 hal_vp9d_release_res(p_hal);
235
236 if (p_hal->group) {
237 ret = mpp_buffer_group_put(p_hal->group);
238 if (ret) {
239 mpp_err("vp9d group free buffer failed\n");
240 return ret;
241 }
242 }
243 MPP_FREE(p_hal->hw_ctx);
244 return ret = MPP_OK;
245 }
246
hal_vp9d_rkv_gen_regs(void * hal,HalTaskInfo * task)247 MPP_RET hal_vp9d_rkv_gen_regs(void *hal, HalTaskInfo *task)
248 {
249 RK_S32 i;
250 RK_U8 bit_depth = 0;
251 RK_U32 ref_frame_width_y;
252 RK_U32 ref_frame_height_y;
253 RK_S32 stream_len = 0, aglin_offset = 0;
254 RK_U32 y_hor_virstride, uv_hor_virstride, y_virstride, uv_virstride, yuv_virstride;
255 RK_U8 *bitstream = NULL;
256 MppBuffer streambuf = NULL;
257 RK_U32 sw_y_hor_virstride;
258 RK_U32 sw_uv_hor_virstride;
259 RK_U32 sw_y_virstride;
260 RK_U32 sw_uv_virstride;
261 RK_U32 sw_yuv_virstride ;
262 RK_U8 ref_idx = 0;
263 RK_U8 ref_frame_idx = 0;
264 RK_U32 *reg_ref_base = 0;
265 RK_S32 intraFlag = 0;
266 MppBuffer framebuf = NULL;
267 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
268 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
269 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
270 MppFrame mframe = NULL;
271
272 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
273
274 if (p_hal->fast_mode) {
275 for (i = 0; i < MAX_GEN_REG; i++) {
276 if (!hw_ctx->g_buf[i].use_flag) {
277 task->dec.reg_index = i;
278 hw_ctx->probe_base = hw_ctx->g_buf[i].probe_base;
279 hw_ctx->count_base = hw_ctx->g_buf[i].count_base;
280 hw_ctx->segid_cur_base = hw_ctx->g_buf[i].segid_cur_base;
281 hw_ctx->segid_last_base = hw_ctx->g_buf[i].segid_last_base;
282 hw_ctx->hw_regs = hw_ctx->g_buf[i].hw_regs;
283 hw_ctx->g_buf[i].use_flag = 1;
284 break;
285 }
286 }
287 if (i == MAX_GEN_REG) {
288 mpp_err("vp9 fast mode buf all used\n");
289 return MPP_ERR_NOMEM;
290 }
291 }
292 VP9_REGS *vp9_hw_regs = (VP9_REGS*)hw_ctx->hw_regs;
293 intraFlag = (!pic_param->frame_type || pic_param->intra_only);
294 hal_vp9d_output_probe(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
295 mpp_buffer_sync_end(hw_ctx->count_base);
296 stream_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);
297 memset(hw_ctx->hw_regs, 0, sizeof(VP9_REGS));
298 vp9_hw_regs->swreg2_sysctrl.sw_dec_mode = 2; //set as vp9 dec
299 vp9_hw_regs->swreg5_stream_len = ((stream_len + 15) & (~15)) + 0x80;
300
301 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
302 bitstream = mpp_buffer_get_ptr(streambuf);
303 aglin_offset = vp9_hw_regs->swreg5_stream_len - stream_len;
304 if (aglin_offset > 0) {
305 memset((void *)(bitstream + stream_len), 0, aglin_offset);
306 }
307
308 //--- caculate the yuv_frame_size and mv_size
309 bit_depth = pic_param->BitDepthMinus8Luma + 8;
310
311 sw_y_hor_virstride = mpp_frame_get_hor_stride(mframe) >> 4;
312 sw_uv_hor_virstride = mpp_frame_get_hor_stride(mframe) >> 4;
313 sw_y_virstride = sw_y_hor_virstride * mpp_frame_get_ver_stride(mframe);
314
315 sw_uv_virstride = sw_uv_hor_virstride * mpp_frame_get_ver_stride(mframe) / 2;
316 sw_yuv_virstride = sw_y_virstride + sw_uv_virstride;
317
318 vp9_hw_regs->swreg3_picpar.sw_y_hor_virstride = sw_y_hor_virstride;
319 vp9_hw_regs->swreg3_picpar.sw_uv_hor_virstride = sw_uv_hor_virstride;
320 vp9_hw_regs->swreg8_y_virstride.sw_y_virstride = sw_y_virstride;
321 vp9_hw_regs->swreg9_yuv_virstride.sw_yuv_virstride = sw_yuv_virstride;
322
323 if (!pic_param->intra_only && pic_param->frame_type &&
324 !pic_param->error_resilient_mode && hw_ctx->ls_info.last_show_frame) {
325 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
326 hw_ctx->pre_mv_base_offset = hw_ctx->mv_base_offset;
327 }
328
329
330 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &framebuf);
331 vp9_hw_regs->swreg7_decout_base = mpp_buffer_get_fd(framebuf);
332 vp9_hw_regs->swreg4_strm_rlc_base = mpp_buffer_get_fd(streambuf);
333
334 vp9_hw_regs->swreg6_cabactbl_prob_base = mpp_buffer_get_fd(hw_ctx->probe_base);
335 vp9_hw_regs->swreg14_vp9_count_base = mpp_buffer_get_fd(hw_ctx->count_base);
336
337 if (hw_ctx->last_segid_flag) {
338 vp9_hw_regs->swreg15_vp9_segidlast_base = mpp_buffer_get_fd(hw_ctx->segid_last_base);
339 vp9_hw_regs->swreg16_vp9_segidcur_base = mpp_buffer_get_fd(hw_ctx->segid_cur_base);
340 } else {
341 vp9_hw_regs->swreg15_vp9_segidlast_base = mpp_buffer_get_fd(hw_ctx->segid_cur_base);
342 vp9_hw_regs->swreg16_vp9_segidcur_base = mpp_buffer_get_fd(hw_ctx->segid_last_base);
343 }
344
345 if (pic_param->stVP9Segments.enabled && pic_param->stVP9Segments.update_map) {
346 hw_ctx->last_segid_flag = !hw_ctx->last_segid_flag;
347 }
348
349 hw_ctx->mv_base_addr = vp9_hw_regs->swreg7_decout_base;
350 hw_ctx->mv_base_offset = mpp_get_ioctl_version() ? sw_yuv_virstride << 4 : sw_yuv_virstride;
351 if (hw_ctx->pre_mv_base_addr < 0) {
352 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
353 hw_ctx->pre_mv_base_offset = hw_ctx->mv_base_offset;
354 }
355 vp9_hw_regs->swreg52_vp9_refcolmv_base = hw_ctx->pre_mv_base_addr;
356 mpp_dev_set_reg_offset(p_hal->dev, 52, hw_ctx->pre_mv_base_offset);
357
358 vp9_hw_regs->swreg10_vp9_cprheader_offset.sw_vp9_cprheader_offset = 0; //no use now.
359 reg_ref_base = &vp9_hw_regs->swreg11_vp9_referlast_base;
360 for (i = 0; i < 3; i++) {
361 ref_idx = pic_param->frame_refs[i].Index7Bits;
362 ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;
363 ref_frame_width_y = pic_param->ref_frame_coded_width[ref_idx];
364 ref_frame_height_y = pic_param->ref_frame_coded_height[ref_idx];
365 if (ref_frame_idx < 0x7f) {
366 mpp_buf_slot_get_prop(p_hal->slots, ref_frame_idx, SLOT_FRAME_PTR, &mframe);
367 y_hor_virstride = mpp_frame_get_hor_stride(mframe) >> 4;
368 uv_hor_virstride = mpp_frame_get_hor_stride(mframe) >> 4;
369 y_virstride = y_hor_virstride * mpp_frame_get_ver_stride(mframe);
370 uv_virstride = uv_hor_virstride * mpp_frame_get_ver_stride(mframe) / 2;
371 } else {
372 y_hor_virstride = (vp9_hor_align((ref_frame_width_y * bit_depth) >> 3) >> 4);
373 uv_hor_virstride = (vp9_hor_align((ref_frame_width_y * bit_depth) >> 3) >> 4);
374 y_virstride = y_hor_virstride * vp9_ver_align(ref_frame_height_y);
375 uv_virstride = uv_hor_virstride * vp9_ver_align(ref_frame_height_y) / 2;
376 }
377 yuv_virstride = y_virstride + uv_virstride;
378
379 if (ref_frame_idx < 0x7f)
380 mpp_buf_slot_get_prop(p_hal->slots, ref_frame_idx, SLOT_BUFFER, &framebuf);
381
382 if (ref_frame_idx < 0x7f) {
383 switch (i) {
384 case 0: {
385 vp9_hw_regs->swreg17_vp9_frame_size_last.sw_framewidth_last = ref_frame_width_y;
386 vp9_hw_regs->swreg17_vp9_frame_size_last.sw_frameheight_last = ref_frame_height_y;
387 vp9_hw_regs->swreg37_vp9_lastf_hor_virstride.sw_vp9_lastfy_hor_virstride = y_hor_virstride;
388 vp9_hw_regs->swreg37_vp9_lastf_hor_virstride.sw_vp9_lastfuv_hor_virstride = uv_hor_virstride;
389 vp9_hw_regs->swreg48_vp9_last_ystride.sw_vp9_lastfy_virstride = y_virstride;
390 vp9_hw_regs->swreg51_vp9_lastref_yuvstride.sw_vp9_lastref_yuv_virstride = yuv_virstride;
391 break;
392 }
393 case 1: {
394 vp9_hw_regs->swreg18_vp9_frame_size_golden.sw_framewidth_golden = ref_frame_width_y;
395 vp9_hw_regs->swreg18_vp9_frame_size_golden.sw_frameheight_golden = ref_frame_height_y;
396 vp9_hw_regs->swreg38_vp9_goldenf_hor_virstride.sw_vp9_goldenfy_hor_virstride = y_hor_virstride;
397 vp9_hw_regs->swreg38_vp9_goldenf_hor_virstride.sw_vp9_goldenuv_hor_virstride = uv_hor_virstride;
398 vp9_hw_regs->swreg49_vp9_golden_ystride.sw_vp9_goldeny_virstride = y_virstride;
399 break;
400 }
401 case 2: {
402 vp9_hw_regs->swreg19_vp9_frame_size_altref.sw_framewidth_alfter = ref_frame_width_y;
403 vp9_hw_regs->swreg19_vp9_frame_size_altref.sw_frameheight_alfter = ref_frame_height_y;
404 vp9_hw_regs->swreg39_vp9_altreff_hor_virstride.sw_vp9_altreffy_hor_virstride = y_hor_virstride;
405 vp9_hw_regs->swreg39_vp9_altreff_hor_virstride.sw_vp9_altreffuv_hor_virstride = uv_hor_virstride;
406 vp9_hw_regs->swreg50_vp9_altrefy_ystride.sw_vp9_altrefy_virstride = y_virstride;
407 break;
408 }
409 default:
410 break;
411 }
412
413 /*0 map to 11*/
414 /*1 map to 12*/
415 /*2 map to 13*/
416 if (framebuf != NULL) {
417 reg_ref_base[i] = mpp_buffer_get_fd(framebuf);
418 } else {
419 mpp_log("ref buff address is no valid used out as base slot index 0x%x", ref_frame_idx);
420 reg_ref_base[i] = vp9_hw_regs->swreg7_decout_base; //set
421 }
422 } else {
423 reg_ref_base[i] = vp9_hw_regs->swreg7_decout_base; //set
424 }
425 }
426
427 for (i = 0; i < 8; i++) {
428 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_frame_qp_delta_en = (hw_ctx->ls_info.feature_mask[i]) & 0x1;
429 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_frame_qp_delta = hw_ctx->ls_info.feature_data[i][0];
430 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_frame_loopfitler_value_en = (hw_ctx->ls_info.feature_mask[i] >> 1) & 0x1;
431 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_frame_loopfilter_value = hw_ctx->ls_info.feature_data[i][1];
432 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_referinfo_en = (hw_ctx->ls_info.feature_mask[i] >> 2) & 0x1;
433 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_referinfo = hw_ctx->ls_info.feature_data[i][2];
434 vp9_hw_regs->swreg20_27_vp9_segid_grp[i].sw_vp9segid_frame_skip_en = (hw_ctx->ls_info.feature_mask[i] >> 3) & 0x1;
435 }
436
437
438 vp9_hw_regs->swreg20_27_vp9_segid_grp[0].sw_vp9segid_abs_delta = hw_ctx->ls_info.abs_delta_last;
439
440 vp9_hw_regs->swreg28_vp9_cprheader_config.sw_vp9_tx_mode = pic_param->txmode;
441
442 vp9_hw_regs->swreg28_vp9_cprheader_config.sw_vp9_frame_reference_mode = pic_param->refmode;
443
444 vp9_hw_regs->swreg32_vp9_ref_deltas_lastframe.sw_vp9_ref_deltas_lastframe = 0;
445
446 if (!intraFlag) {
447 for (i = 0; i < 4; i++)
448 vp9_hw_regs->swreg32_vp9_ref_deltas_lastframe.sw_vp9_ref_deltas_lastframe |= (hw_ctx->ls_info.last_ref_deltas[i] & 0x7f) << (7 * i);
449
450 for (i = 0; i < 2; i++)
451 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_vp9_mode_deltas_lastframe |= (hw_ctx->ls_info.last_mode_deltas[i] & 0x7f) << (7 * i);
452
453
454 } else {
455 hw_ctx->ls_info.segmentation_enable_flag_last = 0;
456 hw_ctx->ls_info.last_intra_only = 1;
457 }
458
459 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_vp9_mode_deltas_lastframe = 0;
460
461 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_segmentation_enable_lstframe = hw_ctx->ls_info.segmentation_enable_flag_last;
462 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_vp9_last_show_frame = hw_ctx->ls_info.last_show_frame;
463 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_vp9_last_intra_only = hw_ctx->ls_info.last_intra_only;
464 vp9_hw_regs->swreg33_vp9_info_lastframe.sw_vp9_last_widthheight_eqcur = (pic_param->width == hw_ctx->ls_info.last_width) && (pic_param->height == hw_ctx->ls_info.last_height);
465
466 vp9_hw_regs->swreg36_vp9_lasttile_size.sw_vp9_lasttile_size = stream_len - pic_param->first_partition_size;
467
468
469 if (!intraFlag) {
470 vp9_hw_regs->swreg29_vp9_lref_scale.sw_vp9_lref_hor_scale = pic_param->mvscale[0][0];
471 vp9_hw_regs->swreg29_vp9_lref_scale.sw_vp9_lref_ver_scale = pic_param->mvscale[0][1];
472 vp9_hw_regs->swreg30_vp9_gref_scale.sw_vp9_gref_hor_scale = pic_param->mvscale[1][0];
473 vp9_hw_regs->swreg30_vp9_gref_scale.sw_vp9_gref_ver_scale = pic_param->mvscale[1][1];
474 vp9_hw_regs->swreg31_vp9_aref_scale.sw_vp9_aref_hor_scale = pic_param->mvscale[2][0];
475 vp9_hw_regs->swreg31_vp9_aref_scale.sw_vp9_aref_ver_scale = pic_param->mvscale[2][1];
476 // vp9_hw_regs.swreg33_vp9_info_lastframe.sw_vp9_color_space_lastkeyframe = p_cm->color_space_last;
477 }
478
479
480 //reuse reg64, and it will be written by hardware to show performance.
481 vp9_hw_regs->swreg64_performance_cycle.sw_performance_cycle = 0;
482 vp9_hw_regs->swreg64_performance_cycle.sw_performance_cycle |= pic_param->width;
483 vp9_hw_regs->swreg64_performance_cycle.sw_performance_cycle |= pic_param->height << 16;
484
485 vp9_hw_regs->swreg1_int.sw_dec_e = 1;
486 vp9_hw_regs->swreg1_int.sw_dec_timeout_e = 1;
487
488 //last info update
489 hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;
490 for (i = 0 ; i < 4; i ++) {
491 hw_ctx->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i];
492 }
493
494 for (i = 0 ; i < 2; i ++) {
495 hw_ctx->ls_info.last_mode_deltas[i] = pic_param->mode_deltas[i];
496 }
497
498 for (i = 0; i < 8; i++) {
499 hw_ctx->ls_info.feature_data[i][0] = pic_param->stVP9Segments.feature_data[i][0];
500 hw_ctx->ls_info.feature_data[i][1] = pic_param->stVP9Segments.feature_data[i][1];
501 hw_ctx->ls_info.feature_data[i][2] = pic_param->stVP9Segments.feature_data[i][2];
502 hw_ctx->ls_info.feature_data[i][3] = pic_param->stVP9Segments.feature_data[i][3];
503 hw_ctx->ls_info.feature_mask[i] = pic_param->stVP9Segments.feature_mask[i];
504 }
505 if (!hw_ctx->ls_info.segmentation_enable_flag_last)
506 hw_ctx->ls_info.segmentation_enable_flag_last = pic_param->stVP9Segments.enabled;
507
508 hw_ctx->ls_info.last_show_frame = pic_param->show_frame;
509 hw_ctx->ls_info.last_width = pic_param->width;
510 hw_ctx->ls_info.last_height = pic_param->height;
511 hw_ctx->ls_info.last_intra_only = (!pic_param->frame_type || pic_param->intra_only);
512 hal_vp9d_dbg_par("stVP9Segments.enabled %d show_frame %d width %d height %d last_intra_only %d",
513 pic_param->stVP9Segments.enabled, pic_param->show_frame,
514 pic_param->width, pic_param->height,
515 hw_ctx->ls_info.last_intra_only);
516
517 // whether need update counts
518 if (pic_param->refresh_frame_context && !pic_param->parallelmode) {
519 task->dec.flags.wait_done = 1;
520 }
521
522 return MPP_OK;
523 }
524
hal_vp9d_rkv_start(void * hal,HalTaskInfo * task)525 MPP_RET hal_vp9d_rkv_start(void *hal, HalTaskInfo *task)
526 {
527 MPP_RET ret = MPP_OK;
528 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
529 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
530 VP9_REGS *hw_regs = (VP9_REGS *)hw_ctx->hw_regs;
531 MppDev dev = p_hal->dev;
532
533 if (p_hal->fast_mode) {
534 RK_S32 index = task->dec.reg_index;
535 hw_regs = (VP9_REGS *)hw_ctx->g_buf[index].hw_regs;
536 }
537
538 mpp_assert(hw_regs);
539
540 if (hal_vp9d_debug & HAL_VP9D_DBG_REG) {
541 RK_U32 *p = (RK_U32 *)hw_regs;
542 RK_U32 i = 0;
543
544 for (i = 0; i < sizeof(VP9_REGS) / 4; i++)
545 mpp_log("set regs[%02d]: %08X\n", i, *p++);
546 }
547
548 do {
549 MppDevRegWrCfg wr_cfg;
550 MppDevRegRdCfg rd_cfg;
551 RK_U32 reg_size = sizeof(VP9_REGS);
552
553 wr_cfg.reg = hw_ctx->hw_regs;
554 wr_cfg.size = reg_size;
555 wr_cfg.offset = 0;
556
557 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
558 if (ret) {
559 mpp_err_f("set register write failed %d\n", ret);
560 break;
561 }
562
563 rd_cfg.reg = hw_ctx->hw_regs;
564 rd_cfg.size = reg_size;
565 rd_cfg.offset = 0;
566
567 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
568 if (ret) {
569 mpp_err_f("set register read failed %d\n", ret);
570 break;
571 }
572
573 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
574 if (ret) {
575 mpp_err_f("send cmd failed %d\n", ret);
576 break;
577 }
578 } while (0);
579
580 (void)task;
581 return ret;
582 }
583
hal_vp9d_rkv_wait(void * hal,HalTaskInfo * task)584 MPP_RET hal_vp9d_rkv_wait(void *hal, HalTaskInfo *task)
585 {
586 MPP_RET ret = MPP_OK;
587 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
588 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
589 VP9_REGS *hw_regs = (VP9_REGS *)hw_ctx->hw_regs;
590
591 if (p_hal->fast_mode)
592 hw_regs = (VP9_REGS *)hw_ctx->g_buf[task->dec.reg_index].hw_regs;
593
594 mpp_assert(hw_regs);
595
596 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
597 if (ret)
598 mpp_err_f("poll cmd failed %d\n", ret);
599
600 if (hal_vp9d_debug & HAL_VP9D_DBG_REG) {
601 RK_U32 *p = (RK_U32 *)hw_regs;
602 RK_U32 i = 0;
603
604 for (i = 0; i < sizeof(VP9_REGS) / 4; i++)
605 mpp_log("get regs[%02d]: %08X\n", i, *p++);
606 }
607
608 if (task->dec.flags.parse_err ||
609 task->dec.flags.ref_err ||
610 !hw_regs->swreg1_int.sw_dec_rdy_sta) {
611 MppFrame mframe = NULL;
612 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
613 mpp_frame_set_errinfo(mframe, 1);
614 }
615
616 if (p_hal->dec_cb && task->dec.flags.wait_done) {
617 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
618
619 mpp_buffer_sync_ro_begin(hw_ctx->count_base);
620 hal_vp9d_update_counts(mpp_buffer_get_ptr(hw_ctx->count_base), task->dec.syntax.data);
621
622 mpp_callback(p_hal->dec_cb, &pic_param->counts);
623 }
624 if (p_hal->fast_mode) {
625 hw_ctx->g_buf[task->dec.reg_index].use_flag = 0;
626 }
627
628 (void)task;
629 return ret;
630 }
631
hal_vp9d_rkv_reset(void * hal)632 MPP_RET hal_vp9d_rkv_reset(void *hal)
633 {
634 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
635 Vp9dRkvCtx *hw_ctx = (Vp9dRkvCtx*)p_hal->hw_ctx;
636
637 hal_vp9d_enter();
638
639 memset(&hw_ctx->ls_info, 0, sizeof(hw_ctx->ls_info));
640 hw_ctx->mv_base_addr = -1;
641 hw_ctx->pre_mv_base_addr = -1;
642 hw_ctx->last_segid_flag = 1;
643
644 hal_vp9d_leave();
645
646 return MPP_OK;
647 }
648
hal_vp9d_rkv_flush(void * hal)649 MPP_RET hal_vp9d_rkv_flush(void *hal)
650 {
651 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
652 Vp9dRkvCtx *hw_ctx = p_hal->hw_ctx;
653
654 hal_vp9d_enter();
655
656 hw_ctx->mv_base_addr = -1;
657 hw_ctx->pre_mv_base_addr = -1;
658
659 hal_vp9d_leave();
660
661 return MPP_OK;
662 }
663
hal_vp9d_rkv_control(void * hal,MpiCmd cmd_type,void * param)664 MPP_RET hal_vp9d_rkv_control(void *hal, MpiCmd cmd_type, void *param)
665 {
666 switch ((MpiCmd)cmd_type) {
667 case MPP_DEC_SET_FRAME_INFO: {
668 /* commit buffer stride */
669 RK_U32 width = mpp_frame_get_width((MppFrame)param);
670 RK_U32 height = mpp_frame_get_height((MppFrame)param);
671
672 mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
673 mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
674 } break;
675 default: {
676 } break;
677 }
678 (void)hal;
679
680 return MPP_OK;
681 }
682
683 const MppHalApi hal_vp9d_rkv = {
684 .name = "vp9d_rkdec",
685 .type = MPP_CTX_DEC,
686 .coding = MPP_VIDEO_CodingVP9,
687 .ctx_size = sizeof(HalVp9dCtx),
688 .flag = 0,
689 .init = hal_vp9d_rkv_init,
690 .deinit = hal_vp9d_rkv_deinit,
691 .reg_gen = hal_vp9d_rkv_gen_regs,
692 .start = hal_vp9d_rkv_start,
693 .wait = hal_vp9d_rkv_wait,
694 .reset = hal_vp9d_rkv_reset,
695 .flush = hal_vp9d_rkv_flush,
696 .control = hal_vp9d_rkv_control,
697 };
698