Lines Matching refs:hw_regs
48 reg_ctx->g_buf[i].hw_regs = in hal_h265d_alloc_res()
73 reg_ctx->hw_regs = mpp_calloc_size(void, sizeof(H265d_REGS_t)); in hal_h265d_alloc_res()
127 if (reg_ctx->g_buf[i].hw_regs) { in hal_h265d_release_res()
128 mpp_free(reg_ctx->g_buf[i].hw_regs); in hal_h265d_release_res()
129 reg_ctx->g_buf[i].hw_regs = NULL; in hal_h265d_release_res()
156 if (reg_ctx->hw_regs) { in hal_h265d_release_res()
157 mpp_free(reg_ctx->hw_regs); in hal_h265d_release_res()
158 reg_ctx->hw_regs = NULL; in hal_h265d_release_res()
731 H265d_REGS_t *hw_regs; in hal_h265d_rkv_gen_regs() local
760 reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs; in hal_h265d_rkv_gen_regs()
792 if (NULL == reg_ctx->hw_regs) { in hal_h265d_rkv_gen_regs()
796 hw_regs = (H265d_REGS_t*)reg_ctx->hw_regs; in hal_h265d_rkv_gen_regs()
797 memset(hw_regs, 0, sizeof(H265d_REGS_t)); in hal_h265d_rkv_gen_regs()
806 hw_regs->sw_picparameter.sw_slice_num = dxva_cxt->slice_count; in hal_h265d_rkv_gen_regs()
807 hw_regs->sw_picparameter.sw_y_hor_virstride = stride_y >> 4; in hal_h265d_rkv_gen_regs()
808 hw_regs->sw_picparameter.sw_uv_hor_virstride = stride_uv >> 4; in hal_h265d_rkv_gen_regs()
809 hw_regs->sw_y_virstride = virstrid_y >> 4; in hal_h265d_rkv_gen_regs()
810 hw_regs->sw_yuv_virstride = virstrid_yuv >> 4; in hal_h265d_rkv_gen_regs()
811 hw_regs->sw_sysctrl.sw_h26x_rps_mode = 0; in hal_h265d_rkv_gen_regs()
814 hw_regs->sw_decout_base = mpp_buffer_get_fd(framebuf); //just index need map in hal_h265d_rkv_gen_regs()
819 if (hw_regs->sw_decout_base == 0) { in hal_h265d_rkv_gen_regs()
823 hw_regs->sw_cur_poc = dxva_cxt->pp.CurrPicOrderCntVal; in hal_h265d_rkv_gen_regs()
833 hw_regs->sw_sysctrl.sw_wait_reset_en = 1; in hal_h265d_rkv_gen_regs()
834 hw_regs->v345_reg_ends.reg064_mvc0.refp_layer_same_with_cur = 0xffff; in hal_h265d_rkv_gen_regs()
837 hw_regs->sw_sysctrl.sw_h26x_rps_mode = 1; in hal_h265d_rkv_gen_regs()
849 hw_regs->sw_cabactbl_base = mpp_buffer_get_fd(reg_ctx->cabac_table_data); in hal_h265d_rkv_gen_regs()
850 hw_regs->sw_pps_base = mpp_buffer_get_fd(reg_ctx->pps_data); in hal_h265d_rkv_gen_regs()
851 hw_regs->sw_rps_base = mpp_buffer_get_fd(reg_ctx->rps_data); in hal_h265d_rkv_gen_regs()
852 hw_regs->sw_strm_rlc_base = mpp_buffer_get_fd(streambuf); in hal_h265d_rkv_gen_regs()
855 hw_regs->sw_stream_len = ((dxva_cxt->bitstream_size + 15) in hal_h265d_rkv_gen_regs()
857 hw_regs->sw_stream_len = stream_buf_size > hw_regs->sw_stream_len ? in hal_h265d_rkv_gen_regs()
858 hw_regs->sw_stream_len : stream_buf_size; in hal_h265d_rkv_gen_regs()
860 aglin_offset = hw_regs->sw_stream_len - dxva_cxt->bitstream_size; in hal_h265d_rkv_gen_regs()
865 hw_regs->sw_interrupt.sw_dec_e = 1; in hal_h265d_rkv_gen_regs()
866 hw_regs->sw_interrupt.sw_dec_timeout_e = 1; in hal_h265d_rkv_gen_regs()
867 hw_regs->sw_interrupt.sw_wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_rkv_gen_regs()
871 hw_regs->cabac_error_en = 0xfdfffffd; in hal_h265d_rkv_gen_regs()
872 hw_regs->rkv_reg_ends.extern_error_en = 0x30000000; in hal_h265d_rkv_gen_regs()
874 valid_ref = hw_regs->sw_decout_base; in hal_h265d_rkv_gen_regs()
878 hw_regs->sw_refer_poc[i] = dxva_cxt->pp.PicOrderCntValList[i]; in hal_h265d_rkv_gen_regs()
883 hw_regs->sw_refer_base[i] = mpp_buffer_get_fd(framebuf); in hal_h265d_rkv_gen_regs()
884 valid_ref = hw_regs->sw_refer_base[i]; in hal_h265d_rkv_gen_regs()
886 hw_regs->sw_refer_base[i] = valid_ref; in hal_h265d_rkv_gen_regs()
890 hw_regs->sw_refer_base[i] = hw_regs->sw_decout_base; in hal_h265d_rkv_gen_regs()
910 H265d_REGS_t *hw_regs = NULL; in hal_h265d_rkv_start() local
923 hw_regs = ( H265d_REGS_t *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_rkv_start()
925 hw_regs = ( H265d_REGS_t *)reg_ctx->hw_regs; in hal_h265d_rkv_start()
928 if (hw_regs == NULL) { in hal_h265d_rkv_start()
943 wr_cfg.reg = hw_regs; in hal_h265d_rkv_start()
949 … h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n", i, ((RK_U32 *)hw_regs)[i]); in hal_h265d_rkv_start()
958 rd_cfg.reg = hw_regs; in hal_h265d_rkv_start()
983 H265d_REGS_t *hw_regs = NULL; in hal_h265d_rkv_wait() local
987 hw_regs = ( H265d_REGS_t *)reg_ctx->g_buf[index].hw_regs; in hal_h265d_rkv_wait()
989 hw_regs = ( H265d_REGS_t *)reg_ctx->hw_regs; in hal_h265d_rkv_wait()
1005 hw_regs->sw_interrupt.sw_dec_error_sta || in hal_h265d_rkv_wait()
1006 hw_regs->sw_interrupt.sw_dec_timeout_sta || in hal_h265d_rkv_wait()
1007 hw_regs->sw_interrupt.sw_dec_empty_sta) { in hal_h265d_rkv_wait()
1043 …"RK_HEVC_DEC: regs[1]=0x%08X, regs[45]=0x%08x\n", ((RK_U32 *)hw_regs)[1], ((RK_U32 *)hw_regs)[45]); in hal_h265d_rkv_wait()