1*437bfbebSnyanmisaka /* 2*437bfbebSnyanmisaka * Copyright 2020 Rockchip Electronics Co. LTD 3*437bfbebSnyanmisaka * 4*437bfbebSnyanmisaka * Licensed under the Apache License, Version 2.0 (the "License"); 5*437bfbebSnyanmisaka * you may not use this file except in compliance with the License. 6*437bfbebSnyanmisaka * You may obtain a copy of the License at 7*437bfbebSnyanmisaka * 8*437bfbebSnyanmisaka * http://www.apache.org/licenses/LICENSE-2.0 9*437bfbebSnyanmisaka * 10*437bfbebSnyanmisaka * Unless required by applicable law or agreed to in writing, software 11*437bfbebSnyanmisaka * distributed under the License is distributed on an "AS IS" BASIS, 12*437bfbebSnyanmisaka * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*437bfbebSnyanmisaka * See the License for the specific language governing permissions and 14*437bfbebSnyanmisaka * limitations under the License. 15*437bfbebSnyanmisaka */ 16*437bfbebSnyanmisaka 17*437bfbebSnyanmisaka #ifndef __HAL_VP9D_CTX_H__ 18*437bfbebSnyanmisaka #define __HAL_VP9D_CTX_H__ 19*437bfbebSnyanmisaka 20*437bfbebSnyanmisaka #include "mpp_device.h" 21*437bfbebSnyanmisaka #include "mpp_hal.h" 22*437bfbebSnyanmisaka #include "hal_bufs.h" 23*437bfbebSnyanmisaka 24*437bfbebSnyanmisaka #define MAX_GEN_REG 3 25*437bfbebSnyanmisaka 26*437bfbebSnyanmisaka typedef struct Vp9dLastInfo_t { 27*437bfbebSnyanmisaka RK_S32 abs_delta_last; 28*437bfbebSnyanmisaka RK_S8 last_ref_deltas[4]; 29*437bfbebSnyanmisaka RK_S8 last_mode_deltas[2]; 30*437bfbebSnyanmisaka RK_U8 segmentation_enable_flag_last; 31*437bfbebSnyanmisaka RK_U8 last_show_frame; 32*437bfbebSnyanmisaka RK_U8 last_intra_only; 33*437bfbebSnyanmisaka RK_U32 last_width; 34*437bfbebSnyanmisaka RK_U32 last_height; 35*437bfbebSnyanmisaka RK_S16 feature_data[8][4]; 36*437bfbebSnyanmisaka RK_U8 feature_mask[8]; 37*437bfbebSnyanmisaka RK_U8 color_space_last; 38*437bfbebSnyanmisaka RK_U8 last_frame_type; 39*437bfbebSnyanmisaka } Vp9dLastInfo; 40*437bfbebSnyanmisaka 41*437bfbebSnyanmisaka typedef struct Vp9dRegBuf_t { 42*437bfbebSnyanmisaka RK_S32 use_flag; 43*437bfbebSnyanmisaka MppBuffer global_base; 44*437bfbebSnyanmisaka MppBuffer probe_base; 45*437bfbebSnyanmisaka MppBuffer count_base; 46*437bfbebSnyanmisaka MppBuffer segid_cur_base; 47*437bfbebSnyanmisaka MppBuffer segid_last_base; 48*437bfbebSnyanmisaka void *hw_regs; 49*437bfbebSnyanmisaka MppBuffer rcb_buf; 50*437bfbebSnyanmisaka } Vp9dRegBuf; 51*437bfbebSnyanmisaka 52*437bfbebSnyanmisaka typedef struct HalVp9dCtx_t { 53*437bfbebSnyanmisaka /* for hal api call back */ 54*437bfbebSnyanmisaka const MppHalApi *api; 55*437bfbebSnyanmisaka 56*437bfbebSnyanmisaka /* for hardware info */ 57*437bfbebSnyanmisaka MppClientType client_type; 58*437bfbebSnyanmisaka RK_U32 hw_id; 59*437bfbebSnyanmisaka MppDev dev; 60*437bfbebSnyanmisaka 61*437bfbebSnyanmisaka MppBufSlots slots; 62*437bfbebSnyanmisaka MppBufSlots packet_slots; 63*437bfbebSnyanmisaka MppBufferGroup group; 64*437bfbebSnyanmisaka MppCbCtx *dec_cb; 65*437bfbebSnyanmisaka RK_U32 fast_mode; 66*437bfbebSnyanmisaka void* hw_ctx; 67*437bfbebSnyanmisaka 68*437bfbebSnyanmisaka const MppDecHwCap *hw_info; 69*437bfbebSnyanmisaka } HalVp9dCtx; 70*437bfbebSnyanmisaka 71*437bfbebSnyanmisaka #endif /*__HAL_VP9D_CTX_H__*/ 72