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Searched refs:pirq (Results 1 – 24 of 24) sorted by relevance

/rk3399_rockchip-uboot/arch/x86/lib/
H A Dpirq_routing.c14 static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, in pirq_get_next_free_irq() argument
56 unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; in pirq_route_irqs() local
60 memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); in pirq_route_irqs()
86 if (!pirq[link]) { in pirq_route_irqs()
87 irq = pirq_get_next_free_irq(dev, pirq, bitmap, in pirq_route_irqs()
89 pirq[link] = irq; in pirq_route_irqs()
91 irq = pirq[link]; in pirq_route_irqs()
108 debug("PIRQ%c: %d\n", 'A' + i, pirq[i]); in pirq_route_irqs()
H A Dmpspec.c283 __weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) in mp_determine_pci_dstirq() argument
286 return pirq + 16; in mp_determine_pci_dstirq()
326 pr.pirq = fdt_addr_to_cpu(cell[2]); in mptable_add_intsrc()
339 dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); in mptable_add_intsrc()
/rk3399_rockchip-uboot/arch/x86/cpu/
H A Dirq.c23 u8 pirq; in pirq_check_irq_routed() local
27 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); in pirq_check_irq_routed()
29 pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base)); in pirq_check_irq_routed()
31 pirq &= 0xf; in pirq_check_irq_routed()
34 if (pirq < 3 || pirq == 8 || pirq == 13) in pirq_check_irq_routed()
37 return pirq == irq ? true : false; in pirq_check_irq_routed()
78 int bus, int device, int pin, int pirq) in fill_irq_info() argument
82 slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); in fill_irq_info()
179 pr.pirq = fdt_addr_to_cpu(cell[2]); in create_pirq_routing_table()
184 'A' + pr.pirq); in create_pirq_routing_table()
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A Dintel,irq-router.txt11 - intel,pirq-config : Specifies the IRQ routing register programming mechanism.
16 configuration space, required only if intel,pirq-config = "ibase".
22 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
25 - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
27 - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
42 intel,pirq-config = "pci";
43 intel,pirq-link = <0x60 8>;
44 intel,pirq-mask = <0xdef8>;
45 intel,pirq-routing = <
H A Dintel-lpc.txt20 - intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
51 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-generic.c383 int pirq; in do_dump_irqs() local
388 for (pirq = 0; pirq < PLATFORM_MAX_IRQ; pirq++) { in do_dump_irqs()
389 if (!irq_desc[pirq].handle_irq) in do_dump_irqs()
392 dev = (struct udevice *)irq_desc[pirq].data; in do_dump_irqs()
399 pirq, irq_desc[pirq].flag & IRQ_FLG_ENABLE ? 1 : 0, in do_dump_irqs()
400 (ulong)irq_desc[pirq].handle_irq, in do_dump_irqs()
401 drv_name, dev->name, irq_desc[pirq].count); in do_dump_irqs()
403 virqs_show(pirq); in do_dump_irqs()
H A Dvirq.c40 int pirq; /* parent irq */ member
73 if (parent_irq == desc->pirq) in find_virq_desc_by_pirq()
106 void virqs_show(int pirq) in virqs_show() argument
114 desc = find_virq_desc_by_pirq(pirq); in virqs_show()
185 void virq_chip_generic_handler(int pirq, void *pdata) in virq_chip_generic_handler() argument
197 desc = find_virq_desc_by_pirq(pirq); in virq_chip_generic_handler()
275 desc->pirq = irq; in virq_add_chip()
381 irq_handler_enable(desc->pirq); in virq_enable()
402 irq_handler_disable(desc->pirq); in virq_disable()
H A Dirq-internal.h39 void virqs_show(int pirq);
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dqemu-x86_i440fx.dts64 intel,pirq-config = "pci";
65 intel,pirq-link = <0x60 4>;
66 intel,pirq-mask = <0x0e40>;
67 intel,pirq-routing = <
H A Dqemu-x86_q35.dts75 intel,pirq-config = "pci";
78 intel,pirq-link = <0x60 8>;
79 intel,pirq-mask = <0x0e40>;
80 intel,pirq-routing = <
H A Dgalileo.dts102 intel,pirq-config = "pci";
104 intel,pirq-link = <0x60 8>;
105 intel,pirq-mask = <0xdef8>;
106 intel,pirq-routing = <
H A Dcrownbay.dts156 intel,pirq-config = "pci";
158 intel,pirq-link = <0x60 8>;
159 intel,pirq-mask = <0xcee0>;
160 intel,pirq-routing = <
H A Dbaytrail_som-db5800-som-6867.dts130 intel,pirq-config = "ibase";
133 intel,pirq-link = <8 8>;
134 intel,pirq-mask = <0xdee0>;
135 intel,pirq-routing = <
H A Dbayleybay.dts107 intel,pirq-config = "ibase";
110 intel,pirq-link = <8 8>;
111 intel,pirq-mask = <0xdee0>;
112 intel,pirq-routing = <
H A Dconga-qeval20-qa3-e3845.dts117 intel,pirq-config = "ibase";
120 intel,pirq-link = <8 8>;
121 intel,pirq-mask = <0xdee0>;
122 intel,pirq-routing = <
H A Ddfi-bt700.dtsi128 intel,pirq-config = "ibase";
131 intel,pirq-link = <8 8>;
132 intel,pirq-mask = <0xdee0>;
133 intel,pirq-routing = <
H A Dminnowmax.dts131 intel,pirq-config = "ibase";
134 intel,pirq-link = <8 8>;
135 intel,pirq-mask = <0xdee0>;
136 intel,pirq-routing = <
H A Dchromebook_samus.dts128 gpio_pirq: gpio-pirq {
132 pirq-apic = <PIRQ_APIC_ROUTE>;
520 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
H A Dchromebook_link.dts391 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
/rk3399_rockchip-uboot/arch/x86/cpu/qemu/
H A Dqemu.c178 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) in mp_determine_pci_dstirq() argument
195 irq = pirq < 8 ? pirq + 16 : pirq + 12; in mp_determine_pci_dstirq()
/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dirq.h53 int pirq; member
H A Dmpspec.h449 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq);
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dintel,x86-broadwell-pinctrl.txt28 - pirq-apic - the pin will be routed to the IOxAPIC
103 gpio_pirq: gpio-pirq {
107 pirq-apic = <PIRQ_APIC_ROUTE>;
/rk3399_rockchip-uboot/doc/
H A DREADME.x86952 Here we have more details on the intel,pirq-routing property below.
954 intel,pirq-routing = <