Merge git://git.denx.de/u-boot-x86

x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer

At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros

x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer

At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: baytrail: Use macros instead of magic numbers for FSP settings

Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.

Signed-off-by: Bin Men

x86: baytrail: Use macros instead of magic numbers for FSP settings

Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: baytrail: Remove "serial-debug-port-*" settings

"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.

Signed-off-b

x86: baytrail: Remove "serial-debug-port-*" settings

"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: baytrail: Change "fsp, mrc-init-tseg-size" default value to 1

The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
FSP default settings. 0 is not valid.

Signed-off-by: Bin Meng

x86: baytrail: Change "fsp, mrc-init-tseg-size" default value to 1

The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
FSP default settings. 0 is not valid.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This

x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
"Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: som-db5800-som-6867: fix SERIRQ on reset

Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.

Pad configuration for SERIRQ is not set to enable the SERIRQ function
after

x86: som-db5800-som-6867: fix SERIRQ on reset

Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.

Pad configuration for SERIRQ is not set to enable the SERIRQ function
after a reset though strangely, it is on initial boot.

Rebooting from Linux, reset command in u-boot and even pushing the reset
button on the development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: Add Advantech SOM-DB5800/SOM-6867 support

Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier

x86: Add Advantech SOM-DB5800/SOM-6867 support

Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio
Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
HDA_SDI0 is set in DT to enable HD Audio codec.
Pin defaults for codec pin complexs are not changed.

Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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