19c7dea60SBin Meng /* 29c7dea60SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 39c7dea60SBin Meng * 49c7dea60SBin Meng * SPDX-License-Identifier: GPL-2.0+ 59c7dea60SBin Meng */ 69c7dea60SBin Meng 79c7dea60SBin Meng #ifndef _ARCH_IRQ_H_ 89c7dea60SBin Meng #define _ARCH_IRQ_H_ 99c7dea60SBin Meng 109c7dea60SBin Meng #include <dt-bindings/interrupt-router/intel-irq.h> 119c7dea60SBin Meng 129c7dea60SBin Meng /** 139c7dea60SBin Meng * Intel interrupt router configuration mechanism 149c7dea60SBin Meng * 159c7dea60SBin Meng * There are two known ways of Intel interrupt router configuration mechanism 169c7dea60SBin Meng * so far. On most cases, the IRQ routing configuraiton is controlled by PCI 179c7dea60SBin Meng * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). 189c7dea60SBin Meng * On some newer platforms like BayTrail and Braswell, the IRQ routing is now 199c7dea60SBin Meng * in the IBASE register block where IBASE is memory-mapped. 209c7dea60SBin Meng */ 219c7dea60SBin Meng enum pirq_config { 229c7dea60SBin Meng PIRQ_VIA_PCI, 239c7dea60SBin Meng PIRQ_VIA_IBASE 249c7dea60SBin Meng }; 259c7dea60SBin Meng 269c7dea60SBin Meng /** 279c7dea60SBin Meng * Intel interrupt router control block 289c7dea60SBin Meng * 299c7dea60SBin Meng * Its members' value will be filled in based on device tree's input. 309c7dea60SBin Meng * 319c7dea60SBin Meng * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE 329c7dea60SBin Meng * @link_base: link value base number 339c7dea60SBin Meng * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means 349c7dea60SBin Meng * IRQ N is available to be routed 359c7dea60SBin Meng * @lb_bdf: irq router's PCI bus/device/function number encoding 369c7dea60SBin Meng * @ibase: IBASE register block base address 37*d4e61f50SBin Meng * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) 38*d4e61f50SBin Meng * @actl_addr: ACTL register offset 399c7dea60SBin Meng */ 409c7dea60SBin Meng struct irq_router { 419c7dea60SBin Meng int config; 429c7dea60SBin Meng u32 link_base; 439c7dea60SBin Meng u16 irq_mask; 449c7dea60SBin Meng u32 bdf; 459c7dea60SBin Meng u32 ibase; 46*d4e61f50SBin Meng bool actl_8bit; 47*d4e61f50SBin Meng int actl_addr; 489c7dea60SBin Meng }; 499c7dea60SBin Meng 509c7dea60SBin Meng struct pirq_routing { 519c7dea60SBin Meng int bdf; 529c7dea60SBin Meng int pin; 539c7dea60SBin Meng int pirq; 549c7dea60SBin Meng }; 559c7dea60SBin Meng 569c7dea60SBin Meng /* PIRQ link number and value conversion */ 579c7dea60SBin Meng #define LINK_V2N(link, base) (link - base) 589c7dea60SBin Meng #define LINK_N2V(link, base) (link + base) 599c7dea60SBin Meng 609c7dea60SBin Meng #define PIRQ_BITMAP 0xdef8 619c7dea60SBin Meng 629c7dea60SBin Meng /** 63d3b884b2SSimon Glass * irq_router_common_init() - Perform common x86 interrupt init 64d3b884b2SSimon Glass * 65d3b884b2SSimon Glass * This creates the PIRQ routing table and routes the IRQs 66d3b884b2SSimon Glass */ 67d3b884b2SSimon Glass int irq_router_common_init(struct udevice *dev); 68d3b884b2SSimon Glass 699c7dea60SBin Meng #endif /* _ARCH_IRQ_H_ */ 70