12b605154SSimon GlassIntel LPC Device Binding 22b605154SSimon Glass======================== 32b605154SSimon Glass 42b605154SSimon GlassThe device tree node which describes the operation of the Intel Low Pin 52b605154SSimon GlassCount device is as follows: 62b605154SSimon Glass 72b605154SSimon GlassRequired properties : 82b605154SSimon Glass- compatible = "intel,lpc" 9*72cd085aSSimon Glass- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the 10*72cd085aSSimon Glass ALT_GP_SMI_EN register 11*72cd085aSSimon Glass- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four 12*72cd085aSSimon Glass cell pairs can be provided - the first of each pair is the base address and 132b605154SSimon Glass the second is the size. These are written into the GENx_DEC registers of 142b605154SSimon Glass the LPC device 15*72cd085aSSimon Glass- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid 16*72cd085aSSimon Glass values are: 17*72cd085aSSimon Glass 0 No effect (default) 18*72cd085aSSimon Glass 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 19*72cd085aSSimon Glass 2 SCI (if corresponding GPIO_EN bit is also set) 20*72cd085aSSimon Glass- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H, 21*72cd085aSSimon Glass one cell for each. 22*72cd085aSSimon Glass 0x00 - 0000 = Reserved 23*72cd085aSSimon Glass 0x01 - 0001 = Reserved 24*72cd085aSSimon Glass 0x02 - 0010 = Reserved 25*72cd085aSSimon Glass 0x03 - 0011 = IRQ3 26*72cd085aSSimon Glass 0x04 - 0100 = IRQ4 27*72cd085aSSimon Glass 0x05 - 0101 = IRQ5 28*72cd085aSSimon Glass 0x06 - 0110 = IRQ6 29*72cd085aSSimon Glass 0x07 - 0111 = IRQ7 30*72cd085aSSimon Glass 0x08 - 1000 = Reserved 31*72cd085aSSimon Glass 0x09 - 1001 = IRQ9 32*72cd085aSSimon Glass 0x0A - 1010 = IRQ10 33*72cd085aSSimon Glass 0x0B - 1011 = IRQ11 34*72cd085aSSimon Glass 0x0C - 1100 = IRQ12 35*72cd085aSSimon Glass 0x0D - 1101 = Reserved 36*72cd085aSSimon Glass 0x0E - 1110 = IRQ14 37*72cd085aSSimon Glass 0x0F - 1111 = IRQ15 38*72cd085aSSimon Glass PIRQ[n]_ROUT[7] - PIRQ Routing Control 39*72cd085aSSimon Glass 0x80 - The PIRQ is not routed. 402b605154SSimon Glass 412b605154SSimon Glass 422b605154SSimon GlassExample 432b605154SSimon Glass------- 442b605154SSimon Glass 452b605154SSimon Glasslpc { 462b605154SSimon Glass compatible = "intel,lpc"; 472b605154SSimon Glass #address-cells = <1>; 482b605154SSimon Glass #size-cells = <1>; 49*72cd085aSSimon Glass intel,gen-dec = <0x800 0xfc 0x900 0xfc>; 50*72cd085aSSimon Glass 51*72cd085aSSimon Glass intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 52*72cd085aSSimon Glass 0x80 0x80 0x80 0x80>; 53*72cd085aSSimon Glass /* 54*72cd085aSSimon Glass * GPI routing 55*72cd085aSSimon Glass * 0 No effect (default) 56*72cd085aSSimon Glass * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is 57*72cd085aSSimon Glass * also set) 58*72cd085aSSimon Glass * 2 SCI (if corresponding GPIO_EN bit is also set) 59*72cd085aSSimon Glass */ 60*72cd085aSSimon Glass intel,gpi-routing = <0 0 0 0 0 0 0 2 61*72cd085aSSimon Glass 1 0 0 0 0 0 0 0>; 62*72cd085aSSimon Glass /* Enable EC SMI source */ 63*72cd085aSSimon Glass intel,alt-gp-smi-enable = <0x0100>; 642b605154SSimon Glass}; 65