15910955fSBin MengIntel Interrupt Router Device Binding 25910955fSBin Meng===================================== 35910955fSBin Meng 45910955fSBin MengThe device tree node which describes the operation of the Intel Interrupt Router 55910955fSBin Mengdevice is as follows: 65910955fSBin Meng 75910955fSBin MengRequired properties : 85910955fSBin Meng- reg : Specifies the interrupt router's PCI configuration space address as 95910955fSBin Meng defined by the Open Firmware spec. 105910955fSBin Meng- compatible = "intel,irq-router" 115910955fSBin Meng- intel,pirq-config : Specifies the IRQ routing register programming mechanism. 125910955fSBin Meng Valid values are: 135910955fSBin Meng "pci": IRQ routing is controlled by PCI configuration registers 145910955fSBin Meng "ibase": IRQ routing is in the memory-mapped IBASE register block 155910955fSBin Meng- intel,ibase-offset : IBASE register offset in the interrupt router's PCI 165910955fSBin Meng configuration space, required only if intel,pirq-config = "ibase". 17*d4e61f50SBin Meng- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must 18*d4e61f50SBin Meng be specified. The 8-bit ACTL register is seen on ICH series chipset, like 19*d4e61f50SBin Meng ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. 20*d4e61f50SBin Meng- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either 21*d4e61f50SBin Meng in the interrupt router's PCI configuration space, or IBASE. 225910955fSBin Meng- intel,pirq-link : Specifies the PIRQ link information with two cells. The 235910955fSBin Meng first cell is the register offset that controls the first PIRQ link routing. 245910955fSBin Meng The second cell is the total number of PIRQ links the router supports. 257fd078cbSSimon Glass- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the 267fd078cbSSimon Glass 8259 PIC. Bit N is 1 means IRQ N is available to be routed. 275910955fSBin Meng- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, 285910955fSBin Meng encoded as 3 cells a group for a device. The first cell is the device's PCI 295910955fSBin Meng bus number, device number and function number encoding with PCI_BDF() macro. 305910955fSBin Meng The second cell is the PCI interrupt pin used by this device. The last cell 315910955fSBin Meng is which PIRQ line the PCI interrupt pin is routed to. 325910955fSBin Meng 335910955fSBin Meng 345910955fSBin MengExample 355910955fSBin Meng------- 365910955fSBin Meng 375910955fSBin Meng#include <dt-bindings/interrupt-router/intel-irq.h> 385910955fSBin Meng 395910955fSBin Meng irq-router@1f,0 { 405910955fSBin Meng reg = <0x0000f800 0 0 0 0>; 415910955fSBin Meng compatible = "intel,irq-router"; 425910955fSBin Meng intel,pirq-config = "pci"; 435910955fSBin Meng intel,pirq-link = <0x60 8>; 445910955fSBin Meng intel,pirq-mask = <0xdef8>; 455910955fSBin Meng intel,pirq-routing = < 465910955fSBin Meng PCI_BDF(0, 2, 0) INTA PIRQA 475910955fSBin Meng PCI_BDF(0, 3, 0) INTA PIRQB 485910955fSBin Meng PCI_BDF(0, 8, 0) INTA PIRQC 495910955fSBin Meng PCI_BDF(0, 8, 1) INTB PIRQD 505910955fSBin Meng PCI_BDF(1, 6, 0) INTA PIRQE 515910955fSBin Meng PCI_BDF(1, 6, 1) INTB PIRQF 525910955fSBin Meng PCI_BDF(1, 6, 2) INTC PIRQG 535910955fSBin Meng PCI_BDF(1, 6, 3) INTD PIRQH 545910955fSBin Meng >; 555910955fSBin Meng }; 56