x86: link: Set up device tree for SPL

Add the correct pre-relocation tag so that the required device tree nodes
are present in the SPL device tree.

On x86 it doesn't make a lot of sense to have a s

x86: link: Set up device tree for SPL

Add the correct pre-relocation tag so that the required device tree nodes
are present in the SPL device tree.

On x86 it doesn't make a lot of sense to have a separate SPL device tree.
Since everything is in the same ROM we might as well just use the main
device tree in both SPL and U-Boot proper. But we haven't implemented that,
so this is a good first step.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: coreboot: Convert to use DM coreboot video driver

This converts coreboot to use DM framebuffer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

x86: dts: Drop memory SPD compatible string

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin

x86: dts: Drop memory SPD compatible string

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: link: Add pin configuration to the device tree

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add

x86: link: Add pin configuration to the device tree

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: dts: link: Add board ID GPIOs

At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.or

x86: dts: link: Add board ID GPIOs

At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: dts: link: Move SPD info into the memory controller

The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to

x86: dts: link: Move SPD info into the memory controller

The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: link: Add required GPIO properties

In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass <sjg@chro

x86: link: Add required GPIO properties

In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ich6_gpio: Convert to use proper DM API

At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While

x86: ich6_gpio: Convert to use proper DM API

At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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spi: ich: Use compatible strings to distinguish controller version

At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatib

spi: ich: Use compatible strings to distinguish controller version

At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: Correct spi node alias

With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.

Signed-off-by: Bin Meng <bmeng.cn@gm

x86: Correct spi node alias

With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: ivybridge: Use syscon for the GMA device

Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to

x86: ivybridge: Use syscon for the GMA device

Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Drop special EHCI init

This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also dr

x86: ivybridge: Drop special EHCI init

This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Convert SDRAM init to use driver model

SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all

x86: ivybridge: Convert SDRAM init to use driver model

SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all
of this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Use the I2C driver to perform SMbus init

Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by:

x86: ivybridge: Use the I2C driver to perform SMbus init

Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Drop the special PCI driver

There is nothing special about the ivybridge pci driver now, so just use
the generic one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin

x86: ivybridge: Drop the special PCI driver

There is nothing special about the ivybridge pci driver now, so just use
the generic one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Do the SATA init before relocation

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relo

x86: ivybridge: Do the SATA init before relocation

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Use common CPU init code

The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs

x86: ivybridge: Use common CPU init code

The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Add a driver for the bd82x6x northbridge

Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Re

x86: ivybridge: Add a driver for the bd82x6x northbridge

Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Move lpc_early_init() to probe()

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass

x86: ivybridge: Move lpc_early_init() to probe()

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Set up the LPC device using driver model

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent

x86: ivybridge: Set up the LPC device using driver model

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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dm: x86: spi: Convert ICH SPI driver to driver model PCI API

At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver

dm: x86: spi: Convert ICH SPI driver to driver model PCI API

At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Convert to use driver model timer

Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Add an i8042 device for boards that have it

Some boards have an i8042 device. Enable the driver for all x86 boards, and
add a device tree node for those which may have this keyboard.

Also adju

x86: Add an i8042 device for boards that have it

Some boards have an i8042 device. Enable the driver for all x86 boards, and
add a device tree node for those which may have this keyboard.

Also adjust the configuration so that i8042 is always separate from the VGA,
and rename the stdin driver accordingly. With this commit the keyboard will
not work, but it is fixed in the next commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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