1cf344252SJoseph Chen /* 2cf344252SJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3cf344252SJoseph Chen * 4cf344252SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5cf344252SJoseph Chen */ 6cf344252SJoseph Chen 7cf344252SJoseph Chen #ifndef _IRQ_GIC_H_ 8cf344252SJoseph Chen #define _IRQ_GIC_H_ 9cf344252SJoseph Chen 10cf344252SJoseph Chen #include <asm/io.h> 11cf344252SJoseph Chen #include <irq-generic.h> 12cf344252SJoseph Chen #include <irq-platform.h> 13cf344252SJoseph Chen #include "irq-internal.h" 14cf344252SJoseph Chen 15cf344252SJoseph Chen /* 16ae63f119SJoseph Chen * IRQ FLAG 17ae63f119SJoseph Chen */ 18ae63f119SJoseph Chen #define IRQ_FLG_ENABLE BIT(0) 19ae63f119SJoseph Chen 20ae63f119SJoseph Chen /* 21cf344252SJoseph Chen * IRQ-NUMBERS 22cf344252SJoseph Chen */ 232c4e90c1SJoseph Chen #define PLATFORM_SUSPEND_MAX_IRQ 12 24cf344252SJoseph Chen #define PLATFORM_GIC_MAX_IRQ (GIC_IRQS_NR) 25cf344252SJoseph Chen #define PLATFORM_GPIO_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR) 26cf344252SJoseph Chen #define PLATFORM_MAX_IRQ (GIC_IRQS_NR + GPIO_IRQS_NR) 27cf344252SJoseph Chen 28cf344252SJoseph Chen /* 29cf344252SJoseph Chen * IRQ-CHIP 30cf344252SJoseph Chen */ 31cf344252SJoseph Chen struct irq_chip *arch_gic_get_irqchip(void); 32cf344252SJoseph Chen struct irq_chip *arch_gpio_get_irqchip(void); 3341766119SJoseph Chen struct irq_chip *arch_virq_get_irqchip(void); 3441766119SJoseph Chen 3541766119SJoseph Chen /* 3641766119SJoseph Chen * IRQ-VIRTUAL 3741766119SJoseph Chen */ 3841766119SJoseph Chen int bad_virq(int irq); 39*92f4f090SJoseph Chen void virqs_show(int pirq); 4041766119SJoseph Chen void virq_free_handler(int irq); 4141766119SJoseph Chen int virq_install_handler(int irq, interrupt_handler_t *handler, void *data); 42cf344252SJoseph Chen 43cf344252SJoseph Chen /* 44cf344252SJoseph Chen * Other 45cf344252SJoseph Chen */ 46cf344252SJoseph Chen int bad_irq(int irq); 47cf344252SJoseph Chen 48cf344252SJoseph Chen /* 49cf344252SJoseph Chen * IRQ-GPIO-SWITCH 50cf344252SJoseph Chen */ 51cf344252SJoseph Chen #define GPIO_BANK_MASK 0xFFFFFF00 52cf344252SJoseph Chen #define GPIO_BANK_OFFSET 8 53cf344252SJoseph Chen #define GPIO_PIN_MASK 0x000000FF 54cf344252SJoseph Chen #define GPIO_PIN_OFFSET 0 55cf344252SJoseph Chen #define EINVAL_GPIO -1 56cf344252SJoseph Chen #define PIN_BASE GIC_IRQS_NR 57cf344252SJoseph Chen 58cf344252SJoseph Chen struct gpio_bank { 59cf344252SJoseph Chen char *name; 60cf344252SJoseph Chen void __iomem *regbase; 61cf344252SJoseph Chen int id; 62cf344252SJoseph Chen int irq_base; 63cf344252SJoseph Chen int ngpio; 64cf344252SJoseph Chen int use_count; 65cf344252SJoseph Chen }; 66cf344252SJoseph Chen 67cf344252SJoseph Chen #define GPIO_BANK_REGISTER(ID, GPIO_BANK_NUM) \ 68cf344252SJoseph Chen { \ 69cf344252SJoseph Chen .name = __stringify(gpio##ID), \ 70cf344252SJoseph Chen .regbase = (unsigned char __iomem *)GPIO##ID##_PHYS, \ 71cf344252SJoseph Chen .id = ID, \ 72cf344252SJoseph Chen .irq_base = PIN_BASE + (ID) * (GPIO_BANK_NUM), \ 73cf344252SJoseph Chen .ngpio = GPIO_BANK_NUM, \ 74cf344252SJoseph Chen .use_count = 0 \ 75cf344252SJoseph Chen } 76cf344252SJoseph Chen 77cf344252SJoseph Chen /* gpio bank[31:8] and pin[7:0] */ 78cf344252SJoseph Chen #define GPIO_BANK(gpio) ((gpio & GPIO_BANK_MASK) >> GPIO_BANK_OFFSET) 79cf344252SJoseph Chen #define GPIO_PIN(gpio) ((gpio & GPIO_PIN_MASK) >> GPIO_PIN_OFFSET) 80cf344252SJoseph Chen #define GPIO_BANK_VALID(gpio) (GPIO_BANK(gpio) < GPIO_BANK_NUM) 81cf344252SJoseph Chen #define GPIO_PIN_VALID(gpio) (GPIO_PIN(gpio) < GPIO_BANK_PINS) 82cf344252SJoseph Chen 83cf344252SJoseph Chen int hard_gpio_to_irq(u32 gpio); 84cf344252SJoseph Chen int irq_to_gpio(int irq); 85cf344252SJoseph Chen struct gpio_bank *gpio_id_to_bank(unsigned int id); 86cf344252SJoseph Chen struct gpio_bank *gpio_to_bank(unsigned gpio); 87cf344252SJoseph Chen 88cf344252SJoseph Chen void __generic_gpio_handle_irq(int irq); 89cf344252SJoseph Chen 90cf344252SJoseph Chen #endif /* _IRQ_GIC_H_ */ 91