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Searched refs:ccr (Results 1 – 25 of 52) sorted by relevance

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/rk3399_rockchip-uboot/drivers/rtc/
H A Dm48t35ax.c30 uchar ccr; /* Clock control register */ in rtc_get() local
33 ccr = rtc_read(0); in rtc_get()
34 ccr = ccr | 0x40; in rtc_get()
35 rtc_write(0, ccr); in rtc_get()
46 ccr = rtc_read(0); in rtc_get()
47 ccr = ccr & 0xBF; in rtc_get()
48 rtc_write(0, ccr); in rtc_get()
74 uchar ccr; /* Clock control register */ in rtc_set() local
82 ccr = rtc_read(0); in rtc_set()
83 ccr = ccr | 0x80; in rtc_set()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dcache.c211 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE)); in dcache_enable()
229 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE)); in dcache_disable()
238 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0; in dcache_status()
313 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_enable()
322 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0; in icache_status()
331 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_disable()
/rk3399_rockchip-uboot/arch/sh/cpu/sh4/
H A Dcache.c40 unsigned long ccr; in cache_control() local
43 ccr = inl(CCR); in cache_control()
45 if (ccr & CCR_CACHE_ENABLE) in cache_control()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c77 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
147 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || in setup_5445x_clocks()
148 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { in setup_5445x_clocks()
169 fbtemp = pPllmult[ccm->ccr & fbpll_mask]; in setup_5445x_clocks()
227 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; in setup_5445x_clocks()
238 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in setup_5445x_clocks()
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c116 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
123 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
392 setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); in dramc_scan_readpipe()
395 await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING); in dramc_scan_readpipe()
504 setbits_le32(&dram->ccr, DRAM_CCR_INIT); in mctl_ddr3_initialize()
505 await_bits_clear(&dram->ccr, DRAM_CCR_INIT); in mctl_ddr3_initialize()
631 await_bits_clear(&dram->ccr, DRAM_CCR_INIT); in dramc_init_helper()
656 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); in dramc_init_helper()
661 setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); in dramc_init_helper()
681 clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); in dramc_init_helper()
[all …]
H A Ddram_sun6i.c177 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_channel_init()
352 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in sunxi_dram_init()
356 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in sunxi_dram_init()
359 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); in sunxi_dram_init()
H A Ddram_sun9i.c303 setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30)); in mctl_sys_init()
333 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
336 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in mctl_sys_init()
338 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
H A Drsb.c55 writel((cd_odly << 8) | div, &rsb->ccr); in rsb_set_clk()
/rk3399_rockchip-uboot/board/ronetix/pm9g45/
H A Dpm9g45.c44 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; in pm9g45_nand_hw_init()
45 writel(csa, &matrix->ccr[6]); in pm9g45_nand_hw_init()
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm920t/
H A Dtimer.c39 writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); in timer_init()
47 writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); in timer_init()
/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dkgdb.c173 *ptr++ = regs->ccr; in kgdb_getregs()
206 case 66: regs->ccr = *ptr; break; in kgdb_putreg()
243 regs->ccr = *ptr++; in kgdb_putregs()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dftsdc010_mci.c115 writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr); in ftsdc010_clkset()
118 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD); in ftsdc010_clkset()
121 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD); in ftsdc010_clkset()
123 clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD); in ftsdc010_clkset()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Drsb.h20 u32 ccr; /* 0x04 */ member
H A Ddram_sun4i.h16 u32 ccr; /* 0x00 controller configuration register */ member
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dat91_tc.h11 u32 ccr; /* 0x00 Channel Control Register */ member
H A Dat91_matrix.h67 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ member
/rk3399_rockchip-uboot/drivers/spi/
H A Dstm32_qspi.c30 u32 ccr; /* 0x14 */ member
273 writel(ccr_reg, &priv->regs->ccr); in _stm32_qspi_enable_mmap()
291 writel(cr_reg, &priv->regs->ccr); in _stm32_qspi_start_xfer()
365 __func__, priv->regs->ccr, priv->regs->ar); in _stm32_qspi_xfer()
397 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); in _stm32_qspi_xfer()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h21 u32 ccr; /* Capture Control Register */ member
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darmv7m.h38 uint32_t ccr; /* offset 0x14: Config and Control Register */ member
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dptrace.h34 PPC_REG ccr; member
/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dasm-offsets.c60 OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ in main()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c108 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in get_clocks()
/rk3399_rockchip-uboot/arch/m68k/include/asm/coldfire/
H A Dssi.h23 u32 ccr; member
/rk3399_rockchip-uboot/include/faraday/
H A Dftsdc010.h31 unsigned int ccr; /* 0x38 - clock contorl reg */ member
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-armada100/
H A Dcpu.h44 u32 ccr; /* 0x004 */ member

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