152f69f81SVladimir Zapolskiy /* 252f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 352f69f81SVladimir Zapolskiy * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 552f69f81SVladimir Zapolskiy */ 652f69f81SVladimir Zapolskiy 752f69f81SVladimir Zapolskiy #ifndef _LPC32XX_TIMER_H 852f69f81SVladimir Zapolskiy #define _LPC32XX_TIMER_H 952f69f81SVladimir Zapolskiy 1052f69f81SVladimir Zapolskiy #include <asm/types.h> 1152f69f81SVladimir Zapolskiy 1252f69f81SVladimir Zapolskiy /* Timer/Counter Registers */ 1352f69f81SVladimir Zapolskiy struct timer_regs { 1452f69f81SVladimir Zapolskiy u32 ir; /* Interrupt Register */ 1552f69f81SVladimir Zapolskiy u32 tcr; /* Timer Control Register */ 1652f69f81SVladimir Zapolskiy u32 tc; /* Timer Counter */ 1752f69f81SVladimir Zapolskiy u32 pr; /* Prescale Register */ 1852f69f81SVladimir Zapolskiy u32 pc; /* Prescale Counter */ 1952f69f81SVladimir Zapolskiy u32 mcr; /* Match Control Register */ 2052f69f81SVladimir Zapolskiy u32 mr[4]; /* Match Registers */ 2152f69f81SVladimir Zapolskiy u32 ccr; /* Capture Control Register */ 2252f69f81SVladimir Zapolskiy u32 cr[4]; /* Capture Registers */ 2352f69f81SVladimir Zapolskiy u32 emr; /* External Match Register */ 2452f69f81SVladimir Zapolskiy u32 reserved[12]; 2552f69f81SVladimir Zapolskiy u32 ctcr; /* Count Control Register */ 2652f69f81SVladimir Zapolskiy }; 2752f69f81SVladimir Zapolskiy 2852f69f81SVladimir Zapolskiy /* Timer/Counter Interrupt Register bits */ 2952f69f81SVladimir Zapolskiy #define TIMER_IR_CR(n) (1 << ((n) + 4)) 3052f69f81SVladimir Zapolskiy #define TIMER_IR_MR(n) (1 << (n)) 3152f69f81SVladimir Zapolskiy 3252f69f81SVladimir Zapolskiy /* Timer/Counter Timer Control Register bits */ 3352f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_RESET (1 << 1) 3452f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_ENABLE (1 << 0) 3552f69f81SVladimir Zapolskiy #define TIMER_TCR_COUNTER_DISABLE (0 << 0) 3652f69f81SVladimir Zapolskiy 3752f69f81SVladimir Zapolskiy /* Timer/Counter Match Control Register bits */ 3852f69f81SVladimir Zapolskiy #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) 3952f69f81SVladimir Zapolskiy #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) 4052f69f81SVladimir Zapolskiy #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) 4152f69f81SVladimir Zapolskiy 4252f69f81SVladimir Zapolskiy /* Timer/Counter Capture Control Register bits */ 4352f69f81SVladimir Zapolskiy #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) 4452f69f81SVladimir Zapolskiy #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) 4552f69f81SVladimir Zapolskiy #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) 4652f69f81SVladimir Zapolskiy 4752f69f81SVladimir Zapolskiy /* Timer/Counter External Match Register bits */ 4852f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) 4952f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) 5052f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) 5152f69f81SVladimir Zapolskiy #define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) 5252f69f81SVladimir Zapolskiy #define TIMER_EMR_EM(n) (1 << (n)) 5352f69f81SVladimir Zapolskiy 5452f69f81SVladimir Zapolskiy /* Timer/Counter Count Control Register bits */ 5552f69f81SVladimir Zapolskiy #define TIMER_CTCR_INPUT(n) ((n) << 2) 5652f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) 5752f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) 5852f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) 5952f69f81SVladimir Zapolskiy #define TIMER_CTCR_MODE_TIMER (0x0 << 0) 6052f69f81SVladimir Zapolskiy 6152f69f81SVladimir Zapolskiy #endif /* _LPC32XX_TIMER_H */ 62