1*254d68b6SMasahiro Yamada /*
2*254d68b6SMasahiro Yamada * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3*254d68b6SMasahiro Yamada *
4*254d68b6SMasahiro Yamada * Generate definitions needed by assembly language modules.
5*254d68b6SMasahiro Yamada * This code generates raw asm output which is post-processed to extract
6*254d68b6SMasahiro Yamada * and format the required data.
7*254d68b6SMasahiro Yamada *
8*254d68b6SMasahiro Yamada * This program is free software; you can redistribute it and/or modify
9*254d68b6SMasahiro Yamada * it under the terms of the GNU General Public License version 2 as
10*254d68b6SMasahiro Yamada * published by the Free Software Foundation.
11*254d68b6SMasahiro Yamada */
12*254d68b6SMasahiro Yamada #include <common.h>
13*254d68b6SMasahiro Yamada
14*254d68b6SMasahiro Yamada #include <linux/kbuild.h>
15*254d68b6SMasahiro Yamada
main(void)16*254d68b6SMasahiro Yamada int main(void)
17*254d68b6SMasahiro Yamada {
18*254d68b6SMasahiro Yamada /*
19*254d68b6SMasahiro Yamada * TODO : Check if each entry in this file is really necessary.
20*254d68b6SMasahiro Yamada * - struct ftahbc02s
21*254d68b6SMasahiro Yamada * - struct ftsdmc021
22*254d68b6SMasahiro Yamada * - struct andes_pcu
23*254d68b6SMasahiro Yamada * - struct dwcddr21mctl
24*254d68b6SMasahiro Yamada * are used only for generating asm-offsets.h.
25*254d68b6SMasahiro Yamada * It means their offset addresses are referenced only from assembly
26*254d68b6SMasahiro Yamada * code. Is it better to define the macros directly in headers?
27*254d68b6SMasahiro Yamada */
28*254d68b6SMasahiro Yamada
29*254d68b6SMasahiro Yamada #ifdef CONFIG_FTSMC020
30*254d68b6SMasahiro Yamada OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
31*254d68b6SMasahiro Yamada OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
32*254d68b6SMasahiro Yamada #endif
33*254d68b6SMasahiro Yamada BLANK();
34*254d68b6SMasahiro Yamada #ifdef CONFIG_FTAHBC020S
35*254d68b6SMasahiro Yamada OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
36*254d68b6SMasahiro Yamada OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
37*254d68b6SMasahiro Yamada OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
38*254d68b6SMasahiro Yamada #endif
39*254d68b6SMasahiro Yamada BLANK();
40*254d68b6SMasahiro Yamada #ifdef CONFIG_FTPMU010
41*254d68b6SMasahiro Yamada OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
42*254d68b6SMasahiro Yamada #endif
43*254d68b6SMasahiro Yamada BLANK();
44*254d68b6SMasahiro Yamada #ifdef CONFIG_FTSDMC021
45*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
46*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
47*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
48*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
49*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
50*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
51*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
52*254d68b6SMasahiro Yamada OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
53*254d68b6SMasahiro Yamada #endif
54*254d68b6SMasahiro Yamada BLANK();
55*254d68b6SMasahiro Yamada #ifdef CONFIG_ANDES_PCU
56*254d68b6SMasahiro Yamada OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
57*254d68b6SMasahiro Yamada #endif
58*254d68b6SMasahiro Yamada BLANK();
59*254d68b6SMasahiro Yamada #ifdef CONFIG_DWCDDR21MCTL
60*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
61*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
62*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
63*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
64*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
65*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
66*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
67*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
68*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
69*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
70*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
71*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
72*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
73*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
74*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
75*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
76*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
77*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
78*254d68b6SMasahiro Yamada OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
79*254d68b6SMasahiro Yamada #endif
80*254d68b6SMasahiro Yamada
81*254d68b6SMasahiro Yamada return 0;
82*254d68b6SMasahiro Yamada }
83